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From: Pranith Kumar <bobby.prani@gmail.com>
To: Andrzej Zaborowski <balrogg@gmail.com>,
	Richard Henderson <rth@twiddle.net>,
	qemu-arm@nongnu.org (open list:ARM target),
	qemu-devel@nongnu.org (open list:All patches CC here)
Cc: qemu-devel@nongnu.org, alex.bennee@linaro.org,
	serge.fdrv@gmail.com, pbonzini@redhat.com,
	peter.maydell@linaro.org
Subject: [PATCH v4 04/14] tcg/arm: Add support for fence
Date: Thu, 14 Jul 2016 16:20:16 -0400	[thread overview]
Message-ID: <20160714202026.9727-5-bobby.prani@gmail.com> (raw)
In-Reply-To: <20160714202026.9727-1-bobby.prani@gmail.com>

Cc: Andrzej Zaborowski <balrogg@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/arm/tcg-target.inc.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index 172feba..4e66bcd 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -313,6 +313,10 @@ typedef enum {
     INSN_LDRD_REG  = 0x000000d0,
     INSN_STRD_IMM  = 0x004000f0,
     INSN_STRD_REG  = 0x000000f0,
+
+    INSN_DMB_ISH   = 0x5bf07ff5,
+    INSN_DMB_MCR   = 0xba0f07ee,
+
 } ARMInsn;
 
 #define SHIFT_IMM_LSL(im)	(((im) << 7) | 0x00)
@@ -1066,6 +1070,15 @@ static inline void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l)
     }
 }
 
+static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+    if (use_armv7_instructions) {
+        tcg_out32(s, INSN_DMB_ISH);
+    } else if (use_armv6_instructions) {
+        tcg_out32(s, INSN_DMB_MCR);
+    }
+}
+
 #ifdef CONFIG_SOFTMMU
 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
  *                                     int mmu_idx, uintptr_t ra)
@@ -1923,6 +1936,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
         tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]);
         break;
 
+    case INDEX_op_mb:
+        tcg_out_mb(s, args[0]);
+        break;
+
     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
     case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
     case INDEX_op_call:     /* Always emitted via tcg_out_call.  */
@@ -1997,6 +2014,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
     { INDEX_op_div_i32, { "r", "r", "r" } },
     { INDEX_op_divu_i32, { "r", "r", "r" } },
 
+    { INDEX_op_mb, { } },
     { -1 },
 };
 
-- 
2.9.0

WARNING: multiple messages have this Message-ID (diff)
From: Pranith Kumar <bobby.prani@gmail.com>
To: Andrzej Zaborowski <balrogg@gmail.com>,
	Richard Henderson <rth@twiddle.net>,
	"open list:ARM target" <qemu-arm@nongnu.org>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: alex.bennee@linaro.org, serge.fdrv@gmail.com,
	pbonzini@redhat.com, peter.maydell@linaro.org
Subject: [Qemu-devel] [PATCH v4 04/14] tcg/arm: Add support for fence
Date: Thu, 14 Jul 2016 16:20:16 -0400	[thread overview]
Message-ID: <20160714202026.9727-5-bobby.prani@gmail.com> (raw)
In-Reply-To: <20160714202026.9727-1-bobby.prani@gmail.com>

Cc: Andrzej Zaborowski <balrogg@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/arm/tcg-target.inc.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index 172feba..4e66bcd 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -313,6 +313,10 @@ typedef enum {
     INSN_LDRD_REG  = 0x000000d0,
     INSN_STRD_IMM  = 0x004000f0,
     INSN_STRD_REG  = 0x000000f0,
+
+    INSN_DMB_ISH   = 0x5bf07ff5,
+    INSN_DMB_MCR   = 0xba0f07ee,
+
 } ARMInsn;
 
 #define SHIFT_IMM_LSL(im)	(((im) << 7) | 0x00)
@@ -1066,6 +1070,15 @@ static inline void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l)
     }
 }
 
+static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+    if (use_armv7_instructions) {
+        tcg_out32(s, INSN_DMB_ISH);
+    } else if (use_armv6_instructions) {
+        tcg_out32(s, INSN_DMB_MCR);
+    }
+}
+
 #ifdef CONFIG_SOFTMMU
 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
  *                                     int mmu_idx, uintptr_t ra)
@@ -1923,6 +1936,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
         tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]);
         break;
 
+    case INDEX_op_mb:
+        tcg_out_mb(s, args[0]);
+        break;
+
     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
     case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
     case INDEX_op_call:     /* Always emitted via tcg_out_call.  */
@@ -1997,6 +2014,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
     { INDEX_op_div_i32, { "r", "r", "r" } },
     { INDEX_op_divu_i32, { "r", "r", "r" } },
 
+    { INDEX_op_mb, { } },
     { -1 },
 };
 
-- 
2.9.0

  parent reply	other threads:[~2016-07-14 20:20 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-07-14 20:20 [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 01/14] Introduce TCGOpcode for memory barrier Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 02/14] tcg/i386: Add support for fence Pranith Kumar
2016-07-14 20:20 ` [PATCH v4 03/14] tcg/aarch64: " Pranith Kumar
2016-07-14 20:20   ` [Qemu-devel] " Pranith Kumar
2016-07-14 20:20 ` Pranith Kumar [this message]
2016-07-14 20:20   ` [Qemu-devel] [PATCH v4 04/14] tcg/arm: " Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 05/14] tcg/ia64: " Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 06/14] tcg/mips: " Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 07/14] tcg/ppc: " Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 08/14] tcg/s390: " Pranith Kumar
2016-10-16  8:47   ` Stefan Hajnoczi
2016-10-16 16:17     ` Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 09/14] tcg/sparc: " Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 10/14] tcg/tci: " Pranith Kumar
2016-07-14 20:20 ` [PATCH v4 11/14] target-arm: Generate fences in ARMv7 frontend Pranith Kumar
2016-07-14 20:20   ` [Qemu-devel] " Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 12/14] target-alpha: Generate fence op Pranith Kumar
2016-07-14 20:20 ` [PATCH v4 13/14] target-aarch64: Generate fences for aarch64 Pranith Kumar
2016-07-14 20:20   ` [Qemu-devel] " Pranith Kumar
2016-07-14 20:20 ` [Qemu-devel] [PATCH v4 14/14] target-i386: Generate fences for x86 Pranith Kumar
2016-07-23 16:08 ` [Qemu-devel] [PATCH v4 00/14] tcg: Add support for fence generation Pranith Kumar
2016-07-23 17:34   ` Paolo Bonzini
2016-07-23 18:00     ` Pranith Kumar
2016-08-08 14:05 ` Pranith Kumar
2016-09-07 17:33 ` Richard Henderson

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