From: Mark Rutland <mark.rutland@arm.com>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
James Morse <james.morse@arm.com>,
Will Deacon <will.deacon@arm.com>,
Kees Cook <keescook@chromium.org>,
kernel-hardening@lists.openwall.com
Subject: [kernel-hardening] Re: [PATCH 4/7] arm64: Disable TTBR0_EL1 during normal kernel execution
Date: Mon, 15 Aug 2016 12:18:58 +0100 [thread overview]
Message-ID: <20160815111857.GA2060@svinekod> (raw)
In-Reply-To: <1471015666-23125-5-git-send-email-catalin.marinas@arm.com>
On Fri, Aug 12, 2016 at 04:27:43PM +0100, Catalin Marinas wrote:
> diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi/asm/ptrace.h
> index b5c3933ed441..9283e6b247f9 100644
> --- a/arch/arm64/include/uapi/asm/ptrace.h
> +++ b/arch/arm64/include/uapi/asm/ptrace.h
> @@ -52,6 +52,8 @@
> #define PSR_Z_BIT 0x40000000
> #define PSR_N_BIT 0x80000000
>
> +#define _PSR_PAN_BIT 22
Given this is under uapi/, shouldn't we lose the leading underscore to align
with other PSR_* definitions?
Or should we not have this under uapi/?
[...]
> + mrs lr, ttbr0_el1
> + tst lr, #0xffff << 48 // Check for the reserved ASID
Did we not have a regular register spare here? Not a problem, but using the lr
here stands out as unusual.
Thanks,
Mark.
WARNING: multiple messages have this Message-ID (diff)
From: mark.rutland@arm.com (Mark Rutland)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/7] arm64: Disable TTBR0_EL1 during normal kernel execution
Date: Mon, 15 Aug 2016 12:18:58 +0100 [thread overview]
Message-ID: <20160815111857.GA2060@svinekod> (raw)
In-Reply-To: <1471015666-23125-5-git-send-email-catalin.marinas@arm.com>
On Fri, Aug 12, 2016 at 04:27:43PM +0100, Catalin Marinas wrote:
> diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi/asm/ptrace.h
> index b5c3933ed441..9283e6b247f9 100644
> --- a/arch/arm64/include/uapi/asm/ptrace.h
> +++ b/arch/arm64/include/uapi/asm/ptrace.h
> @@ -52,6 +52,8 @@
> #define PSR_Z_BIT 0x40000000
> #define PSR_N_BIT 0x80000000
>
> +#define _PSR_PAN_BIT 22
Given this is under uapi/, shouldn't we lose the leading underscore to align
with other PSR_* definitions?
Or should we not have this under uapi/?
[...]
> + mrs lr, ttbr0_el1
> + tst lr, #0xffff << 48 // Check for the reserved ASID
Did we not have a regular register spare here? Not a problem, but using the lr
here stands out as unusual.
Thanks,
Mark.
next prev parent reply other threads:[~2016-08-15 11:18 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-12 15:27 [kernel-hardening] [PATCH 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching Catalin Marinas
2016-08-12 15:27 ` Catalin Marinas
2016-08-12 15:27 ` [kernel-hardening] [PATCH 1/7] arm64: Factor out PAN enabling/disabling into separate uaccess_* macros Catalin Marinas
2016-08-12 15:27 ` Catalin Marinas
2016-08-12 15:27 ` [kernel-hardening] [PATCH 2/7] arm64: Factor out TTBR0_EL1 setting into a specific asm macro Catalin Marinas
2016-08-12 15:27 ` Catalin Marinas
2016-08-12 15:27 ` [kernel-hardening] [PATCH 3/7] arm64: Introduce uaccess_{disable,enable} functionality based on TTBR0_EL1 Catalin Marinas
2016-08-12 15:27 ` [PATCH 3/7] arm64: Introduce uaccess_{disable, enable} " Catalin Marinas
2016-08-12 15:27 ` [kernel-hardening] [PATCH 4/7] arm64: Disable TTBR0_EL1 during normal kernel execution Catalin Marinas
2016-08-12 15:27 ` Catalin Marinas
2016-08-15 11:18 ` Mark Rutland [this message]
2016-08-15 11:18 ` Mark Rutland
2016-08-15 16:39 ` [kernel-hardening] " Catalin Marinas
2016-08-15 16:39 ` Catalin Marinas
2016-08-12 15:27 ` [kernel-hardening] [PATCH 5/7] arm64: Handle faults caused by inadvertent user access with PAN enabled Catalin Marinas
2016-08-12 15:27 ` Catalin Marinas
2016-08-12 15:27 ` [kernel-hardening] [PATCH 6/7] arm64: xen: Enable user access before a privcmd hvc call Catalin Marinas
2016-08-12 15:27 ` Catalin Marinas
2016-08-15 9:58 ` Julien Grall
2016-08-15 9:58 ` [kernel-hardening] " Julien Grall
2016-08-15 9:58 ` Julien Grall
2016-08-15 18:00 ` [kernel-hardening] " Stefano Stabellini
2016-08-15 18:00 ` Stefano Stabellini
2016-08-15 18:00 ` Stefano Stabellini
2016-08-12 15:27 ` [kernel-hardening] [PATCH 7/7] arm64: Enable CONFIG_ARM64_TTBR0_PAN Catalin Marinas
2016-08-12 15:27 ` Catalin Marinas
2016-08-12 18:04 ` [kernel-hardening] Re: [PATCH 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching Kees Cook
2016-08-12 18:04 ` Kees Cook
2016-08-12 18:22 ` [kernel-hardening] " Catalin Marinas
2016-08-12 18:22 ` Catalin Marinas
2016-08-13 9:13 ` [kernel-hardening] " Ard Biesheuvel
2016-08-13 9:13 ` Ard Biesheuvel
2016-08-15 9:48 ` Catalin Marinas
2016-08-15 9:48 ` Catalin Marinas
2016-08-15 9:58 ` Mark Rutland
2016-08-15 9:58 ` Mark Rutland
2016-08-15 10:02 ` Ard Biesheuvel
2016-08-15 10:02 ` Ard Biesheuvel
2016-08-15 10:06 ` Mark Rutland
2016-08-15 10:06 ` Mark Rutland
2016-08-15 10:10 ` Will Deacon
2016-08-15 10:10 ` Will Deacon
2016-08-15 10:15 ` Mark Rutland
2016-08-15 10:15 ` Mark Rutland
2016-08-15 10:21 ` Will Deacon
2016-08-15 10:21 ` Will Deacon
2016-08-15 10:21 ` Ard Biesheuvel
2016-08-15 10:21 ` Ard Biesheuvel
2016-08-15 10:30 ` Will Deacon
2016-08-15 10:30 ` Will Deacon
2016-08-15 10:31 ` Ard Biesheuvel
2016-08-15 10:31 ` Ard Biesheuvel
2016-08-15 10:37 ` Will Deacon
2016-08-15 10:37 ` Will Deacon
2016-08-15 10:43 ` Ard Biesheuvel
2016-08-15 10:43 ` Ard Biesheuvel
2016-08-15 10:52 ` Catalin Marinas
2016-08-15 10:52 ` Catalin Marinas
2016-08-15 10:56 ` Ard Biesheuvel
2016-08-15 10:56 ` Ard Biesheuvel
2016-08-15 11:02 ` Will Deacon
2016-08-15 11:02 ` Will Deacon
2016-08-15 16:13 ` Catalin Marinas
2016-08-15 16:13 ` Catalin Marinas
2016-08-15 19:04 ` Ard Biesheuvel
2016-08-15 19:04 ` Ard Biesheuvel
2016-08-15 11:00 ` Will Deacon
2016-08-15 11:00 ` Will Deacon
2016-08-15 10:30 ` Mark Rutland
2016-08-15 10:30 ` Mark Rutland
2016-08-15 10:08 ` Will Deacon
2016-08-15 10:08 ` Will Deacon
2016-08-26 15:39 ` David Brown
2016-08-26 15:39 ` David Brown
2016-08-26 17:24 ` Catalin Marinas
2016-08-26 17:24 ` Catalin Marinas
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