From: Christoffer Dall <christoffer.dall@linaro.org>
To: Christopher Covington <cov@codeaurora.org>
Cc: linux-doc@vger.kernel.org, kvm@vger.kernel.org,
Marc Zyngier <marc.zyngier@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
timur@codeaurora.org, Jonathan Corbet <corbet@lwn.net>,
Will Deacon <will.deacon@arm.com>,
linux-kernel@vger.kernel.org, Paolo Bonzini <pbonzini@redhat.com>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003
Date: Wed, 4 Jan 2017 11:33:22 +0100 [thread overview]
Message-ID: <20170104103322.GA20461@cbox> (raw)
In-Reply-To: <20161229224335.13531-2-cov@codeaurora.org>
On Thu, Dec 29, 2016 at 05:43:32PM -0500, Christopher Covington wrote:
> From: Shanker Donthineni <shankerd@codeaurora.org>
>
> On the Qualcomm Datacenter Technologies Falkor v1 CPU, memory accesses may
> allocate TLB entries using an incorrect ASID when TTBRx_EL1 is being
> updated. Changing the TTBRx_EL1[ASID] and TTBRx_EL1[BADDR] fields
> separately using a reserved ASID will ensure that there are no TLB entries
> with incorrect ASID after changing the the ASID.
When we restore guest state in KVM, we completely save and restore
TTBRx_EL1 from EL2. Would that be affected by this erratum?
Thanks,
-Christoffer
WARNING: multiple messages have this Message-ID (diff)
From: christoffer.dall@linaro.org (Christoffer Dall)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003
Date: Wed, 4 Jan 2017 11:33:22 +0100 [thread overview]
Message-ID: <20170104103322.GA20461@cbox> (raw)
In-Reply-To: <20161229224335.13531-2-cov@codeaurora.org>
On Thu, Dec 29, 2016 at 05:43:32PM -0500, Christopher Covington wrote:
> From: Shanker Donthineni <shankerd@codeaurora.org>
>
> On the Qualcomm Datacenter Technologies Falkor v1 CPU, memory accesses may
> allocate TLB entries using an incorrect ASID when TTBRx_EL1 is being
> updated. Changing the TTBRx_EL1[ASID] and TTBRx_EL1[BADDR] fields
> separately using a reserved ASID will ensure that there are no TLB entries
> with incorrect ASID after changing the the ASID.
When we restore guest state in KVM, we completely save and restore
TTBRx_EL1 from EL2. Would that be affected by this erratum?
Thanks,
-Christoffer
WARNING: multiple messages have this Message-ID (diff)
From: Christoffer Dall <christoffer.dall@linaro.org>
To: Christopher Covington <cov@codeaurora.org>
Cc: "Paolo Bonzini" <pbonzini@redhat.com>,
"Radim Krčmář" <rkrcmar@redhat.com>,
"Marc Zyngier" <marc.zyngier@arm.com>,
"Catalin Marinas" <catalin.marinas@arm.com>,
"Will Deacon" <will.deacon@arm.com>,
kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org,
shankerd@codeaurora.org, timur@codeaurora.org,
"Jonathan Corbet" <corbet@lwn.net>,
linux-doc@vger.kernel.org
Subject: Re: [PATCH v2 2/5] arm64: Work around Falkor erratum 1003
Date: Wed, 4 Jan 2017 11:33:22 +0100 [thread overview]
Message-ID: <20170104103322.GA20461@cbox> (raw)
In-Reply-To: <20161229224335.13531-2-cov@codeaurora.org>
On Thu, Dec 29, 2016 at 05:43:32PM -0500, Christopher Covington wrote:
> From: Shanker Donthineni <shankerd@codeaurora.org>
>
> On the Qualcomm Datacenter Technologies Falkor v1 CPU, memory accesses may
> allocate TLB entries using an incorrect ASID when TTBRx_EL1 is being
> updated. Changing the TTBRx_EL1[ASID] and TTBRx_EL1[BADDR] fields
> separately using a reserved ASID will ensure that there are no TLB entries
> with incorrect ASID after changing the the ASID.
When we restore guest state in KVM, we completely save and restore
TTBRx_EL1 from EL2. Would that be affected by this erratum?
Thanks,
-Christoffer
next prev parent reply other threads:[~2017-01-04 10:31 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-29 22:43 [PATCH v2 1/5] arm64: Define Falkor v1 CPU Christopher Covington
2016-12-29 22:43 ` Christopher Covington
2016-12-29 22:43 ` Christopher Covington
2016-12-29 22:43 ` [PATCH v2 2/5] arm64: Work around Falkor erratum 1003 Christopher Covington
2016-12-29 22:43 ` Christopher Covington
2016-12-29 22:43 ` Christopher Covington
2016-12-29 23:02 ` Timur Tabi
2016-12-29 23:02 ` Timur Tabi
2017-01-06 15:39 ` Christopher Covington
2017-01-06 15:39 ` Christopher Covington
2017-01-06 15:51 ` Timur Tabi
2017-01-06 15:51 ` Timur Tabi
2016-12-29 23:08 ` Timur Tabi
2016-12-29 23:08 ` Timur Tabi
2017-01-06 15:44 ` Christopher Covington
2017-01-06 15:44 ` Christopher Covington
2017-01-06 15:49 ` Timur Tabi
2017-01-06 15:49 ` Timur Tabi
2016-12-30 2:44 ` kbuild test robot
2016-12-30 2:44 ` kbuild test robot
2016-12-30 2:44 ` kbuild test robot
2017-01-03 15:55 ` Mark Rutland
2017-01-03 15:55 ` Mark Rutland
2017-01-03 15:55 ` Mark Rutland
2017-01-06 15:49 ` Christopher Covington
2017-01-06 15:49 ` Christopher Covington
2017-01-06 15:49 ` Christopher Covington
2017-01-04 10:33 ` Christoffer Dall [this message]
2017-01-04 10:33 ` Christoffer Dall
2017-01-04 10:33 ` Christoffer Dall
2017-01-11 13:11 ` Christopher Covington
2017-01-11 13:11 ` Christopher Covington
2017-01-11 13:11 ` Christopher Covington
2016-12-29 22:43 ` [PATCH v2 3/5] arm64: Create and use __tlbi_dsb() macros Christopher Covington
2016-12-29 22:43 ` Christopher Covington
2016-12-29 22:43 ` Christopher Covington
2016-12-29 22:43 ` [PATCH v2 4/5] arm64: Use __tlbi_dsb() macros in KVM code Christopher Covington
2016-12-29 22:43 ` Christopher Covington
2016-12-29 22:43 ` Christopher Covington
2017-01-03 15:57 ` Mark Rutland
2017-01-03 15:57 ` Mark Rutland
2017-01-03 15:57 ` Mark Rutland
2017-01-06 15:51 ` Christopher Covington
2017-01-06 15:51 ` Christopher Covington
2017-01-06 16:05 ` Mark Rutland
2017-01-06 16:05 ` Mark Rutland
2017-01-06 16:05 ` Mark Rutland
2016-12-29 22:43 ` [PATCH v2 5/5] arm64: Work around Falkor erratum 1009 Christopher Covington
2016-12-29 22:43 ` Christopher Covington
2016-12-29 22:43 ` Christopher Covington
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