From: Stephen Boyd <sboyd@codeaurora.org>
To: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Arnd Bergmann <arnd@arndb.de>, Mark Brown <broonie@kernel.org>,
Xiaolong Zhang <xiaolong.zhang@spreadtrum.com>,
Orson Zhai <orson.zhai@spreadtrum.com>,
Geng Ren <geng.ren@spreadtrum.com>,
Chunyan Zhang <zhang.lyra@gmail.com>
Subject: Re: [PATCH V1 8/9] clk: sprd: add clocks support for SC9860
Date: Mon, 19 Jun 2017 18:41:37 -0700 [thread overview]
Message-ID: <20170620014137.GK4493@codeaurora.org> (raw)
In-Reply-To: <20170618015855.27738-9-chunyan.zhang@spreadtrum.com>
On 06/18, Chunyan Zhang wrote:
> diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile
> index c593a93..0d90b40 100644
> --- a/drivers/clk/sprd/Makefile
> +++ b/drivers/clk/sprd/Makefile
> @@ -1,3 +1,4 @@
> ifneq ($(CONFIG_OF),)
> obj-y += ccu_common.o ccu_gate.o ccu_mux.o ccu_div.o ccu_composite.o ccu_pll.o
> +obj-y += ccu-sc9860.o
And a Kconfig for this SoC specific driver.
> endif
> diff --git a/drivers/clk/sprd/ccu-sc9860.c b/drivers/clk/sprd/ccu-sc9860.c
> new file mode 100644
> index 0000000..6cd4dc5
> --- /dev/null
> +++ b/drivers/clk/sprd/ccu-sc9860.c
> +
> +static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
> + 6, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
> + 13, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
> + 26, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
> + 104, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
> + 1, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
> + 1, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
> + 4, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_rco_4m, "rco-4m", "ext-rc0-100m",
> + 25, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_rco_2m, "rco-2m", "ext-rc0-100m",
> + 50, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_3k2, "fac-3k2", "ext-32k",
> + 10, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_1k, "fac-1k", "ext-32k",
> + 32, 1, CLK_IS_BASIC);
> +
> +#define SC9860_GATE_FLAGS (CLK_IGNORE_UNUSED | CLK_IS_BASIC)
No CLK_IS_BASIC. Why is everything marked as CLK_IGNORE_UNUSED?
> +static SPRD_CCU_GATE(rpll0_gate, "rpll0-gate", "ext-26m", 0x402b016c,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(rpll1_gate, "rpll1-gate", "ext-26m", 0x402b016c,
> + 0x1000, BIT(18), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(mpll0_gate, "mpll0-gate", "ext-26m", 0x402b00b0,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(mpll1_gate, "mpll1-gate", "ext-26m", 0x402b00b0,
> + 0x1000, BIT(18), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(dpll0_gate, "dpll0-gate", "ext-26m", 0x402b00b4,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(dpll1_gate, "dpll1-gate", "ext-26m", 0x402b00b4,
> + 0x1000, BIT(18), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(gpll_gate, "gpll-gate", "ext-26m", 0x402b032c,
> + 0x1000, BIT(0), SC9860_GATE_FLAGS,
> + CLK_GATE_SET_TO_DISABLE);
> +static SPRD_CCU_GATE(cppll_gate, "cppll-gate", "ext-26m", 0x402b02b4,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(ltepll0_gate, "ltepll0-gate", "ext-26m", 0x402b00b8,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(ltepll1_gate, "ltepll1-gate", "ext-26m", 0x402b010c,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(twpll_gate, "twpll-gate", "ext-26m", 0x402b00bc,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(sdio0_2x_en, "sdio0-2x-en", 0x402e013c,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(sdio0_1x_en, "sdio0-1x-en", 0x402e013c,
> + 0x1000, BIT(3), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(sdio1_2x_en, "sdio1-2x-en", 0x402e013c,
> + 0x1000, BIT(4), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(sdio1_1x_en, "sdio1-1x-en", 0x402e013c,
> + 0x1000, BIT(5), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(sdio2_2x_en, "sdio2-2x-en", 0x402e013c,
> + 0x1000, BIT(6), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(sdio2_1x_en, "sdio2-1x-en", 0x402e013c,
> + 0x1000, BIT(7), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(emmc_1x_en, "emmc-1x-en", 0x402e013c,
> + 0x1000, BIT(8), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(emmc_2x_en, "emmc-2x-en", 0x402e013c,
> + 0x1000, BIT(9), SC9860_GATE_FLAGS, 0);
> +
> +/* GPLL/LPLL/DPLL/RPLL/CPLL */
> +static const u64 const itable1[4] = {3, 780000000, 988000000, 1196000000};
> +
> +/* TWPLL/MPLL0/MPLL1 */
> +static const u64 itable2[4] = {3, 1638000000, 2080000000, 2600000000UL};
> +
> +static const struct ccu_bit_field const f_rpll[PLL_FACT_MAX] = {
> + { .shift = 0, .width = 1 }, /* lock_done */
> + { .shift = 3, .width = 1 }, /* div_s */
> + { .shift = 80, .width = 1 }, /* mod_en */
Are they even shifts? Or offsets from some base? I have to go
back and read the other patch.
> + { .shift = 81, .width = 1 }, /* sdm_en */
> + { .shift = 0, .width = 0 }, /* refin */
> + { .shift = 14, .width = 2 }, /* ibias */
> + { .shift = 16, .width = 7 }, /* n */
> + { .shift = 4, .width = 7 }, /* nint */
> + { .shift = 32, .width = 23}, /* kint */
> + { .shift = 0, .width = 0 }, /* prediv */
> + { .shift = 0, .width = 0 }, /* postdiv */
> +};
> +static const u32 const regs_rpll0[4] = { 3, 0x44, 0x48, 0x4c };
> +static SPRD_CCU_PLL_WITH_ITABLE(rpll0_clk, "rpll0", "rpll0-gate", 0x40400044,
> + regs_rpll0, itable1, 200, f_rpll);
> +
> +static const u32 const regs_rpll1[4] = { 3, 0x50, 0x54, 0x58 };
> +static SPRD_CCU_PLL_WITH_ITABLE(rpll1_clk, "rpll1", "rpll1-gate", 0x40400050,
> + regs_rpll1, itable1, 200, f_rpll);
> +
> +static const struct ccu_bit_field const f_mpll0[PLL_FACT_MAX] = {
[...]
> diff --git a/include/dt-bindings/clock/sc9860-ccu.h b/include/dt-bindings/clock/sc9860-ccu.h
> new file mode 100644
> index 0000000..dd7ccf9
> --- /dev/null
> +++ b/include/dt-bindings/clock/sc9860-ccu.h
> @@ -0,0 +1,19 @@
> +/*
> + * Spreadtrum SC9860 platform clocks
> + *
> + * Copyright (C) 2017, Spreadtrum Communications Inc.
> + *
> + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_SC9860_CCU_H_
> +#define _DT_BINDINGS_CLK_SC9860_CCU_H_
> +
> +#define CLK_FAC_1M 2
> +#define CLK_EMMC_2X_EN 29
> +#define CLK_L0_409M6 60
> +#define CLK_EMMC_2X 88
> +#define CLK_EMMC_EB 158
Why are only a handful exposed in the header file? Not exposing
everything is mostly a maintenance nightmare right now.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH V1 8/9] clk: sprd: add clocks support for SC9860
Date: Mon, 19 Jun 2017 18:41:37 -0700 [thread overview]
Message-ID: <20170620014137.GK4493@codeaurora.org> (raw)
In-Reply-To: <20170618015855.27738-9-chunyan.zhang@spreadtrum.com>
On 06/18, Chunyan Zhang wrote:
> diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile
> index c593a93..0d90b40 100644
> --- a/drivers/clk/sprd/Makefile
> +++ b/drivers/clk/sprd/Makefile
> @@ -1,3 +1,4 @@
> ifneq ($(CONFIG_OF),)
> obj-y += ccu_common.o ccu_gate.o ccu_mux.o ccu_div.o ccu_composite.o ccu_pll.o
> +obj-y += ccu-sc9860.o
And a Kconfig for this SoC specific driver.
> endif
> diff --git a/drivers/clk/sprd/ccu-sc9860.c b/drivers/clk/sprd/ccu-sc9860.c
> new file mode 100644
> index 0000000..6cd4dc5
> --- /dev/null
> +++ b/drivers/clk/sprd/ccu-sc9860.c
> +
> +static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
> + 6, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
> + 13, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
> + 26, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
> + 104, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
> + 1, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
> + 1, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
> + 4, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_rco_4m, "rco-4m", "ext-rc0-100m",
> + 25, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_rco_2m, "rco-2m", "ext-rc0-100m",
> + 50, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_3k2, "fac-3k2", "ext-32k",
> + 10, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_1k, "fac-1k", "ext-32k",
> + 32, 1, CLK_IS_BASIC);
> +
> +#define SC9860_GATE_FLAGS (CLK_IGNORE_UNUSED | CLK_IS_BASIC)
No CLK_IS_BASIC. Why is everything marked as CLK_IGNORE_UNUSED?
> +static SPRD_CCU_GATE(rpll0_gate, "rpll0-gate", "ext-26m", 0x402b016c,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(rpll1_gate, "rpll1-gate", "ext-26m", 0x402b016c,
> + 0x1000, BIT(18), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(mpll0_gate, "mpll0-gate", "ext-26m", 0x402b00b0,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(mpll1_gate, "mpll1-gate", "ext-26m", 0x402b00b0,
> + 0x1000, BIT(18), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(dpll0_gate, "dpll0-gate", "ext-26m", 0x402b00b4,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(dpll1_gate, "dpll1-gate", "ext-26m", 0x402b00b4,
> + 0x1000, BIT(18), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(gpll_gate, "gpll-gate", "ext-26m", 0x402b032c,
> + 0x1000, BIT(0), SC9860_GATE_FLAGS,
> + CLK_GATE_SET_TO_DISABLE);
> +static SPRD_CCU_GATE(cppll_gate, "cppll-gate", "ext-26m", 0x402b02b4,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(ltepll0_gate, "ltepll0-gate", "ext-26m", 0x402b00b8,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(ltepll1_gate, "ltepll1-gate", "ext-26m", 0x402b010c,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(twpll_gate, "twpll-gate", "ext-26m", 0x402b00bc,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(sdio0_2x_en, "sdio0-2x-en", 0x402e013c,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(sdio0_1x_en, "sdio0-1x-en", 0x402e013c,
> + 0x1000, BIT(3), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(sdio1_2x_en, "sdio1-2x-en", 0x402e013c,
> + 0x1000, BIT(4), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(sdio1_1x_en, "sdio1-1x-en", 0x402e013c,
> + 0x1000, BIT(5), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(sdio2_2x_en, "sdio2-2x-en", 0x402e013c,
> + 0x1000, BIT(6), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(sdio2_1x_en, "sdio2-1x-en", 0x402e013c,
> + 0x1000, BIT(7), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(emmc_1x_en, "emmc-1x-en", 0x402e013c,
> + 0x1000, BIT(8), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(emmc_2x_en, "emmc-2x-en", 0x402e013c,
> + 0x1000, BIT(9), SC9860_GATE_FLAGS, 0);
> +
> +/* GPLL/LPLL/DPLL/RPLL/CPLL */
> +static const u64 const itable1[4] = {3, 780000000, 988000000, 1196000000};
> +
> +/* TWPLL/MPLL0/MPLL1 */
> +static const u64 itable2[4] = {3, 1638000000, 2080000000, 2600000000UL};
> +
> +static const struct ccu_bit_field const f_rpll[PLL_FACT_MAX] = {
> + { .shift = 0, .width = 1 }, /* lock_done */
> + { .shift = 3, .width = 1 }, /* div_s */
> + { .shift = 80, .width = 1 }, /* mod_en */
Are they even shifts? Or offsets from some base? I have to go
back and read the other patch.
> + { .shift = 81, .width = 1 }, /* sdm_en */
> + { .shift = 0, .width = 0 }, /* refin */
> + { .shift = 14, .width = 2 }, /* ibias */
> + { .shift = 16, .width = 7 }, /* n */
> + { .shift = 4, .width = 7 }, /* nint */
> + { .shift = 32, .width = 23}, /* kint */
> + { .shift = 0, .width = 0 }, /* prediv */
> + { .shift = 0, .width = 0 }, /* postdiv */
> +};
> +static const u32 const regs_rpll0[4] = { 3, 0x44, 0x48, 0x4c };
> +static SPRD_CCU_PLL_WITH_ITABLE(rpll0_clk, "rpll0", "rpll0-gate", 0x40400044,
> + regs_rpll0, itable1, 200, f_rpll);
> +
> +static const u32 const regs_rpll1[4] = { 3, 0x50, 0x54, 0x58 };
> +static SPRD_CCU_PLL_WITH_ITABLE(rpll1_clk, "rpll1", "rpll1-gate", 0x40400050,
> + regs_rpll1, itable1, 200, f_rpll);
> +
> +static const struct ccu_bit_field const f_mpll0[PLL_FACT_MAX] = {
[...]
> diff --git a/include/dt-bindings/clock/sc9860-ccu.h b/include/dt-bindings/clock/sc9860-ccu.h
> new file mode 100644
> index 0000000..dd7ccf9
> --- /dev/null
> +++ b/include/dt-bindings/clock/sc9860-ccu.h
> @@ -0,0 +1,19 @@
> +/*
> + * Spreadtrum SC9860 platform clocks
> + *
> + * Copyright (C) 2017, Spreadtrum Communications Inc.
> + *
> + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_SC9860_CCU_H_
> +#define _DT_BINDINGS_CLK_SC9860_CCU_H_
> +
> +#define CLK_FAC_1M 2
> +#define CLK_EMMC_2X_EN 29
> +#define CLK_L0_409M6 60
> +#define CLK_EMMC_2X 88
> +#define CLK_EMMC_EB 158
Why are only a handful exposed in the header file? Not exposing
everything is mostly a maintenance nightmare right now.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
To: Chunyan Zhang <chunyan.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>
Cc: Michael Turquette
<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>,
Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Xiaolong Zhang
<xiaolong.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>,
Orson Zhai <orson.zhai-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>,
Geng Ren <geng.ren-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>,
Chunyan Zhang
<zhang.lyra-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Subject: Re: [PATCH V1 8/9] clk: sprd: add clocks support for SC9860
Date: Mon, 19 Jun 2017 18:41:37 -0700 [thread overview]
Message-ID: <20170620014137.GK4493@codeaurora.org> (raw)
In-Reply-To: <20170618015855.27738-9-chunyan.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>
On 06/18, Chunyan Zhang wrote:
> diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile
> index c593a93..0d90b40 100644
> --- a/drivers/clk/sprd/Makefile
> +++ b/drivers/clk/sprd/Makefile
> @@ -1,3 +1,4 @@
> ifneq ($(CONFIG_OF),)
> obj-y += ccu_common.o ccu_gate.o ccu_mux.o ccu_div.o ccu_composite.o ccu_pll.o
> +obj-y += ccu-sc9860.o
And a Kconfig for this SoC specific driver.
> endif
> diff --git a/drivers/clk/sprd/ccu-sc9860.c b/drivers/clk/sprd/ccu-sc9860.c
> new file mode 100644
> index 0000000..6cd4dc5
> --- /dev/null
> +++ b/drivers/clk/sprd/ccu-sc9860.c
> +
> +static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
> + 6, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
> + 13, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
> + 26, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
> + 104, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
> + 1, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
> + 1, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
> + 4, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_rco_4m, "rco-4m", "ext-rc0-100m",
> + 25, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_rco_2m, "rco-2m", "ext-rc0-100m",
> + 50, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_3k2, "fac-3k2", "ext-32k",
> + 10, 1, CLK_IS_BASIC);
> +static CLK_FIXED_FACTOR(fac_1k, "fac-1k", "ext-32k",
> + 32, 1, CLK_IS_BASIC);
> +
> +#define SC9860_GATE_FLAGS (CLK_IGNORE_UNUSED | CLK_IS_BASIC)
No CLK_IS_BASIC. Why is everything marked as CLK_IGNORE_UNUSED?
> +static SPRD_CCU_GATE(rpll0_gate, "rpll0-gate", "ext-26m", 0x402b016c,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(rpll1_gate, "rpll1-gate", "ext-26m", 0x402b016c,
> + 0x1000, BIT(18), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(mpll0_gate, "mpll0-gate", "ext-26m", 0x402b00b0,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(mpll1_gate, "mpll1-gate", "ext-26m", 0x402b00b0,
> + 0x1000, BIT(18), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(dpll0_gate, "dpll0-gate", "ext-26m", 0x402b00b4,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(dpll1_gate, "dpll1-gate", "ext-26m", 0x402b00b4,
> + 0x1000, BIT(18), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(gpll_gate, "gpll-gate", "ext-26m", 0x402b032c,
> + 0x1000, BIT(0), SC9860_GATE_FLAGS,
> + CLK_GATE_SET_TO_DISABLE);
> +static SPRD_CCU_GATE(cppll_gate, "cppll-gate", "ext-26m", 0x402b02b4,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(ltepll0_gate, "ltepll0-gate", "ext-26m", 0x402b00b8,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(ltepll1_gate, "ltepll1-gate", "ext-26m", 0x402b010c,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE(twpll_gate, "twpll-gate", "ext-26m", 0x402b00bc,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(sdio0_2x_en, "sdio0-2x-en", 0x402e013c,
> + 0x1000, BIT(2), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(sdio0_1x_en, "sdio0-1x-en", 0x402e013c,
> + 0x1000, BIT(3), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(sdio1_2x_en, "sdio1-2x-en", 0x402e013c,
> + 0x1000, BIT(4), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(sdio1_1x_en, "sdio1-1x-en", 0x402e013c,
> + 0x1000, BIT(5), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(sdio2_2x_en, "sdio2-2x-en", 0x402e013c,
> + 0x1000, BIT(6), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(sdio2_1x_en, "sdio2-1x-en", 0x402e013c,
> + 0x1000, BIT(7), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(emmc_1x_en, "emmc-1x-en", 0x402e013c,
> + 0x1000, BIT(8), SC9860_GATE_FLAGS, 0);
> +static SPRD_CCU_GATE_NO_PARENT(emmc_2x_en, "emmc-2x-en", 0x402e013c,
> + 0x1000, BIT(9), SC9860_GATE_FLAGS, 0);
> +
> +/* GPLL/LPLL/DPLL/RPLL/CPLL */
> +static const u64 const itable1[4] = {3, 780000000, 988000000, 1196000000};
> +
> +/* TWPLL/MPLL0/MPLL1 */
> +static const u64 itable2[4] = {3, 1638000000, 2080000000, 2600000000UL};
> +
> +static const struct ccu_bit_field const f_rpll[PLL_FACT_MAX] = {
> + { .shift = 0, .width = 1 }, /* lock_done */
> + { .shift = 3, .width = 1 }, /* div_s */
> + { .shift = 80, .width = 1 }, /* mod_en */
Are they even shifts? Or offsets from some base? I have to go
back and read the other patch.
> + { .shift = 81, .width = 1 }, /* sdm_en */
> + { .shift = 0, .width = 0 }, /* refin */
> + { .shift = 14, .width = 2 }, /* ibias */
> + { .shift = 16, .width = 7 }, /* n */
> + { .shift = 4, .width = 7 }, /* nint */
> + { .shift = 32, .width = 23}, /* kint */
> + { .shift = 0, .width = 0 }, /* prediv */
> + { .shift = 0, .width = 0 }, /* postdiv */
> +};
> +static const u32 const regs_rpll0[4] = { 3, 0x44, 0x48, 0x4c };
> +static SPRD_CCU_PLL_WITH_ITABLE(rpll0_clk, "rpll0", "rpll0-gate", 0x40400044,
> + regs_rpll0, itable1, 200, f_rpll);
> +
> +static const u32 const regs_rpll1[4] = { 3, 0x50, 0x54, 0x58 };
> +static SPRD_CCU_PLL_WITH_ITABLE(rpll1_clk, "rpll1", "rpll1-gate", 0x40400050,
> + regs_rpll1, itable1, 200, f_rpll);
> +
> +static const struct ccu_bit_field const f_mpll0[PLL_FACT_MAX] = {
[...]
> diff --git a/include/dt-bindings/clock/sc9860-ccu.h b/include/dt-bindings/clock/sc9860-ccu.h
> new file mode 100644
> index 0000000..dd7ccf9
> --- /dev/null
> +++ b/include/dt-bindings/clock/sc9860-ccu.h
> @@ -0,0 +1,19 @@
> +/*
> + * Spreadtrum SC9860 platform clocks
> + *
> + * Copyright (C) 2017, Spreadtrum Communications Inc.
> + *
> + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_SC9860_CCU_H_
> +#define _DT_BINDINGS_CLK_SC9860_CCU_H_
> +
> +#define CLK_FAC_1M 2
> +#define CLK_EMMC_2X_EN 29
> +#define CLK_L0_409M6 60
> +#define CLK_EMMC_2X 88
> +#define CLK_EMMC_EB 158
Why are only a handful exposed in the header file? Not exposing
everything is mostly a maintenance nightmare right now.
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next prev parent reply other threads:[~2017-06-20 1:41 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-18 1:58 [PATCH V1 0/9] add clock driver for Spreadtrum platforms Chunyan Zhang
2017-06-18 1:58 ` Chunyan Zhang
2017-06-18 1:58 ` Chunyan Zhang
2017-06-18 1:58 ` [PATCH V1 1/9] dt-bindings: Add Spreadtrum CCU binding documentation Chunyan Zhang
2017-06-18 1:58 ` Chunyan Zhang
2017-06-18 1:58 ` Chunyan Zhang
2017-06-23 20:05 ` Rob Herring
2017-06-23 20:05 ` Rob Herring
2017-06-18 1:58 ` [PATCH V1 2/9] clk: sprd: Add common infrastructure Chunyan Zhang
2017-06-18 1:58 ` Chunyan Zhang
2017-06-18 1:58 ` Chunyan Zhang
2017-06-20 1:29 ` Stephen Boyd
2017-06-20 1:29 ` Stephen Boyd
2017-06-22 10:12 ` Chunyan Zhang
2017-06-22 10:12 ` Chunyan Zhang
2017-06-18 1:58 ` [PATCH V1 3/9] clk: sprd: add gate clock support Chunyan Zhang
2017-06-18 1:58 ` Chunyan Zhang
2017-06-18 1:58 ` Chunyan Zhang
2017-06-20 1:31 ` Stephen Boyd
2017-06-20 1:31 ` Stephen Boyd
2017-06-20 1:31 ` Stephen Boyd
2017-06-22 10:16 ` Chunyan Zhang
2017-06-22 10:16 ` Chunyan Zhang
2017-06-30 1:43 ` Stephen Boyd
2017-06-30 1:43 ` Stephen Boyd
2017-06-30 1:43 ` Stephen Boyd
2017-06-18 1:58 ` [PATCH V1 4/9] clk: sprd: add mux " Chunyan Zhang
2017-06-18 1:58 ` Chunyan Zhang
2017-06-18 1:58 ` Chunyan Zhang
2017-06-18 1:58 ` [PATCH V1 5/9] clk: sprd: add divider " Chunyan Zhang
2017-06-18 1:58 ` Chunyan Zhang
2017-06-18 1:58 ` Chunyan Zhang
2017-06-18 1:58 ` [PATCH V1 6/9] clk: sprd: add composite " Chunyan Zhang
2017-06-18 1:58 ` Chunyan Zhang
2017-06-18 1:58 ` Chunyan Zhang
2017-06-19 0:13 ` kbuild test robot
2017-06-19 0:13 ` kbuild test robot
2017-06-19 0:13 ` kbuild test robot
2017-06-18 1:58 ` [PATCH V1 7/9] clk: sprd: add adjustable pll support Chunyan Zhang
2017-06-18 1:58 ` Chunyan Zhang
2017-06-18 1:58 ` Chunyan Zhang
2017-06-20 1:37 ` Stephen Boyd
2017-06-20 1:37 ` Stephen Boyd
2017-06-22 10:17 ` Chunyan Zhang
2017-06-22 10:17 ` Chunyan Zhang
2017-06-22 10:17 ` Chunyan Zhang
2017-06-22 11:15 ` Arnd Bergmann
2017-06-22 11:15 ` Arnd Bergmann
2017-06-22 12:06 ` Chunyan Zhang
2017-06-22 12:06 ` Chunyan Zhang
2017-06-30 1:44 ` Stephen Boyd
2017-06-30 1:44 ` Stephen Boyd
2017-06-30 1:44 ` Stephen Boyd
2017-06-30 7:55 ` Chunyan Zhang
2017-06-30 7:55 ` Chunyan Zhang
2017-06-30 19:22 ` Stephen Boyd
2017-06-30 19:22 ` Stephen Boyd
2017-07-03 7:41 ` Chunyan Zhang
2017-07-03 7:41 ` Chunyan Zhang
2017-07-03 7:41 ` Chunyan Zhang
2017-06-18 1:58 ` [PATCH V1 8/9] clk: sprd: add clocks support for SC9860 Chunyan Zhang
2017-06-18 1:58 ` Chunyan Zhang
2017-06-18 1:58 ` Chunyan Zhang
2017-06-20 1:41 ` Stephen Boyd [this message]
2017-06-20 1:41 ` Stephen Boyd
2017-06-20 1:41 ` Stephen Boyd
2017-06-22 10:21 ` Chunyan Zhang
2017-06-22 10:21 ` Chunyan Zhang
2017-06-30 1:41 ` Stephen Boyd
2017-06-30 1:41 ` Stephen Boyd
2017-06-30 1:41 ` Stephen Boyd
2017-06-18 1:58 ` [PATCH V1 9/9] arm64: dts: add ccu " Chunyan Zhang
2017-06-18 1:58 ` Chunyan Zhang
2017-06-18 1:58 ` Chunyan Zhang
2017-06-20 1:24 ` Stephen Boyd
2017-06-20 1:24 ` Stephen Boyd
2017-06-22 10:24 ` Chunyan Zhang
2017-06-22 10:24 ` Chunyan Zhang
2017-06-22 10:24 ` Chunyan Zhang
2017-06-30 0:57 ` Stephen Boyd
2017-06-30 0:57 ` Stephen Boyd
2017-06-30 7:37 ` Chunyan Zhang
2017-06-30 7:37 ` Chunyan Zhang
2017-06-20 1:25 ` [PATCH V1 0/9] add clock driver for Spreadtrum platforms Stephen Boyd
2017-06-20 1:25 ` Stephen Boyd
2017-06-22 10:07 ` Chunyan Zhang
2017-06-22 10:07 ` Chunyan Zhang
2017-06-30 0:45 ` Stephen Boyd
2017-06-30 0:45 ` Stephen Boyd
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