Re: [PATCH V3 11/12] PCI: tegra: Increase the deskew retry time

[Thierry Reding <thierry.reding@gmail.com>]

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On Mon, Oct 30, 2017 at 07:27:22PM +0530, Manikanta Maddireddy wrote:
> Some times Gen2 to Gen1 link speed switching fails due to instability in
> deskew logic on lane0 in Tegra210. Increase the deskew retry time to
> resolve this issue.
> 
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> V3:
> * no change in this patch
> V2:
> * no change in this patch
> 
>  drivers/pci/host/pci-tegra.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> index 3993e9221c96..b29329226e3d 100644
> --- a/drivers/pci/host/pci-tegra.c
> +++ b/drivers/pci/host/pci-tegra.c
> @@ -224,6 +224,10 @@
>  #define  RP_VEND_XP_OPPORTUNISTIC_UPDATEFC	(1 << 28)
>  #define  RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK	(0xff << 18)
>  
> +#define RP_VEND_CTL0	0xf44
> +#define  RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK	(0xf << 12)
> +#define  RP_VEND_CTL0_DSK_RST_PULSE_WIDTH	(0x9 << 12)
> +
>  #define RP_VEND_CTL1	0xf48
>  #define  RP_VEND_CTL1_ERPT	(1 << 13)
>  
> @@ -318,6 +322,7 @@ struct tegra_pcie_soc {
>  	bool program_ectl_settings;
>  	bool update_clamp_threshold;
>  	bool raw_violation_fixup;
> +	bool program_deskew_time;
>  };
>  
>  static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
> @@ -2216,6 +2221,16 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
>  		value |= RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK;
>  		writel(value, port->base + RP_VEND_XP);
>  	}
> +
> +	/* Tune deskew retry time to take care of Gen2 -> Gen1
> +	 * link speed change error in corner cases
> +	 */

Wrong block comment style. With that fixed:

Acked-by: Thierry Reding <treding@nvidia.com>

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