From: Thierry Reding <thierry.reding@gmail.com>
To: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Cc: bhelgaas@google.com, jonathanh@nvidia.com, vidyas@nvidia.com,
mperttunen@nvidia.com, linux-tegra@vger.kernel.org,
linux-pci@vger.kernel.org, kthota@nvidia.com
Subject: Re: [PATCH V3 07/12] PCI: tegra: Disable AFI dynamic clock gating
Date: Thu, 14 Dec 2017 16:32:16 +0100 [thread overview]
Message-ID: <20171214153216.GH13733@ulmo> (raw)
In-Reply-To: <1509371843-22931-8-git-send-email-mmaddireddy@nvidia.com>
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On Mon, Oct 30, 2017 at 07:27:18PM +0530, Manikanta Maddireddy wrote:
> When there are 32 outstanding writes from AFI to memory, the outstanding
> write counter overflows and indicates that there are "0" outstanding write
> transactions. This outstanding write counter is used to generate IDLE
> signal to dynamically gate the AFI clock.
>
> When memory controller is under heavy load, its possible that write
> completions will come back to AFI after long delay and AFI write counter
> overflows. AFI clock gets gated even when there are outstanding
> transactions towards memory controller resutling in system hang.
>
> Disable dynamic clock gating of AFI clock to avoid system hang.
>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
> V3:
> * no change in this patch
> V2:
> * no change in this patch
>
> drivers/pci/host/pci-tegra.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> index 4562b0c113a8..c264037112cb 100644
> --- a/drivers/pci/host/pci-tegra.c
> +++ b/drivers/pci/host/pci-tegra.c
> @@ -103,8 +103,9 @@
> #define AFI_MSI_EN_VEC6 0xa4
> #define AFI_MSI_EN_VEC7 0xa8
>
> -#define AFI_CONFIGURATION 0xac
> -#define AFI_CONFIGURATION_EN_FPCI (1 << 0)
> +#define AFI_CONFIGURATION 0xac
> +#define AFI_CONFIGURATION_EN_FPCI (1 << 0)
> +#define AFI_CONFIGURATION_CLKEN_OVERRIDE (1 << 31)
>
> #define AFI_FPCI_ERROR_MASKS 0xb0
>
> @@ -1059,9 +1060,10 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
> }
> }
>
> - /* finally enable PCIe */
> + /* Disable AFI dynamic clock gating and enable PCIe */
> value = afi_readl(pcie, AFI_CONFIGURATION);
> - value |= AFI_CONFIGURATION_EN_FPCI;
> + value |= (AFI_CONFIGURATION_EN_FPCI |
> + AFI_CONFIGURATION_CLKEN_OVERRIDE);
I think this is cleaner (and results in a smaller diff) if you simply
put this on a new line:
value |= AFI_CONFIGURATION_CLKEN_OVERRIDE;
Thierry
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WARNING: multiple messages have this Message-ID (diff)
From: Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Manikanta Maddireddy
<mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org,
jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
vidyas-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
kthota-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org
Subject: Re: [PATCH V3 07/12] PCI: tegra: Disable AFI dynamic clock gating
Date: Thu, 14 Dec 2017 16:32:16 +0100 [thread overview]
Message-ID: <20171214153216.GH13733@ulmo> (raw)
In-Reply-To: <1509371843-22931-8-git-send-email-mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 2083 bytes --]
On Mon, Oct 30, 2017 at 07:27:18PM +0530, Manikanta Maddireddy wrote:
> When there are 32 outstanding writes from AFI to memory, the outstanding
> write counter overflows and indicates that there are "0" outstanding write
> transactions. This outstanding write counter is used to generate IDLE
> signal to dynamically gate the AFI clock.
>
> When memory controller is under heavy load, its possible that write
> completions will come back to AFI after long delay and AFI write counter
> overflows. AFI clock gets gated even when there are outstanding
> transactions towards memory controller resutling in system hang.
>
> Disable dynamic clock gating of AFI clock to avoid system hang.
>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> V3:
> * no change in this patch
> V2:
> * no change in this patch
>
> drivers/pci/host/pci-tegra.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> index 4562b0c113a8..c264037112cb 100644
> --- a/drivers/pci/host/pci-tegra.c
> +++ b/drivers/pci/host/pci-tegra.c
> @@ -103,8 +103,9 @@
> #define AFI_MSI_EN_VEC6 0xa4
> #define AFI_MSI_EN_VEC7 0xa8
>
> -#define AFI_CONFIGURATION 0xac
> -#define AFI_CONFIGURATION_EN_FPCI (1 << 0)
> +#define AFI_CONFIGURATION 0xac
> +#define AFI_CONFIGURATION_EN_FPCI (1 << 0)
> +#define AFI_CONFIGURATION_CLKEN_OVERRIDE (1 << 31)
>
> #define AFI_FPCI_ERROR_MASKS 0xb0
>
> @@ -1059,9 +1060,10 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
> }
> }
>
> - /* finally enable PCIe */
> + /* Disable AFI dynamic clock gating and enable PCIe */
> value = afi_readl(pcie, AFI_CONFIGURATION);
> - value |= AFI_CONFIGURATION_EN_FPCI;
> + value |= (AFI_CONFIGURATION_EN_FPCI |
> + AFI_CONFIGURATION_CLKEN_OVERRIDE);
I think this is cleaner (and results in a smaller diff) if you simply
put this on a new line:
value |= AFI_CONFIGURATION_CLKEN_OVERRIDE;
Thierry
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next prev parent reply other threads:[~2017-12-14 15:32 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-30 13:57 [PATCH V3 00/12] Enable Tegra root port features and apply SW fixups Manikanta Maddireddy
2017-10-30 13:57 ` Manikanta Maddireddy
2017-10-30 13:57 ` [PATCH V3 01/12] PCI: tegra: Start LTSSM after programming root port Manikanta Maddireddy
2017-10-30 13:57 ` Manikanta Maddireddy
2017-12-12 11:32 ` Lorenzo Pieralisi
2017-12-12 11:32 ` Lorenzo Pieralisi
2017-12-13 11:50 ` Manikanta Maddireddy
2017-12-13 11:50 ` Manikanta Maddireddy
2017-12-13 14:08 ` Lorenzo Pieralisi
2017-12-13 14:08 ` Lorenzo Pieralisi
2017-12-13 16:32 ` Manikanta Maddireddy
2017-12-13 16:32 ` Manikanta Maddireddy
2017-12-13 18:34 ` Lorenzo Pieralisi
2017-12-13 18:34 ` Lorenzo Pieralisi
2017-12-13 19:27 ` Manikanta Maddireddy
2017-12-13 19:27 ` Manikanta Maddireddy
2017-12-14 9:57 ` Lorenzo Pieralisi
2017-12-14 9:57 ` Lorenzo Pieralisi
2018-03-07 12:00 ` Lorenzo Pieralisi
2018-03-07 17:10 ` Manikanta Maddireddy
2017-10-30 13:57 ` [PATCH V3 02/12] PCI: tegra: Move REFCLK pad settings out of phy_power_on() Manikanta Maddireddy
2017-10-30 13:57 ` Manikanta Maddireddy
2017-12-12 11:45 ` Lorenzo Pieralisi
2017-12-12 11:45 ` Lorenzo Pieralisi
2017-12-13 12:02 ` Manikanta Maddireddy
2017-12-13 12:02 ` Manikanta Maddireddy
2017-12-13 14:23 ` Lorenzo Pieralisi
2017-12-13 1:16 ` Mikko Perttunen
2017-12-13 1:16 ` Mikko Perttunen
2017-12-14 15:14 ` Thierry Reding
2017-12-19 12:40 ` Lorenzo Pieralisi
2017-12-19 12:40 ` Lorenzo Pieralisi
2017-10-30 13:57 ` [PATCH V3 03/12] PCI: tegra: Retrain link for Gen2 speed Manikanta Maddireddy
2017-10-30 13:57 ` Manikanta Maddireddy
2017-12-12 14:32 ` Lorenzo Pieralisi
2017-12-12 14:32 ` Lorenzo Pieralisi
2017-12-13 17:54 ` Manikanta Maddireddy
2017-12-13 17:54 ` Manikanta Maddireddy
2017-12-13 18:51 ` Lorenzo Pieralisi
2017-12-13 18:51 ` Lorenzo Pieralisi
2017-12-13 19:10 ` Bjorn Helgaas
2017-12-13 19:10 ` Bjorn Helgaas
2017-12-21 19:48 ` Ley Foon Tan
2017-12-21 19:48 ` Ley Foon Tan
2017-10-30 13:57 ` [PATCH V3 04/12] PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability Manikanta Maddireddy
2017-10-30 13:57 ` Manikanta Maddireddy
2017-12-14 15:29 ` Thierry Reding
2017-12-14 15:29 ` Thierry Reding
2017-10-30 13:57 ` [PATCH V3 05/12] PCI: tegra: Program UPHY electrical settings in Tegra210 Manikanta Maddireddy
2017-10-30 13:57 ` Manikanta Maddireddy
2017-12-14 15:28 ` Thierry Reding
2017-12-14 15:28 ` Thierry Reding
2017-10-30 13:57 ` [PATCH V3 06/12] PCI: tegra: Enable opportunistic update FC and ACK Manikanta Maddireddy
2017-10-30 13:57 ` Manikanta Maddireddy
2017-12-14 15:30 ` Thierry Reding
2017-12-14 15:30 ` Thierry Reding
2017-10-30 13:57 ` [PATCH V3 07/12] PCI: tegra: Disable AFI dynamic clock gating Manikanta Maddireddy
2017-10-30 13:57 ` Manikanta Maddireddy
2017-12-14 15:32 ` Thierry Reding [this message]
2017-12-14 15:32 ` Thierry Reding
2017-10-30 13:57 ` [PATCH V3 08/12] PCI: tegra: Wait for DLLP to finish before entering L1 or L2 Manikanta Maddireddy
2017-10-30 13:57 ` Manikanta Maddireddy
2017-12-14 15:34 ` Thierry Reding
2017-12-14 15:34 ` Thierry Reding
2017-10-30 13:57 ` [PATCH V3 09/12] PCI: tegra: Enable PCIe xclk clock clamping Manikanta Maddireddy
2017-10-30 13:57 ` Manikanta Maddireddy
2017-12-14 15:58 ` Thierry Reding
2017-12-14 15:58 ` Thierry Reding
2017-10-30 13:57 ` [PATCH V3 10/12] PCI: tegra: Add SW fixup for RAW violations Manikanta Maddireddy
2017-10-30 13:57 ` Manikanta Maddireddy
2017-12-14 16:00 ` Thierry Reding
2017-12-14 16:00 ` Thierry Reding
2017-10-30 13:57 ` [PATCH V3 11/12] PCI: tegra: Increase the deskew retry time Manikanta Maddireddy
2017-10-30 13:57 ` Manikanta Maddireddy
2017-12-14 16:02 ` Thierry Reding
2017-10-30 13:57 ` [PATCH V3 12/12] PCI: tegra: Update flow control threshold in Tegra210 Manikanta Maddireddy
2017-10-30 13:57 ` Manikanta Maddireddy
2017-12-12 17:43 ` Lorenzo Pieralisi
2017-12-12 17:43 ` Lorenzo Pieralisi
2017-12-14 16:13 ` Thierry Reding
2017-12-14 16:13 ` Thierry Reding
2017-12-14 16:14 ` Thierry Reding
2017-12-14 16:14 ` Thierry Reding
2017-11-25 19:59 ` [PATCH V3 00/12] Enable Tegra root port features and apply SW fixups Manikanta Maddireddy
2017-11-25 19:59 ` Manikanta Maddireddy
2017-11-27 18:09 ` Lorenzo Pieralisi
2017-11-27 18:09 ` Lorenzo Pieralisi
2017-11-27 18:27 ` Manikanta Maddireddy
2017-11-27 18:27 ` Manikanta Maddireddy
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