From: shawnguo@kernel.org (Shawn Guo)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/4] arm64: add basic DTS for i.MX8MQ
Date: Tue, 23 Jan 2018 18:36:11 +0800 [thread overview]
Message-ID: <20180123103609.GD27764@dragon> (raw)
In-Reply-To: <20180117183244.28303-2-l.stach@pengutronix.de>
On Wed, Jan 17, 2018 at 07:32:42PM +0100, Lucas Stach wrote:
> This adds the basic DTS for the i.MX8MQ.
> For now only the following peripherals are supported:
> - IOMUXC (pin controller)
> - CCM (clock controller)
> - GPIO
> - UART
> - uSDHC (SD/eMMC controller)
> - FEC (ethernet controller)
> - i2c
>
> This is enough to get a very basic board support up and running.
>
> One known limitation is that the driver for the GPC interrupt
> controller is still missing, rendering the CPU sleep states unusable
> as there is nothing waking them up anymore. This will be fixed in
> due course.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/nxp/imx8mq-pinfunc.h | 632 +++++++++++++++++++++++++++++++
> arch/arm64/boot/dts/nxp/imx8mq.dtsi | 418 ++++++++++++++++++++
> 3 files changed, 1051 insertions(+)
> create mode 100644 arch/arm64/boot/dts/nxp/imx8mq-pinfunc.h
> create mode 100644 arch/arm64/boot/dts/nxp/imx8mq.dtsi
<snip>
> diff --git a/arch/arm64/boot/dts/nxp/imx8mq.dtsi b/arch/arm64/boot/dts/nxp/imx8mq.dtsi
> new file mode 100644
> index 000000000000..64955a97558e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/nxp/imx8mq.dtsi
> @@ -0,0 +1,418 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <dt-bindings/clock/imx8mq-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include "imx8mq-pinfunc.h"
> +
> +/* first 128 KiB of memory are owned by ATF */
> +/memreserve/ 0x40000000 0x00020000;
> +
> +/ {
> + compatible = "nxp,imx8mq";
> + /* This should really be the GPC, but we need a driver for this first */
> + interrupt-parent = <&gic>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + gpio0 = &gpio1;
> + gpio1 = &gpio2;
> + gpio2 = &gpio3;
> + gpio3 = &gpio4;
> + gpio4 = &gpio5;
> + i2c0 = &i2c1;
> + i2c1 = &i2c2;
> + i2c2 = &i2c3;
> + i2c3 = &i2c4;
> + serial0 = &uart1;
> + serial1 = &uart2;
> + serial2 = &uart3;
> + serial3 = &uart4;
> + };
> +
> + ckil: clk-ckil {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + clock-output-names = "ckil";
> + };
> +
> + osc_25m: clk-osc-25m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + clock-output-names = "osc_25m";
> + };
> +
> + osc_27m: clk-osc-27m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <27000000>;
> + clock-output-names = "osc_27m";
> + };
> +
> + clk_ext1: clk-ext1 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <133000000>;
> + clock-output-names = "clk_ext1";
> + };
> +
> + clk_ext2: clk-ext2 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <133000000>;
> + clock-output-names = "clk_ext2";
> + };
> +
> + clk_ext3: clk-ext3 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <133000000>;
> + clock-output-names = "clk_ext3";
> + };
> +
> + clk_ext4: clk-ext4 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency= <133000000>;
> + clock-output-names = "clk_ext4";
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + idle-states {
> + entry-method = "psci";
> +
> + CPU_SLEEP: cpu-sleep {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010033>;
> + local-timer-stop;
> + entry-latency-us = <1000>;
> + exit-latency-us = <700>;
> + min-residency-us = <2700>;
> + wakeup-latency-us = <1500>;
> + };
> + };
> +
> + A53_0: cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + };
> +
> + A53_1: cpu at 1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + };
> +
> + A53_2: cpu at 2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x2>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + };
> +
> + A53_3: cpu at 3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x3>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + };
> +
> + A53_L2: l2-cache0 {
> + compatible = "cache";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
> + clock-frequency = <8333333>;
> + interrupt-parent = <&gic>;
> + arm,no-tick-in-suspend;
> + };
> +
> + peripherals at 0 {
What's the reason of using 'peripherals' rather than 'soc' which is the
case for most device trees?
> + compatible = "simple-bus";
> +
Drop the newline.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x0 0x3e000000>;
> +
> +
One newline is enough.
> + aips-bus at 30000000 { /* AIPS1 */
> + compatible = "nxp,imx8mq-aips-bus", "simple-bus";
> +
Drop the newline.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x30000000 0x30000000 0x400000>;
> +
> + gpio1: gpio at 30200000 {
> + compatible = "nxp,imx8mq-gpio", "fsl,imx35-gpio";
It looks a bit odd to have different vendor prefix for the same device.
But we can understand the reason. Just curious if this is what vendor
kernel does?
> + reg = <0x30200000 0x10000>;
> + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio2: gpio at 30210000 {
> + compatible = "nxp,imx8mq-gpio", "fsl,imx35-gpio";
> + reg = <0x30210000 0x10000>;
> + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio3: gpio at 30220000 {
> + compatible = "nxp,imx8mq-gpio", "fsl,imx35-gpio";
> + reg = <0x30220000 0x10000>;
> + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio4: gpio at 30230000 {
> + compatible = "nxp,imx8mq-gpio", "fsl,imx35-gpio";
> + reg = <0x30230000 0x10000>;
> + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio5: gpio at 30240000 {
> + compatible = "nxp,imx8mq-gpio", "fsl,imx35-gpio";
> + reg = <0x30240000 0x10000>;
> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + iomuxc: iomuxc at 30330000 {
> + compatible = "nxp,imx8mq-iomuxc";
> + reg = <0x30330000 0x10000>;
> + };
> +
> + gpr: iomuxc-gpr at 30340000 {
> + compatible = "nxp,imx8mq-iomuxc-gpr", "syscon";
> + reg = <0x30340000 0x10000>;
> + };
> +
> + anatop: anatop at 30360000 {
> + compatible = "nxp,imx8mq-anatop", "syscon";
> + reg = <0x30360000 0x10000>;
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + clk: ccm at 30380000 {
> + compatible = "nxp,imx8mq-ccm";
> + reg = <0x30380000 0x10000>;
> + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> + #clock-cells = <1>;
> + clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
> + <&clk_ext1>, <&clk_ext2>,
> + <&clk_ext3>, <&clk_ext4>;
> + clock-names = "ckil", "osc_25m", "osc_27m",
> + "clk_ext1", "clk_ext2",
> + "clk_ext3", "clk_ext4";
> + };
> + };
> +
> + aips-bus at 30400000 { /* AIPS2 */
> + compatible = "nxp,imx8mq-aips-bus", "simple-bus";
> +
Drop the newline.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x30400000 0x30400000 0x400000>;
> + };
> +
> + aips-bus at 30800000 { /* AIPS3 */
> + compatible = "nxp,imx8mq-aips-bus", "simple-bus";
> +
Ditto
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x30800000 0x30800000 0x400000>;
> +
> + uart1: serial at 30860000 {
> + compatible = "nxp,imx8mq-uart",
> + "fsl,imx6q-uart", "fsl,imx21-uart";
Falling on "fsl,imx6q-uart" only is good enough?
> + reg = <0x30860000 0x10000>;
> + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
> + <&clk IMX8MQ_CLK_UART1_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + uart3: serial at 30880000 {
> + compatible = "nxp,imx8mq-uart",
> + "fsl,imx6q-uart", "fsl,imx21-uart";
> + reg = <0x30880000 0x10000>;
> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
> + <&clk IMX8MQ_CLK_UART3_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + uart2: serial at 30890000 {
> + compatible = "nxp,imx8mq-uart",
> + "fsl,imx6q-uart", "fsl,imx21-uart";
> + reg = <0x30890000 0x10000>;
> + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
> + <&clk IMX8MQ_CLK_UART2_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + i2c1: i2c at 30a20000 {
> + compatible = "nxp,imx8mq-i2c", "fsl,imx21-i2c";
> + reg = <0x30a20000 0x10000>;
> + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
> + status = "disabled";
Please put the 'status' at the bottom of property list.
Shawn
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c2: i2c at 30a30000 {
> + compatible = "nxp,imx8mq-i2c", "fsl,imx21-i2c";
> + reg = <0x30a30000 0x10000>;
> + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c3: i2c at 30a40000 {
> + compatible = "nxp,imx8mq-i2c", "fsl,imx21-i2c";
> + reg = <0x30a40000 0x10000>;
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c4: i2c at 30a50000 {
> + compatible = "nxp,imx8mq-i2c", "fsl,imx21-i2c";
> + reg = <0x30a50000 0x10000>;
> + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + uart4: serial at 30a60000 {
> + compatible = "nxp,imx8mq-uart",
> + "fsl,imx6q-uart", "fsl,imx21-uart";
> + reg = <0x30a60000 0x10000>;
> + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
> + <&clk IMX8MQ_CLK_UART4_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + usdhc1: usdhc at 30b40000 {
> + compatible = "nxp,imx8mq-usdhc",
> + "fsl,imx7d-usdhc";
> + reg = <0x30b40000 0x10000>;
> + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_DUMMY>,
> + <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
> + <&clk IMX8MQ_CLK_USDHC1_ROOT>;
> + clock-names = "ipg", "ahb", "per";
> + fsl,tuning-start-tap = <20>;
> + fsl,tuning-step = <2>;
> + bus-width = <4>;
> + status = "disabled";
> + };
> +
> + usdhc2: usdhc at 30b50000 {
> + compatible = "nxp,imx8mq-usdhc",
> + "fsl,imx7d-usdhc";
> + reg = <0x30b50000 0x10000>;
> + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_DUMMY>,
> + <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
> + <&clk IMX8MQ_CLK_USDHC2_ROOT>;
> + clock-names = "ipg", "ahb", "per";
> + fsl,tuning-start-tap = <20>;
> + fsl,tuning-step = <2>;
> + bus-width = <4>;
> + status = "disabled";
> + };
> +
> + fec1: ethernet at 30be0000 {
> + compatible = "nxp,imx8mq-fec", "fsl,imx6sx-fec";
> + reg = <0x30be0000 0x10000>;
> + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
> + <&clk IMX8MQ_CLK_ENET1_ROOT>,
> + <&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
> + <&clk IMX8MQ_CLK_ENET_REF_DIV>,
> + <&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
> + clock-names = "ipg", "ahb", "ptp",
> + "enet_clk_ref", "enet_out";
> + fsl,num-tx-queues = <3>;
> + fsl,num-rx-queues = <3>;
> + status = "disabled";
> + };
> + };
> +
> + gic: interrupt-controller at 38800000 {
> + compatible = "arm,gic-v3";
> + reg = <0x38800000 0x10000>, /* GIC Dist */
> + <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&gic>;
> + };
> + };
> +};
> --
> 2.11.0
>
WARNING: multiple messages have this Message-ID (diff)
From: Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Cc: Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org>,
Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org,
patchwork-lst-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org
Subject: Re: [PATCH 2/4] arm64: add basic DTS for i.MX8MQ
Date: Tue, 23 Jan 2018 18:36:11 +0800 [thread overview]
Message-ID: <20180123103609.GD27764@dragon> (raw)
In-Reply-To: <20180117183244.28303-2-l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
On Wed, Jan 17, 2018 at 07:32:42PM +0100, Lucas Stach wrote:
> This adds the basic DTS for the i.MX8MQ.
> For now only the following peripherals are supported:
> - IOMUXC (pin controller)
> - CCM (clock controller)
> - GPIO
> - UART
> - uSDHC (SD/eMMC controller)
> - FEC (ethernet controller)
> - i2c
>
> This is enough to get a very basic board support up and running.
>
> One known limitation is that the driver for the GPC interrupt
> controller is still missing, rendering the CPU sleep states unusable
> as there is nothing waking them up anymore. This will be fixed in
> due course.
>
> Signed-off-by: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> ---
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/nxp/imx8mq-pinfunc.h | 632 +++++++++++++++++++++++++++++++
> arch/arm64/boot/dts/nxp/imx8mq.dtsi | 418 ++++++++++++++++++++
> 3 files changed, 1051 insertions(+)
> create mode 100644 arch/arm64/boot/dts/nxp/imx8mq-pinfunc.h
> create mode 100644 arch/arm64/boot/dts/nxp/imx8mq.dtsi
<snip>
> diff --git a/arch/arm64/boot/dts/nxp/imx8mq.dtsi b/arch/arm64/boot/dts/nxp/imx8mq.dtsi
> new file mode 100644
> index 000000000000..64955a97558e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/nxp/imx8mq.dtsi
> @@ -0,0 +1,418 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <dt-bindings/clock/imx8mq-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include "imx8mq-pinfunc.h"
> +
> +/* first 128 KiB of memory are owned by ATF */
> +/memreserve/ 0x40000000 0x00020000;
> +
> +/ {
> + compatible = "nxp,imx8mq";
> + /* This should really be the GPC, but we need a driver for this first */
> + interrupt-parent = <&gic>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + gpio0 = &gpio1;
> + gpio1 = &gpio2;
> + gpio2 = &gpio3;
> + gpio3 = &gpio4;
> + gpio4 = &gpio5;
> + i2c0 = &i2c1;
> + i2c1 = &i2c2;
> + i2c2 = &i2c3;
> + i2c3 = &i2c4;
> + serial0 = &uart1;
> + serial1 = &uart2;
> + serial2 = &uart3;
> + serial3 = &uart4;
> + };
> +
> + ckil: clk-ckil {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + clock-output-names = "ckil";
> + };
> +
> + osc_25m: clk-osc-25m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + clock-output-names = "osc_25m";
> + };
> +
> + osc_27m: clk-osc-27m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <27000000>;
> + clock-output-names = "osc_27m";
> + };
> +
> + clk_ext1: clk-ext1 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <133000000>;
> + clock-output-names = "clk_ext1";
> + };
> +
> + clk_ext2: clk-ext2 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <133000000>;
> + clock-output-names = "clk_ext2";
> + };
> +
> + clk_ext3: clk-ext3 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <133000000>;
> + clock-output-names = "clk_ext3";
> + };
> +
> + clk_ext4: clk-ext4 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency= <133000000>;
> + clock-output-names = "clk_ext4";
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + idle-states {
> + entry-method = "psci";
> +
> + CPU_SLEEP: cpu-sleep {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010033>;
> + local-timer-stop;
> + entry-latency-us = <1000>;
> + exit-latency-us = <700>;
> + min-residency-us = <2700>;
> + wakeup-latency-us = <1500>;
> + };
> + };
> +
> + A53_0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + };
> +
> + A53_1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + };
> +
> + A53_2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x2>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + };
> +
> + A53_3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x3>;
> + enable-method = "psci";
> + next-level-cache = <&A53_L2>;
> + cpu-idle-states = <&CPU_SLEEP>;
> + };
> +
> + A53_L2: l2-cache0 {
> + compatible = "cache";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
> + clock-frequency = <8333333>;
> + interrupt-parent = <&gic>;
> + arm,no-tick-in-suspend;
> + };
> +
> + peripherals@0 {
What's the reason of using 'peripherals' rather than 'soc' which is the
case for most device trees?
> + compatible = "simple-bus";
> +
Drop the newline.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x0 0x3e000000>;
> +
> +
One newline is enough.
> + aips-bus@30000000 { /* AIPS1 */
> + compatible = "nxp,imx8mq-aips-bus", "simple-bus";
> +
Drop the newline.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x30000000 0x30000000 0x400000>;
> +
> + gpio1: gpio@30200000 {
> + compatible = "nxp,imx8mq-gpio", "fsl,imx35-gpio";
It looks a bit odd to have different vendor prefix for the same device.
But we can understand the reason. Just curious if this is what vendor
kernel does?
> + reg = <0x30200000 0x10000>;
> + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio2: gpio@30210000 {
> + compatible = "nxp,imx8mq-gpio", "fsl,imx35-gpio";
> + reg = <0x30210000 0x10000>;
> + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio3: gpio@30220000 {
> + compatible = "nxp,imx8mq-gpio", "fsl,imx35-gpio";
> + reg = <0x30220000 0x10000>;
> + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio4: gpio@30230000 {
> + compatible = "nxp,imx8mq-gpio", "fsl,imx35-gpio";
> + reg = <0x30230000 0x10000>;
> + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio5: gpio@30240000 {
> + compatible = "nxp,imx8mq-gpio", "fsl,imx35-gpio";
> + reg = <0x30240000 0x10000>;
> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + iomuxc: iomuxc@30330000 {
> + compatible = "nxp,imx8mq-iomuxc";
> + reg = <0x30330000 0x10000>;
> + };
> +
> + gpr: iomuxc-gpr@30340000 {
> + compatible = "nxp,imx8mq-iomuxc-gpr", "syscon";
> + reg = <0x30340000 0x10000>;
> + };
> +
> + anatop: anatop@30360000 {
> + compatible = "nxp,imx8mq-anatop", "syscon";
> + reg = <0x30360000 0x10000>;
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + clk: ccm@30380000 {
> + compatible = "nxp,imx8mq-ccm";
> + reg = <0x30380000 0x10000>;
> + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> + #clock-cells = <1>;
> + clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
> + <&clk_ext1>, <&clk_ext2>,
> + <&clk_ext3>, <&clk_ext4>;
> + clock-names = "ckil", "osc_25m", "osc_27m",
> + "clk_ext1", "clk_ext2",
> + "clk_ext3", "clk_ext4";
> + };
> + };
> +
> + aips-bus@30400000 { /* AIPS2 */
> + compatible = "nxp,imx8mq-aips-bus", "simple-bus";
> +
Drop the newline.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x30400000 0x30400000 0x400000>;
> + };
> +
> + aips-bus@30800000 { /* AIPS3 */
> + compatible = "nxp,imx8mq-aips-bus", "simple-bus";
> +
Ditto
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x30800000 0x30800000 0x400000>;
> +
> + uart1: serial@30860000 {
> + compatible = "nxp,imx8mq-uart",
> + "fsl,imx6q-uart", "fsl,imx21-uart";
Falling on "fsl,imx6q-uart" only is good enough?
> + reg = <0x30860000 0x10000>;
> + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
> + <&clk IMX8MQ_CLK_UART1_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + uart3: serial@30880000 {
> + compatible = "nxp,imx8mq-uart",
> + "fsl,imx6q-uart", "fsl,imx21-uart";
> + reg = <0x30880000 0x10000>;
> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
> + <&clk IMX8MQ_CLK_UART3_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + uart2: serial@30890000 {
> + compatible = "nxp,imx8mq-uart",
> + "fsl,imx6q-uart", "fsl,imx21-uart";
> + reg = <0x30890000 0x10000>;
> + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
> + <&clk IMX8MQ_CLK_UART2_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + i2c1: i2c@30a20000 {
> + compatible = "nxp,imx8mq-i2c", "fsl,imx21-i2c";
> + reg = <0x30a20000 0x10000>;
> + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
> + status = "disabled";
Please put the 'status' at the bottom of property list.
Shawn
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c2: i2c@30a30000 {
> + compatible = "nxp,imx8mq-i2c", "fsl,imx21-i2c";
> + reg = <0x30a30000 0x10000>;
> + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c3: i2c@30a40000 {
> + compatible = "nxp,imx8mq-i2c", "fsl,imx21-i2c";
> + reg = <0x30a40000 0x10000>;
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c4: i2c@30a50000 {
> + compatible = "nxp,imx8mq-i2c", "fsl,imx21-i2c";
> + reg = <0x30a50000 0x10000>;
> + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + uart4: serial@30a60000 {
> + compatible = "nxp,imx8mq-uart",
> + "fsl,imx6q-uart", "fsl,imx21-uart";
> + reg = <0x30a60000 0x10000>;
> + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
> + <&clk IMX8MQ_CLK_UART4_ROOT>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> +
> + usdhc1: usdhc@30b40000 {
> + compatible = "nxp,imx8mq-usdhc",
> + "fsl,imx7d-usdhc";
> + reg = <0x30b40000 0x10000>;
> + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_DUMMY>,
> + <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
> + <&clk IMX8MQ_CLK_USDHC1_ROOT>;
> + clock-names = "ipg", "ahb", "per";
> + fsl,tuning-start-tap = <20>;
> + fsl,tuning-step = <2>;
> + bus-width = <4>;
> + status = "disabled";
> + };
> +
> + usdhc2: usdhc@30b50000 {
> + compatible = "nxp,imx8mq-usdhc",
> + "fsl,imx7d-usdhc";
> + reg = <0x30b50000 0x10000>;
> + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_DUMMY>,
> + <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
> + <&clk IMX8MQ_CLK_USDHC2_ROOT>;
> + clock-names = "ipg", "ahb", "per";
> + fsl,tuning-start-tap = <20>;
> + fsl,tuning-step = <2>;
> + bus-width = <4>;
> + status = "disabled";
> + };
> +
> + fec1: ethernet@30be0000 {
> + compatible = "nxp,imx8mq-fec", "fsl,imx6sx-fec";
> + reg = <0x30be0000 0x10000>;
> + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
> + <&clk IMX8MQ_CLK_ENET1_ROOT>,
> + <&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
> + <&clk IMX8MQ_CLK_ENET_REF_DIV>,
> + <&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
> + clock-names = "ipg", "ahb", "ptp",
> + "enet_clk_ref", "enet_out";
> + fsl,num-tx-queues = <3>;
> + fsl,num-rx-queues = <3>;
> + status = "disabled";
> + };
> + };
> +
> + gic: interrupt-controller@38800000 {
> + compatible = "arm,gic-v3";
> + reg = <0x38800000 0x10000>, /* GIC Dist */
> + <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&gic>;
> + };
> + };
> +};
> --
> 2.11.0
>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
next prev parent reply other threads:[~2018-01-23 10:36 UTC|newest]
Thread overview: 69+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-17 18:32 [PATCH 1/4] ARM64: add basic Kconfig symbols for i.MX8 Lucas Stach
2018-01-17 18:32 ` Lucas Stach
2018-01-17 18:32 ` [PATCH 2/4] arm64: add basic DTS for i.MX8MQ Lucas Stach
2018-01-17 18:32 ` Lucas Stach
2018-01-22 11:51 ` Arnd Bergmann
2018-01-22 11:51 ` Arnd Bergmann
2018-01-22 11:51 ` Arnd Bergmann
2018-01-22 11:57 ` Fabio Estevam
2018-01-22 11:57 ` Fabio Estevam
2018-01-22 14:47 ` Shawn Guo
2018-01-22 14:47 ` Shawn Guo
2018-01-22 15:11 ` Arnd Bergmann
2018-01-22 15:11 ` Arnd Bergmann
2018-01-22 17:50 ` Lucas Stach
2018-01-22 17:50 ` Lucas Stach
2018-01-23 1:40 ` Shawn Guo
2018-01-23 1:40 ` Shawn Guo
2018-01-23 10:36 ` Shawn Guo [this message]
2018-01-23 10:36 ` Shawn Guo
2018-01-23 13:23 ` Lucas Stach
2018-01-23 13:23 ` Lucas Stach
2018-01-25 9:48 ` aisheng.dong at codeaurora.org
2018-01-25 9:48 ` aisheng.dong-sgV2jX0FEOL9JmXXK+q4OQ
2018-01-25 10:27 ` Lucas Stach
2018-01-25 10:27 ` Lucas Stach
2018-01-25 12:34 ` Dong Aisheng
2018-01-25 12:34 ` Dong Aisheng
2018-02-02 7:27 ` Shawn Guo
2018-02-02 7:27 ` Shawn Guo
2018-01-29 17:45 ` Rob Herring
2018-01-29 17:45 ` Rob Herring
2018-01-29 17:55 ` Rob Herring
2018-01-29 17:55 ` Rob Herring
2018-01-29 18:00 ` Lucas Stach
2018-01-29 18:00 ` Lucas Stach
2018-01-30 14:55 ` Rob Herring
2018-01-30 14:55 ` Rob Herring
2018-01-17 18:32 ` [PATCH 3/4] arm64: add support for i.MX8M EVK board Lucas Stach
2018-01-17 18:32 ` Lucas Stach
2018-01-22 11:58 ` Fabio Estevam
2018-01-22 11:58 ` Fabio Estevam
2018-01-23 10:39 ` Shawn Guo
2018-01-23 10:39 ` Shawn Guo
2018-01-25 10:10 ` aisheng.dong at codeaurora.org
2018-01-25 10:10 ` aisheng.dong-sgV2jX0FEOL9JmXXK+q4OQ
2018-01-25 10:31 ` Lucas Stach
2018-01-25 10:31 ` Lucas Stach
2018-01-25 10:49 ` Dong Aisheng
2018-01-25 10:49 ` Dong Aisheng
2018-01-25 11:09 ` Lucas Stach
2018-01-25 11:09 ` Lucas Stach
2018-01-25 13:03 ` Dong Aisheng
2018-01-25 13:03 ` Dong Aisheng
2018-01-25 18:03 ` Lucas Stach
2018-01-25 18:03 ` Lucas Stach
2018-01-26 3:06 ` A.s. Dong
2018-01-26 3:06 ` A.s. Dong
2018-01-24 14:47 ` Baruch Siach
2018-01-24 14:47 ` Baruch Siach
2018-01-25 9:52 ` Baruch Siach
2018-01-25 9:52 ` Baruch Siach
2018-01-29 17:52 ` Rob Herring
2018-01-29 17:52 ` Rob Herring
2018-01-17 18:32 ` [PATCH 4/4] MAINTAINERS: add i.MX8 DT path to i.MX architecture Lucas Stach
2018-01-17 18:32 ` Lucas Stach
2018-01-22 11:58 ` Fabio Estevam
2018-01-22 11:58 ` Fabio Estevam
2018-01-22 11:53 ` [PATCH 1/4] ARM64: add basic Kconfig symbols for i.MX8 Fabio Estevam
2018-01-22 11:53 ` Fabio Estevam
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180123103609.GD27764@dragon \
--to=shawnguo@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.