* [v2 1/2] drm/i915: Fix GCMAX color register programming
2019-03-29 14:29 [v2 0/2] Fixed GC MAX register programming for gamma luts Uma Shankar
@ 2019-03-29 14:29 ` Uma Shankar
2019-03-29 14:29 ` [v2 2/2] drm/i915: Program EXT2 GC MAX registers Uma Shankar
` (5 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Uma Shankar @ 2019-03-29 14:29 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala, maarten.lankhorst
GC MAX register is used to program values from 1.0 to
less than 3.0. A different register was used instead of
the intended one. Fixed the same.
Currently limiting it to 1.0 due to ABI limitations.
v2: Updated the 1.0 programming and aligned as per GLK, based
on Ville's feedback.
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/intel_color.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index ff910ed..c776159 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -518,14 +518,14 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of
I915_WRITE(PREC_PAL_DATA(pipe), word);
}
- /* Program the max register to clamp values > 1.0. */
- i = lut_size - 1;
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 0),
- drm_color_lut_extract(lut[i].red, 16));
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 1),
- drm_color_lut_extract(lut[i].green, 16));
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 2),
- drm_color_lut_extract(lut[i].blue, 16));
+ /*
+ * Program the max register to clamp values > 1.0.
+ * ToDo: Extend the ABI to be able to program values
+ * from 1.0 to 3.0
+ */
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16));
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16));
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16));
} else {
for (i = 0; i < lut_size; i++) {
u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
@@ -534,9 +534,9 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of
(v << 20) | (v << 10) | v);
}
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16) - 1);
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
- I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16));
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16));
+ I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16));
}
/*
--
1.9.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread* [v2 2/2] drm/i915: Program EXT2 GC MAX registers
2019-03-29 14:29 [v2 0/2] Fixed GC MAX register programming for gamma luts Uma Shankar
2019-03-29 14:29 ` [v2 1/2] drm/i915: Fix GCMAX color register programming Uma Shankar
@ 2019-03-29 14:29 ` Uma Shankar
2019-03-29 14:30 ` [v2 0/2] Fixed GC MAX register programming for gamma luts Lionel Landwerlin
` (4 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Uma Shankar @ 2019-03-29 14:29 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala, maarten.lankhorst
EXT2 GC MAX registers are introduced from Gen10+ to
program values from 3.0 to 7.0. Enabled the same, but
currently limiting it to 1.0 as userspace ABI is limited
at that currently.
v2: Updated the 1.0 programming and aligned as per GLK, also added
GLK along with GEN10+ check, as per Ville's feedback.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_color.c | 22 ++++++++++++++++++++++
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c866379..341f03e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10144,6 +10144,7 @@ enum skl_power_gate {
#define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
+#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
#define _PRE_CSC_GAMC_INDEX_A 0x4A484
#define _PRE_CSC_GAMC_INDEX_B 0x4AC84
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index c776159..f2907cf 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -526,6 +526,17 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16));
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16));
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16));
+
+ /*
+ * Program the gc max 2 register to clamp values > 1.0.
+ * ToDo: Extend the ABI to be able to program values
+ * from 3.0 to 7.0
+ */
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), (1 << 16));
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), (1 << 16));
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), (1 << 16));
+ }
} else {
for (i = 0; i < lut_size; i++) {
u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
@@ -537,6 +548,17 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16));
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16));
I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16));
+
+ /*
+ * Program the gc max 2 register to clamp values > 1.0.
+ * ToDo: Extend the ABI to be able to program values
+ * from 3.0 to 7.0
+ */
+ if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), (1 << 16));
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), (1 << 16));
+ I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), (1 << 16));
+ }
}
/*
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [v2 0/2] Fixed GC MAX register programming for gamma luts
2019-03-29 14:29 [v2 0/2] Fixed GC MAX register programming for gamma luts Uma Shankar
2019-03-29 14:29 ` [v2 1/2] drm/i915: Fix GCMAX color register programming Uma Shankar
2019-03-29 14:29 ` [v2 2/2] drm/i915: Program EXT2 GC MAX registers Uma Shankar
@ 2019-03-29 14:30 ` Lionel Landwerlin
2019-03-29 14:49 ` Shankar, Uma
2019-03-29 14:36 ` ✗ Fi.CI.CHECKPATCH: warning for Fixed GC MAX register programming for gamma luts (rev2) Patchwork
` (3 subsequent siblings)
6 siblings, 1 reply; 9+ messages in thread
From: Lionel Landwerlin @ 2019-03-29 14:30 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: ville.syrjala, maarten.lankhorst
On 29/03/2019 14:29, Uma Shankar wrote:
> Register offsets used to program GC max were not correct. This series
> fixes the same, also limits the values to accurately clamp at 1.0.
> Also added support to program EXT2 GC Max needed for values from 3.0
> to 7.0. Limiting it again to 1.0 due to ABI limitations.
>
> v2: Addressed Ville's review comments.
>
> Uma Shankar (2):
> drm/i915: Fix GCMAX color register programming
> drm/i915: Program EXT2 GC MAX registers
>
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_color.c | 44 ++++++++++++++++++++++++++++----------
> 2 files changed, 34 insertions(+), 11 deletions(-)
>
Curious about whether that fixed some of the issues you were seeing with
the igt tests? :)
-Lionel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [v2 0/2] Fixed GC MAX register programming for gamma luts
2019-03-29 14:30 ` [v2 0/2] Fixed GC MAX register programming for gamma luts Lionel Landwerlin
@ 2019-03-29 14:49 ` Shankar, Uma
0 siblings, 0 replies; 9+ messages in thread
From: Shankar, Uma @ 2019-03-29 14:49 UTC (permalink / raw)
To: Landwerlin, Lionel G, intel-gfx@lists.freedesktop.org
Cc: Syrjala, Ville, Lankhorst, Maarten
>-----Original Message-----
>From: Landwerlin, Lionel G
>Sent: Friday, March 29, 2019 8:00 PM
>To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org
>Cc: Syrjala, Ville <ville.syrjala@intel.com>; Lankhorst, Maarten
><maarten.lankhorst@intel.com>
>Subject: Re: [Intel-gfx] [v2 0/2] Fixed GC MAX register programming for gamma luts
>
>On 29/03/2019 14:29, Uma Shankar wrote:
>> Register offsets used to program GC max were not correct. This series
>> fixes the same, also limits the values to accurately clamp at 1.0.
>> Also added support to program EXT2 GC Max needed for values from 3.0
>> to 7.0. Limiting it again to 1.0 due to ABI limitations.
>>
>> v2: Addressed Ville's review comments.
>>
>> Uma Shankar (2):
>> drm/i915: Fix GCMAX color register programming
>> drm/i915: Program EXT2 GC MAX registers
>>
>> drivers/gpu/drm/i915/i915_reg.h | 1 +
>> drivers/gpu/drm/i915/intel_color.c | 44 ++++++++++++++++++++++++++++----------
>> 2 files changed, 34 insertions(+), 11 deletions(-)
>>
>Curious about whether that fixed some of the issues you were seeing with the igt
>tests? :)
Unfortunately No Lionel, the test results are still the same :(
>
>
>-Lionel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Fixed GC MAX register programming for gamma luts (rev2)
2019-03-29 14:29 [v2 0/2] Fixed GC MAX register programming for gamma luts Uma Shankar
` (2 preceding siblings ...)
2019-03-29 14:30 ` [v2 0/2] Fixed GC MAX register programming for gamma luts Lionel Landwerlin
@ 2019-03-29 14:36 ` Patchwork
2019-03-29 15:02 ` ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2019-03-29 14:36 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
== Series Details ==
Series: Fixed GC MAX register programming for gamma luts (rev2)
URL : https://patchwork.freedesktop.org/series/58734/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
88164253880f drm/i915: Fix GCMAX color register programming
cad25ef86aee drm/i915: Program EXT2 GC MAX registers
-:24: WARNING:LONG_LINE: line over 100 characters
#24: FILE: drivers/gpu/drm/i915/i915_reg.h:10147:
+#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
total: 0 errors, 1 warnings, 0 checks, 41 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* ✓ Fi.CI.BAT: success for Fixed GC MAX register programming for gamma luts (rev2)
2019-03-29 14:29 [v2 0/2] Fixed GC MAX register programming for gamma luts Uma Shankar
` (3 preceding siblings ...)
2019-03-29 14:36 ` ✗ Fi.CI.CHECKPATCH: warning for Fixed GC MAX register programming for gamma luts (rev2) Patchwork
@ 2019-03-29 15:02 ` Patchwork
2019-03-29 18:17 ` ✓ Fi.CI.IGT: " Patchwork
2019-03-29 18:32 ` [v2 0/2] Fixed GC MAX register programming for gamma luts Ville Syrjälä
6 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2019-03-29 15:02 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
== Series Details ==
Series: Fixed GC MAX register programming for gamma luts (rev2)
URL : https://patchwork.freedesktop.org/series/58734/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12630
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/58734/revisions/2/mbox/
Known issues
------------
Here are the changes found in Patchwork_12630 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-compute:
- fi-kbl-8809g: NOTRUN -> FAIL [fdo#108094]
* igt@gem_exec_store@basic-bsd1:
- fi-kbl-r: NOTRUN -> SKIP [fdo#109271] +41
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: PASS -> DMESG-FAIL [fdo#110235 ]
* igt@i915_selftest@live_uncore:
- fi-skl-gvtdvm: PASS -> DMESG-FAIL [fdo#110210]
* igt@kms_chamelium@vga-edid-read:
- fi-hsw-4770r: NOTRUN -> SKIP [fdo#109271] +45
#### Possible fixes ####
* igt@amdgpu/amd_basic@userptr:
- fi-kbl-8809g: DMESG-WARN [fdo#108965] -> PASS
* igt@i915_selftest@live_uncore:
- fi-ivb-3770: DMESG-FAIL [fdo#110210] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS +2
* igt@prime_vgem@basic-fence-flip:
- fi-gdg-551: FAIL [fdo#103182] -> PASS +1
[fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#108094]: https://bugs.freedesktop.org/show_bug.cgi?id=108094
[fdo#108965]: https://bugs.freedesktop.org/show_bug.cgi?id=108965
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#110210]: https://bugs.freedesktop.org/show_bug.cgi?id=110210
[fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
Participating hosts (46 -> 40)
------------------------------
Additional (2): fi-hsw-4770r fi-kbl-r
Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-icl-u2 fi-bwr-2160 fi-bsw-cyan fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5837 -> Patchwork_12630
CI_DRM_5837: 1a35af6fa0d612425e325024cbac10e6fa9a9cd5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4912: 66deae8b6fa69540f069d6551cd22013f5343948 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12630: cad25ef86aeec8f53dca8f9267402a8cf7ee705f @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cad25ef86aee drm/i915: Program EXT2 GC MAX registers
88164253880f drm/i915: Fix GCMAX color register programming
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12630/
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* ✓ Fi.CI.IGT: success for Fixed GC MAX register programming for gamma luts (rev2)
2019-03-29 14:29 [v2 0/2] Fixed GC MAX register programming for gamma luts Uma Shankar
` (4 preceding siblings ...)
2019-03-29 15:02 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-03-29 18:17 ` Patchwork
2019-03-29 18:32 ` [v2 0/2] Fixed GC MAX register programming for gamma luts Ville Syrjälä
6 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2019-03-29 18:17 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
== Series Details ==
Series: Fixed GC MAX register programming for gamma luts (rev2)
URL : https://patchwork.freedesktop.org/series/58734/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5837_full -> Patchwork_12630_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_12630_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@read_all_entries_display_off:
- shard-skl: NOTRUN -> INCOMPLETE [fdo#104108]
* igt@gem_tiled_pread_pwrite:
- shard-iclb: PASS -> TIMEOUT [fdo#109673]
* igt@i915_suspend@fence-restore-untiled:
- shard-skl: PASS -> INCOMPLETE [fdo#104108] / [fdo#107773] +1
* igt@kms_atomic_transition@3x-modeset-transitions-nonblocking:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3
* igt@kms_atomic_transition@4x-modeset-transitions-nonblocking-fencing:
- shard-snb: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +11
* igt@kms_busy@basic-modeset-e:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_busy@extended-modeset-hang-newfb-render-b:
- shard-skl: PASS -> DMESG-WARN [fdo#110222]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#110222]
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-kbl: NOTRUN -> DMESG-WARN [fdo#110222]
* igt@kms_chamelium@vga-edid-read:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +41
* igt@kms_flip@2x-plain-flip-ts-check:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +19
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: PASS -> FAIL [fdo#105363]
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: PASS -> INCOMPLETE [fdo#109507]
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
- shard-snb: NOTRUN -> SKIP [fdo#109271] +70
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-iclb: PASS -> FAIL [fdo#103167] +5
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
- shard-iclb: PASS -> FAIL [fdo#105682] / [fdo#109247]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-iclb: PASS -> FAIL [fdo#109247] +10
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +23
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl: NOTRUN -> FAIL [fdo#107815] / [fdo#108145]
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +1
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: PASS -> FAIL [fdo#107815]
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: PASS -> SKIP [fdo#109441] +2
* igt@kms_psr@sprite_blt:
- shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215]
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: PASS -> DMESG-FAIL [fdo#105763]
* igt@kms_sysfs_edid_timing:
- shard-skl: NOTRUN -> FAIL [fdo#100047]
* igt@kms_vblank@pipe-a-ts-continuation-dpms-rpm:
- shard-apl: PASS -> FAIL [fdo#104894]
#### Possible fixes ####
* igt@gem_eio@hibernate:
- shard-snb: FAIL [fdo#107918] -> PASS
* igt@gem_pwrite@big-cpu-fbr:
- shard-apl: INCOMPLETE [fdo#103927] -> PASS
* igt@gem_tiled_swapping@non-threaded:
- shard-iclb: DMESG-WARN [fdo#108686] -> PASS
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
- shard-kbl: DMESG-WARN [fdo#110222] -> PASS
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: FAIL [fdo#102670] / [fdo#106081] -> PASS
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: FAIL [fdo#105363] -> PASS
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: FAIL [fdo#105363] -> PASS
- shard-snb: FAIL [fdo#105363] -> PASS
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-iclb: FAIL [fdo#109247] -> PASS +12
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-blt:
- shard-iclb: FAIL [fdo#103167] -> PASS
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-gtt:
- shard-iclb: FAIL [fdo#105682] / [fdo#109247] -> PASS +1
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: SKIP [fdo#109441] -> PASS +4
* igt@kms_psr@sprite_render:
- shard-iclb: FAIL [fdo#107383] / [fdo#110215] -> PASS +5
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-iclb: FAIL [fdo#104894] -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105682]: https://bugs.freedesktop.org/show_bug.cgi?id=105682
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106081]: https://bugs.freedesktop.org/show_bug.cgi?id=106081
[fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
[fdo#107918]: https://bugs.freedesktop.org/show_bug.cgi?id=107918
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#109673]: https://bugs.freedesktop.org/show_bug.cgi?id=109673
[fdo#110215]: https://bugs.freedesktop.org/show_bug.cgi?id=110215
[fdo#110222]: https://bugs.freedesktop.org/show_bug.cgi?id=110222
Participating hosts (10 -> 9)
------------------------------
Missing (1): shard-hsw
Build changes
-------------
* Linux: CI_DRM_5837 -> Patchwork_12630
CI_DRM_5837: 1a35af6fa0d612425e325024cbac10e6fa9a9cd5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4912: 66deae8b6fa69540f069d6551cd22013f5343948 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12630: cad25ef86aeec8f53dca8f9267402a8cf7ee705f @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12630/
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^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [v2 0/2] Fixed GC MAX register programming for gamma luts
2019-03-29 14:29 [v2 0/2] Fixed GC MAX register programming for gamma luts Uma Shankar
` (5 preceding siblings ...)
2019-03-29 18:17 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-03-29 18:32 ` Ville Syrjälä
6 siblings, 0 replies; 9+ messages in thread
From: Ville Syrjälä @ 2019-03-29 18:32 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx, ville.syrjala, maarten.lankhorst
On Fri, Mar 29, 2019 at 07:59:14PM +0530, Uma Shankar wrote:
> Register offsets used to program GC max were not correct. This series
> fixes the same, also limits the values to accurately clamp at 1.0.
> Also added support to program EXT2 GC Max needed for values from 3.0
> to 7.0. Limiting it again to 1.0 due to ABI limitations.
>
> v2: Addressed Ville's review comments.
>
> Uma Shankar (2):
> drm/i915: Fix GCMAX color register programming
> drm/i915: Program EXT2 GC MAX registers
Both pushed to dinq. Thanks.
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 9+ messages in thread