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From: Claudio Carvalho <cclaudio@linux.ibm.com>
To: linuxppc-dev@ozlabs.org
Cc: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>,
	Michael Anderson <andmike@linux.ibm.com>,
	Ram Pai <linuxram@us.ibm.com>,
	Claudio Carvalho <cclaudio@linux.ibm.com>,
	kvm-ppc@vger.kernel.org, Bharata B Rao <bharata@linux.ibm.com>,
	Ryan Grimm <grimm@linux.ibm.com>,
	Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>,
	Thiago Bauermann <bauerman@linux.ibm.com>,
	Anshuman Khandual <khandual@linux.vnet.ibm.com>
Subject: [PATCH v4 1/8] KVM: PPC: Ultravisor: Introduce the MSR_S bit
Date: Fri, 28 Jun 2019 20:08:18 +0000	[thread overview]
Message-ID: <20190628200825.31049-2-cclaudio@linux.ibm.com> (raw)
In-Reply-To: <20190628200825.31049-1-cclaudio@linux.ibm.com>

From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>

The ultravisor processor mode is introduced in POWER platforms that
supports the Protected Execution Facility (PEF). Ultravisor is higher
privileged than hypervisor mode.

In PEF enabled platforms, the MSR_S bit is used to indicate if the
thread is in secure state. With the MSR_S bit, the privilege state of
the thread is now determined by MSR_S, MSR_HV and MSR_PR, as follows:

S   HV  PR
-----------------------
0   x   1   problem
1   0   1   problem
x   x   0   privileged
x   1   0   hypervisor
1   1   0   ultravisor
1   1   1   reserved

The hypervisor doesn't (and can't) run with the MSR_S bit set, but a
secure guest and the ultravisor firmware do.

Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Signed-off-by: Ram Pai <linuxram@us.ibm.com>
[ Update the commit message ]
Signed-off-by: Claudio Carvalho <cclaudio@linux.ibm.com>
---
 arch/powerpc/include/asm/reg.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 10caa145f98b..39b4c0a519f5 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -38,6 +38,7 @@
 #define MSR_TM_LG	32		/* Trans Mem Available */
 #define MSR_VEC_LG	25	        /* Enable AltiVec */
 #define MSR_VSX_LG	23		/* Enable VSX */
+#define MSR_S_LG	22		/* Secure VM bit */
 #define MSR_POW_LG	18		/* Enable Power Management */
 #define MSR_WE_LG	18		/* Wait State Enable */
 #define MSR_TGPR_LG	17		/* TLB Update registers in use */
@@ -71,11 +72,13 @@
 #define MSR_SF		__MASK(MSR_SF_LG)	/* Enable 64 bit mode */
 #define MSR_ISF		__MASK(MSR_ISF_LG)	/* Interrupt 64b mode valid on 630 */
 #define MSR_HV 		__MASK(MSR_HV_LG)	/* Hypervisor state */
+#define MSR_S		__MASK(MSR_S_LG)	/* Secure state */
 #else
 /* so tests for these bits fail on 32-bit */
 #define MSR_SF		0
 #define MSR_ISF		0
 #define MSR_HV		0
+#define MSR_S		0
 #endif
 
 /*
-- 
2.20.1

WARNING: multiple messages have this Message-ID (diff)
From: Claudio Carvalho <cclaudio@linux.ibm.com>
To: linuxppc-dev@ozlabs.org
Cc: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>,
	Michael Anderson <andmike@linux.ibm.com>,
	Ram Pai <linuxram@us.ibm.com>,
	Claudio Carvalho <cclaudio@linux.ibm.com>,
	kvm-ppc@vger.kernel.org, Bharata B Rao <bharata@linux.ibm.com>,
	Ryan Grimm <grimm@linux.ibm.com>,
	Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>,
	Thiago Bauermann <bauerman@linux.ibm.com>,
	Anshuman Khandual <khandual@linux.vnet.ibm.com>
Subject: [PATCH v4 1/8] KVM: PPC: Ultravisor: Introduce the MSR_S bit
Date: Fri, 28 Jun 2019 17:08:18 -0300	[thread overview]
Message-ID: <20190628200825.31049-2-cclaudio@linux.ibm.com> (raw)
In-Reply-To: <20190628200825.31049-1-cclaudio@linux.ibm.com>

From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>

The ultravisor processor mode is introduced in POWER platforms that
supports the Protected Execution Facility (PEF). Ultravisor is higher
privileged than hypervisor mode.

In PEF enabled platforms, the MSR_S bit is used to indicate if the
thread is in secure state. With the MSR_S bit, the privilege state of
the thread is now determined by MSR_S, MSR_HV and MSR_PR, as follows:

S   HV  PR
-----------------------
0   x   1   problem
1   0   1   problem
x   x   0   privileged
x   1   0   hypervisor
1   1   0   ultravisor
1   1   1   reserved

The hypervisor doesn't (and can't) run with the MSR_S bit set, but a
secure guest and the ultravisor firmware do.

Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Signed-off-by: Ram Pai <linuxram@us.ibm.com>
[ Update the commit message ]
Signed-off-by: Claudio Carvalho <cclaudio@linux.ibm.com>
---
 arch/powerpc/include/asm/reg.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 10caa145f98b..39b4c0a519f5 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -38,6 +38,7 @@
 #define MSR_TM_LG	32		/* Trans Mem Available */
 #define MSR_VEC_LG	25	        /* Enable AltiVec */
 #define MSR_VSX_LG	23		/* Enable VSX */
+#define MSR_S_LG	22		/* Secure VM bit */
 #define MSR_POW_LG	18		/* Enable Power Management */
 #define MSR_WE_LG	18		/* Wait State Enable */
 #define MSR_TGPR_LG	17		/* TLB Update registers in use */
@@ -71,11 +72,13 @@
 #define MSR_SF		__MASK(MSR_SF_LG)	/* Enable 64 bit mode */
 #define MSR_ISF		__MASK(MSR_ISF_LG)	/* Interrupt 64b mode valid on 630 */
 #define MSR_HV 		__MASK(MSR_HV_LG)	/* Hypervisor state */
+#define MSR_S		__MASK(MSR_S_LG)	/* Secure state */
 #else
 /* so tests for these bits fail on 32-bit */
 #define MSR_SF		0
 #define MSR_ISF		0
 #define MSR_HV		0
+#define MSR_S		0
 #endif
 
 /*
-- 
2.20.1


  reply	other threads:[~2019-06-28 20:08 UTC|newest]

Thread overview: 97+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-28 20:08 [PATCH v4 0/8] kvmppc: Paravirtualize KVM to support ultravisor Claudio Carvalho
2019-06-28 20:08 ` Claudio Carvalho
2019-06-28 20:08 ` Claudio Carvalho [this message]
2019-06-28 20:08   ` [PATCH v4 1/8] KVM: PPC: Ultravisor: Introduce the MSR_S bit Claudio Carvalho
2019-07-08 17:38   ` janani
2019-07-08 17:38     ` janani
2019-07-11 12:57   ` Michael Ellerman
2019-07-11 12:57     ` Michael Ellerman
2019-07-12  0:59     ` Nicholas Piggin
2019-07-12  0:59       ` Nicholas Piggin
2019-07-12  0:57   ` Nicholas Piggin
2019-07-12  0:57     ` Nicholas Piggin
2019-07-12  6:29     ` Michael Ellerman
2019-07-12  6:29       ` Michael Ellerman
2019-07-12 21:07     ` Claudio Carvalho
2019-07-12 21:07       ` Claudio Carvalho
2019-06-28 20:08 ` [PATCH v4 2/8] powerpc: Introduce FW_FEATURE_ULTRAVISOR Claudio Carvalho
2019-06-28 20:08   ` Claudio Carvalho
2019-07-08 17:40   ` janani
2019-07-08 17:40     ` janani
2019-07-11 12:57   ` Michael Ellerman
2019-07-11 12:57     ` Michael Ellerman
2019-07-12 18:01     ` Claudio Carvalho
2019-07-15  4:10       ` Michael Ellerman
2019-07-15  4:10         ` Michael Ellerman
2019-06-28 20:08 ` [PATCH v4 3/8] KVM: PPC: Ultravisor: Add generic ultravisor call handler Claudio Carvalho
2019-06-28 20:08   ` Claudio Carvalho
2019-07-08 17:55   ` janani
2019-07-08 17:55     ` janani
2019-07-11 12:57   ` Michael Ellerman
2019-07-11 12:57     ` Michael Ellerman
2019-07-13 17:42     ` Claudio Carvalho
2019-07-13 17:42       ` Claudio Carvalho
2019-07-15  4:46       ` Michael Ellerman
2019-07-15  4:46         ` Michael Ellerman
2019-07-12  1:18   ` Nicholas Piggin
2019-07-12  1:18     ` Nicholas Piggin
2019-06-28 20:08 ` [PATCH v4 4/8] KVM: PPC: Ultravisor: Use UV_WRITE_PATE ucall to register a PATE Claudio Carvalho
2019-06-28 20:08   ` Claudio Carvalho
2019-07-08 17:57   ` janani
2019-07-08 17:57     ` janani
2019-07-11 12:57   ` Michael Ellerman
2019-07-11 12:57     ` Michael Ellerman
2019-07-17 14:59     ` Ryan Grimm
2019-07-17 14:59       ` Ryan Grimm
2019-07-18 21:25     ` Claudio Carvalho
2019-07-18 21:25       ` Claudio Carvalho
2019-07-19  2:25       ` Michael Ellerman
2019-07-19  2:25         ` Michael Ellerman
2019-06-28 20:08 ` [PATCH v4 5/8] KVM: PPC: Ultravisor: Restrict flush of the partition tlb cache Claudio Carvalho
2019-06-28 20:08   ` Claudio Carvalho
2019-07-01  5:54   ` Alexey Kardashevskiy
2019-07-01  5:54     ` Alexey Kardashevskiy
2019-07-08 20:05     ` Claudio Carvalho
2019-07-08 20:05       ` Claudio Carvalho
2019-07-08 19:54   ` janani
2019-07-08 19:54     ` janani
2019-07-10 17:09     ` Ram Pai
2019-07-10 17:09       ` Ram Pai
2019-06-28 20:08 ` [PATCH v4 6/8] KVM: PPC: Ultravisor: Restrict LDBAR access Claudio Carvalho
2019-06-28 20:08   ` Claudio Carvalho
2019-07-01  5:54   ` Alexey Kardashevskiy
2019-07-01  5:54     ` Alexey Kardashevskiy
2019-07-01  6:17     ` maddy
2019-07-01  6:29       ` maddy
2019-07-01  6:30       ` Alexey Kardashevskiy
2019-07-01  6:30         ` Alexey Kardashevskiy
2019-07-01  6:46         ` Ram Pai
2019-07-01  6:46           ` Ram Pai
2019-07-13 17:56           ` Claudio Carvalho
2019-07-13 17:56             ` Claudio Carvalho
2019-07-08 20:22   ` janani
2019-07-08 20:22     ` janani
2019-07-11 12:57   ` Michael Ellerman
2019-07-11 12:57     ` Michael Ellerman
2019-07-15  0:38     ` Claudio Carvalho
2019-07-15  0:38       ` Claudio Carvalho
2019-06-28 20:08 ` [PATCH v4 7/8] KVM: PPC: Ultravisor: Enter a secure guest Claudio Carvalho
2019-06-28 20:08   ` Claudio Carvalho
2019-07-08 20:53   ` janani
2019-07-08 20:53     ` janani
2019-07-08 20:52     ` Claudio Carvalho
2019-07-08 20:52       ` Claudio Carvalho
2019-07-11 12:57   ` Michael Ellerman
2019-07-11 12:57     ` Michael Ellerman
2019-07-18  2:47     ` Sukadev Bhattiprolu
2019-07-18  2:47       ` Sukadev Bhattiprolu
2019-07-22 11:05       ` Michael Ellerman
2019-07-22 11:05         ` Michael Ellerman
2019-07-12  2:03   ` Nicholas Piggin
2019-07-12  2:03     ` Nicholas Piggin
2019-06-28 20:08 ` [PATCH v4 8/8] KVM: PPC: Ultravisor: Check for MSR_S during hv_reset_msr Claudio Carvalho
2019-06-28 20:08   ` Claudio Carvalho
2019-07-08 20:54   ` janani
2019-07-08 20:54     ` janani
2019-07-11 12:57   ` Michael Ellerman
2019-07-11 12:57     ` Michael Ellerman

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