* [PATCH v3] drm/dp: Add function to parse EDID descriptors for adaptive sync limits @ 2020-03-03 0:08 ` Manasi Navare 0 siblings, 0 replies; 11+ messages in thread From: Manasi Navare @ 2020-03-03 0:08 UTC (permalink / raw) To: intel-gfx, dri-devel; +Cc: Kazlauskas, Manasi Navare, Nicholas Adaptive Sync is a VESA feature so add a DRM core helper to parse the EDID's detailed descritors to obtain the adaptive sync monitor range. Store this info as part fo drm_display_info so it can be used across all drivers. This part of the code is stripped out of amdgpu's function amdgpu_dm_update_freesync_caps() to make it generic and be used across all DRM drivers v3: * Remove the edid parsing restriction for just DP (Nicholas) * Use drm_for_each_detailed_block (Ville) * Make the drm_get_adaptive_sync_range function static (Harry, Jani) v2: * Change vmin and vmax to use u8 (Ville) * Dont store pixel clock since that is just a max dotclock and not related to VRR mode (Manasi) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Clinton A Taylor <clinton.a.taylor@intel.com> Cc: Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/drm_edid.c | 44 +++++++++++++++++++++++++++++++++++++ include/drm/drm_connector.h | 22 +++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index ad41764a4ebe..e3f152180b6b 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -4938,6 +4938,47 @@ static void drm_parse_cea_ext(struct drm_connector *connector, } } +static +void get_adaptive_sync_range(struct detailed_timing *timing, + void *info_adaptive_sync) +{ + struct drm_adaptive_sync_info *adaptive_sync = info_adaptive_sync; + const struct detailed_non_pixel *data = &timing->data.other_data; + const struct detailed_data_monitor_range *range = &data->data.range; + + if (data->type != EDID_DETAIL_MONITOR_RANGE) + return; + + /* + * Check for flag range limits only. If flag == 1 then + * no additional timing information provided. + * Default GTF, GTF Secondary curve and CVT are not + * supported + */ + if (range->flags != 1) + return; + + adaptive_sync->min_vfreq = range->min_vfreq; + adaptive_sync->max_vfreq = range->max_vfreq; +} + +static +void drm_get_adaptive_sync_range(struct drm_connector *connector, + const struct edid *edid) +{ + struct drm_display_info *info = &connector->display_info; + + if (!version_greater(edid, 1, 1)) + return; + + drm_for_each_detailed_block((u8 *)edid, get_adaptive_sync_range, + &info->adaptive_sync); + + DRM_DEBUG_KMS("Adaptive Sync refresh rate range is %d Hz - %d Hz\n", + info->adaptive_sync.min_vfreq, + info->adaptive_sync.max_vfreq); +} + /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset * all of the values which would have been set from EDID */ @@ -4960,6 +5001,7 @@ drm_reset_display_info(struct drm_connector *connector) memset(&info->hdmi, 0, sizeof(info->hdmi)); info->non_desktop = 0; + memset(&info->adaptive_sync, 0, sizeof(info->adaptive_sync)); } u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) @@ -4975,6 +5017,8 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); + drm_get_adaptive_sync_range(connector, edid); + DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); if (edid->revision < 3) diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index 0df7a95ca5d9..2b22c0fa42c4 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -254,6 +254,23 @@ enum drm_panel_orientation { DRM_MODE_PANEL_ORIENTATION_RIGHT_UP, }; +/** + * struct drm_adaptive_sync_info - Panel's Adaptive Sync capabilities for + * &drm_display_info + * + * This struct is used to store a Panel's Adaptive Sync capabilities + * as parsed from EDID's detailed monitor range descriptor block. + * + * @min_vfreq: This is the min supported refresh rate in Hz from + * EDID's detailed monitor range. + * @max_vfreq: This is the max supported refresh rate in Hz from + * EDID's detailed monitor range + */ +struct drm_adaptive_sync_info { + u8 min_vfreq; + u8 max_vfreq; +}; + /* * This is a consolidated colorimetry list supported by HDMI and * DP protocol standard. The respective connectors will register @@ -473,6 +490,11 @@ struct drm_display_info { * @non_desktop: Non desktop display (HMD). */ bool non_desktop; + + /** + * @adaptive_sync: Adaptive Sync capabilities of the DP/eDP sink + */ + struct drm_adaptive_sync_info adaptive_sync; }; int drm_display_info_set_bus_formats(struct drm_display_info *info, -- 2.19.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] [PATCH v3] drm/dp: Add function to parse EDID descriptors for adaptive sync limits @ 2020-03-03 0:08 ` Manasi Navare 0 siblings, 0 replies; 11+ messages in thread From: Manasi Navare @ 2020-03-03 0:08 UTC (permalink / raw) To: intel-gfx, dri-devel; +Cc: Kazlauskas, Harry Wentland, Nicholas Adaptive Sync is a VESA feature so add a DRM core helper to parse the EDID's detailed descritors to obtain the adaptive sync monitor range. Store this info as part fo drm_display_info so it can be used across all drivers. This part of the code is stripped out of amdgpu's function amdgpu_dm_update_freesync_caps() to make it generic and be used across all DRM drivers v3: * Remove the edid parsing restriction for just DP (Nicholas) * Use drm_for_each_detailed_block (Ville) * Make the drm_get_adaptive_sync_range function static (Harry, Jani) v2: * Change vmin and vmax to use u8 (Ville) * Dont store pixel clock since that is just a max dotclock and not related to VRR mode (Manasi) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Clinton A Taylor <clinton.a.taylor@intel.com> Cc: Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/drm_edid.c | 44 +++++++++++++++++++++++++++++++++++++ include/drm/drm_connector.h | 22 +++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index ad41764a4ebe..e3f152180b6b 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -4938,6 +4938,47 @@ static void drm_parse_cea_ext(struct drm_connector *connector, } } +static +void get_adaptive_sync_range(struct detailed_timing *timing, + void *info_adaptive_sync) +{ + struct drm_adaptive_sync_info *adaptive_sync = info_adaptive_sync; + const struct detailed_non_pixel *data = &timing->data.other_data; + const struct detailed_data_monitor_range *range = &data->data.range; + + if (data->type != EDID_DETAIL_MONITOR_RANGE) + return; + + /* + * Check for flag range limits only. If flag == 1 then + * no additional timing information provided. + * Default GTF, GTF Secondary curve and CVT are not + * supported + */ + if (range->flags != 1) + return; + + adaptive_sync->min_vfreq = range->min_vfreq; + adaptive_sync->max_vfreq = range->max_vfreq; +} + +static +void drm_get_adaptive_sync_range(struct drm_connector *connector, + const struct edid *edid) +{ + struct drm_display_info *info = &connector->display_info; + + if (!version_greater(edid, 1, 1)) + return; + + drm_for_each_detailed_block((u8 *)edid, get_adaptive_sync_range, + &info->adaptive_sync); + + DRM_DEBUG_KMS("Adaptive Sync refresh rate range is %d Hz - %d Hz\n", + info->adaptive_sync.min_vfreq, + info->adaptive_sync.max_vfreq); +} + /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset * all of the values which would have been set from EDID */ @@ -4960,6 +5001,7 @@ drm_reset_display_info(struct drm_connector *connector) memset(&info->hdmi, 0, sizeof(info->hdmi)); info->non_desktop = 0; + memset(&info->adaptive_sync, 0, sizeof(info->adaptive_sync)); } u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) @@ -4975,6 +5017,8 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); + drm_get_adaptive_sync_range(connector, edid); + DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); if (edid->revision < 3) diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index 0df7a95ca5d9..2b22c0fa42c4 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -254,6 +254,23 @@ enum drm_panel_orientation { DRM_MODE_PANEL_ORIENTATION_RIGHT_UP, }; +/** + * struct drm_adaptive_sync_info - Panel's Adaptive Sync capabilities for + * &drm_display_info + * + * This struct is used to store a Panel's Adaptive Sync capabilities + * as parsed from EDID's detailed monitor range descriptor block. + * + * @min_vfreq: This is the min supported refresh rate in Hz from + * EDID's detailed monitor range. + * @max_vfreq: This is the max supported refresh rate in Hz from + * EDID's detailed monitor range + */ +struct drm_adaptive_sync_info { + u8 min_vfreq; + u8 max_vfreq; +}; + /* * This is a consolidated colorimetry list supported by HDMI and * DP protocol standard. The respective connectors will register @@ -473,6 +490,11 @@ struct drm_display_info { * @non_desktop: Non desktop display (HMD). */ bool non_desktop; + + /** + * @adaptive_sync: Adaptive Sync capabilities of the DP/eDP sink + */ + struct drm_adaptive_sync_info adaptive_sync; }; int drm_display_info_set_bus_formats(struct drm_display_info *info, -- 2.19.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/dp: Add function to parse EDID descriptors for adaptive sync limits (rev2) 2020-03-03 0:08 ` [Intel-gfx] " Manasi Navare (?) @ 2020-03-03 1:53 ` Patchwork -1 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2020-03-03 1:53 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx == Series Details == Series: drm/dp: Add function to parse EDID descriptors for adaptive sync limits (rev2) URL : https://patchwork.freedesktop.org/series/68488/ State : warning == Summary == $ make htmldocs 2>&1 > /dev/null | grep i915 Error: Cannot open file ./drivers/gpu/drm/i915/intel_csr.c Error: Cannot open file ./drivers/gpu/drm/i915/intel_csr.c Error: Cannot open file ./drivers/gpu/drm/i915/intel_csr.c ./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq' not described in 'intel_shared_dpll_funcs' ./drivers/gpu/drm/i915/i915_vma.h:1: warning: 'Virtual Memory Address' not found ./drivers/gpu/drm/i915/i915_gem_gtt.c:1: warning: 'Global GTT views' not found WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function csr support for dmc ./drivers/gpu/drm/i915/intel_csr.c' failed with return code 1 WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -internal ./drivers/gpu/drm/i915/intel_csr.c' failed with return code 2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/dp: Add function to parse EDID descriptors for adaptive sync limits (rev2) 2020-03-03 0:08 ` [Intel-gfx] " Manasi Navare (?) (?) @ 2020-03-03 2:13 ` Patchwork -1 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2020-03-03 2:13 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx == Series Details == Series: drm/dp: Add function to parse EDID descriptors for adaptive sync limits (rev2) URL : https://patchwork.freedesktop.org/series/68488/ State : success == Summary == CI Bug Log - changes from CI_DRM_8050 -> Patchwork_16790 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/index.html Known issues ------------ Here are the changes found in Patchwork_16790 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live@gem_contexts: - fi-cfl-guc: [PASS][1] -> [INCOMPLETE][2] ([fdo#106070] / [i915#424]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/fi-cfl-guc/igt@i915_selftest@live@gem_contexts.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-icl-u2: [PASS][3] -> [FAIL][4] ([i915#217]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html * igt@prime_self_import@basic-llseek-bad: - fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([CI#94] / [i915#402]) +1 similar issue [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/fi-tgl-y/igt@prime_self_import@basic-llseek-bad.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/fi-tgl-y/igt@prime_self_import@basic-llseek-bad.html #### Possible fixes #### * igt@i915_selftest@live@execlists: - fi-icl-y: [DMESG-FAIL][7] ([fdo#108569]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/fi-icl-y/igt@i915_selftest@live@execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/fi-icl-y/igt@i915_selftest@live@execlists.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][9] ([fdo#111096] / [i915#323]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html * igt@prime_self_import@basic-with_fd_dup: - fi-tgl-y: [DMESG-WARN][11] ([CI#94] / [i915#402]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/fi-tgl-y/igt@prime_self_import@basic-with_fd_dup.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/fi-tgl-y/igt@prime_self_import@basic-with_fd_dup.html [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94 [fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424 Participating hosts (46 -> 42) ------------------------------ Additional (4): fi-bsw-kefka fi-gdg-551 fi-snb-2520m fi-elk-e7500 Missing (8): fi-hsw-4200u fi-glk-dsi fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-n2820 fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_8050 -> Patchwork_16790 CI-20190529: 20190529 CI_DRM_8050: 422d76f5669ce8b7cd0c579f60628877159cbe7c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5484: 91b36b61e76901a2bd09fe93ac7bf7b8a60f258c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16790: 2495771ecf20343ab2818cd325a319fb42577522 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 2495771ecf20 drm/dp: Add function to parse EDID descriptors for adaptive sync limits == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3] drm/dp: Add function to parse EDID descriptors for adaptive sync limits 2020-03-03 0:08 ` [Intel-gfx] " Manasi Navare @ 2020-03-03 13:42 ` Ville Syrjälä -1 siblings, 0 replies; 11+ messages in thread From: Ville Syrjälä @ 2020-03-03 13:42 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx, dri-devel, Kazlauskas, Nicholas On Mon, Mar 02, 2020 at 04:08:59PM -0800, Manasi Navare wrote: > Adaptive Sync is a VESA feature so add a DRM core helper to parse > the EDID's detailed descritors to obtain the adaptive sync monitor range. > Store this info as part fo drm_display_info so it can be used > across all drivers. > This part of the code is stripped out of amdgpu's function > amdgpu_dm_update_freesync_caps() to make it generic and be used > across all DRM drivers > > v3: > * Remove the edid parsing restriction for just DP (Nicholas) > * Use drm_for_each_detailed_block (Ville) > * Make the drm_get_adaptive_sync_range function static (Harry, Jani) > v2: > * Change vmin and vmax to use u8 (Ville) > * Dont store pixel clock since that is just a max dotclock > and not related to VRR mode (Manasi) > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Harry Wentland <harry.wentland@amd.com> > Cc: Clinton A Taylor <clinton.a.taylor@intel.com> > Cc: Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > --- > drivers/gpu/drm/drm_edid.c | 44 +++++++++++++++++++++++++++++++++++++ > include/drm/drm_connector.h | 22 +++++++++++++++++++ > 2 files changed, 66 insertions(+) > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c > index ad41764a4ebe..e3f152180b6b 100644 > --- a/drivers/gpu/drm/drm_edid.c > +++ b/drivers/gpu/drm/drm_edid.c > @@ -4938,6 +4938,47 @@ static void drm_parse_cea_ext(struct drm_connector *connector, > } > } > > +static > +void get_adaptive_sync_range(struct detailed_timing *timing, > + void *info_adaptive_sync) > +{ > + struct drm_adaptive_sync_info *adaptive_sync = info_adaptive_sync; > + const struct detailed_non_pixel *data = &timing->data.other_data; > + const struct detailed_data_monitor_range *range = &data->data.range; > + > + if (data->type != EDID_DETAIL_MONITOR_RANGE)a is_display_descriptor() > + return; > + > + /* > + * Check for flag range limits only. If flag == 1 then > + * no additional timing information provided. > + * Default GTF, GTF Secondary curve and CVT are not > + * supported > + */ > + if (range->flags != 1) Pls name the flags. > + return; > + > + adaptive_sync->min_vfreq = range->min_vfreq; > + adaptive_sync->max_vfreq = range->max_vfreq; > +} > + > +static > +void drm_get_adaptive_sync_range(struct drm_connector *connector, > + const struct edid *edid) > +{ > + struct drm_display_info *info = &connector->display_info; > + > + if (!version_greater(edid, 1, 1)) > + return; > + > + drm_for_each_detailed_block((u8 *)edid, get_adaptive_sync_range, > + &info->adaptive_sync); > + > + DRM_DEBUG_KMS("Adaptive Sync refresh rate range is %d Hz - %d Hz\n", > + info->adaptive_sync.min_vfreq, > + info->adaptive_sync.max_vfreq); > +} > + > /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset > * all of the values which would have been set from EDID > */ > @@ -4960,6 +5001,7 @@ drm_reset_display_info(struct drm_connector *connector) > memset(&info->hdmi, 0, sizeof(info->hdmi)); > > info->non_desktop = 0; > + memset(&info->adaptive_sync, 0, sizeof(info->adaptive_sync)); > } > > u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) > @@ -4975,6 +5017,8 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi > > info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); > > + drm_get_adaptive_sync_range(connector, edid); > + > DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); > > if (edid->revision < 3) > diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h > index 0df7a95ca5d9..2b22c0fa42c4 100644 > --- a/include/drm/drm_connector.h > +++ b/include/drm/drm_connector.h > @@ -254,6 +254,23 @@ enum drm_panel_orientation { > DRM_MODE_PANEL_ORIENTATION_RIGHT_UP, > }; > > +/** > + * struct drm_adaptive_sync_info - Panel's Adaptive Sync capabilities for > + * &drm_display_info > + * > + * This struct is used to store a Panel's Adaptive Sync capabilities > + * as parsed from EDID's detailed monitor range descriptor block. > + * > + * @min_vfreq: This is the min supported refresh rate in Hz from > + * EDID's detailed monitor range. > + * @max_vfreq: This is the max supported refresh rate in Hz from > + * EDID's detailed monitor range > + */ > +struct drm_adaptive_sync_info { > + u8 min_vfreq; > + u8 max_vfreq; > +}; > + > /* > * This is a consolidated colorimetry list supported by HDMI and > * DP protocol standard. The respective connectors will register > @@ -473,6 +490,11 @@ struct drm_display_info { > * @non_desktop: Non desktop display (HMD). > */ > bool non_desktop; > + > + /** > + * @adaptive_sync: Adaptive Sync capabilities of the DP/eDP sink > + */ > + struct drm_adaptive_sync_info adaptive_sync; > }; > > int drm_display_info_set_bus_formats(struct drm_display_info *info, > -- > 2.19.1 -- Ville Syrjälä Intel _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH v3] drm/dp: Add function to parse EDID descriptors for adaptive sync limits @ 2020-03-03 13:42 ` Ville Syrjälä 0 siblings, 0 replies; 11+ messages in thread From: Ville Syrjälä @ 2020-03-03 13:42 UTC (permalink / raw) To: Manasi Navare; +Cc: Harry Wentland, intel-gfx, dri-devel, Kazlauskas, Nicholas On Mon, Mar 02, 2020 at 04:08:59PM -0800, Manasi Navare wrote: > Adaptive Sync is a VESA feature so add a DRM core helper to parse > the EDID's detailed descritors to obtain the adaptive sync monitor range. > Store this info as part fo drm_display_info so it can be used > across all drivers. > This part of the code is stripped out of amdgpu's function > amdgpu_dm_update_freesync_caps() to make it generic and be used > across all DRM drivers > > v3: > * Remove the edid parsing restriction for just DP (Nicholas) > * Use drm_for_each_detailed_block (Ville) > * Make the drm_get_adaptive_sync_range function static (Harry, Jani) > v2: > * Change vmin and vmax to use u8 (Ville) > * Dont store pixel clock since that is just a max dotclock > and not related to VRR mode (Manasi) > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Harry Wentland <harry.wentland@amd.com> > Cc: Clinton A Taylor <clinton.a.taylor@intel.com> > Cc: Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > --- > drivers/gpu/drm/drm_edid.c | 44 +++++++++++++++++++++++++++++++++++++ > include/drm/drm_connector.h | 22 +++++++++++++++++++ > 2 files changed, 66 insertions(+) > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c > index ad41764a4ebe..e3f152180b6b 100644 > --- a/drivers/gpu/drm/drm_edid.c > +++ b/drivers/gpu/drm/drm_edid.c > @@ -4938,6 +4938,47 @@ static void drm_parse_cea_ext(struct drm_connector *connector, > } > } > > +static > +void get_adaptive_sync_range(struct detailed_timing *timing, > + void *info_adaptive_sync) > +{ > + struct drm_adaptive_sync_info *adaptive_sync = info_adaptive_sync; > + const struct detailed_non_pixel *data = &timing->data.other_data; > + const struct detailed_data_monitor_range *range = &data->data.range; > + > + if (data->type != EDID_DETAIL_MONITOR_RANGE)a is_display_descriptor() > + return; > + > + /* > + * Check for flag range limits only. If flag == 1 then > + * no additional timing information provided. > + * Default GTF, GTF Secondary curve and CVT are not > + * supported > + */ > + if (range->flags != 1) Pls name the flags. > + return; > + > + adaptive_sync->min_vfreq = range->min_vfreq; > + adaptive_sync->max_vfreq = range->max_vfreq; > +} > + > +static > +void drm_get_adaptive_sync_range(struct drm_connector *connector, > + const struct edid *edid) > +{ > + struct drm_display_info *info = &connector->display_info; > + > + if (!version_greater(edid, 1, 1)) > + return; > + > + drm_for_each_detailed_block((u8 *)edid, get_adaptive_sync_range, > + &info->adaptive_sync); > + > + DRM_DEBUG_KMS("Adaptive Sync refresh rate range is %d Hz - %d Hz\n", > + info->adaptive_sync.min_vfreq, > + info->adaptive_sync.max_vfreq); > +} > + > /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset > * all of the values which would have been set from EDID > */ > @@ -4960,6 +5001,7 @@ drm_reset_display_info(struct drm_connector *connector) > memset(&info->hdmi, 0, sizeof(info->hdmi)); > > info->non_desktop = 0; > + memset(&info->adaptive_sync, 0, sizeof(info->adaptive_sync)); > } > > u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) > @@ -4975,6 +5017,8 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi > > info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); > > + drm_get_adaptive_sync_range(connector, edid); > + > DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); > > if (edid->revision < 3) > diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h > index 0df7a95ca5d9..2b22c0fa42c4 100644 > --- a/include/drm/drm_connector.h > +++ b/include/drm/drm_connector.h > @@ -254,6 +254,23 @@ enum drm_panel_orientation { > DRM_MODE_PANEL_ORIENTATION_RIGHT_UP, > }; > > +/** > + * struct drm_adaptive_sync_info - Panel's Adaptive Sync capabilities for > + * &drm_display_info > + * > + * This struct is used to store a Panel's Adaptive Sync capabilities > + * as parsed from EDID's detailed monitor range descriptor block. > + * > + * @min_vfreq: This is the min supported refresh rate in Hz from > + * EDID's detailed monitor range. > + * @max_vfreq: This is the max supported refresh rate in Hz from > + * EDID's detailed monitor range > + */ > +struct drm_adaptive_sync_info { > + u8 min_vfreq; > + u8 max_vfreq; > +}; > + > /* > * This is a consolidated colorimetry list supported by HDMI and > * DP protocol standard. The respective connectors will register > @@ -473,6 +490,11 @@ struct drm_display_info { > * @non_desktop: Non desktop display (HMD). > */ > bool non_desktop; > + > + /** > + * @adaptive_sync: Adaptive Sync capabilities of the DP/eDP sink > + */ > + struct drm_adaptive_sync_info adaptive_sync; > }; > > int drm_display_info_set_bus_formats(struct drm_display_info *info, > -- > 2.19.1 -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3] drm/dp: Add function to parse EDID descriptors for adaptive sync limits 2020-03-03 13:42 ` [Intel-gfx] " Ville Syrjälä @ 2020-03-04 17:36 ` Manasi Navare -1 siblings, 0 replies; 11+ messages in thread From: Manasi Navare @ 2020-03-04 17:36 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx, Kazlauskas, dri-devel, Nicholas On Tue, Mar 03, 2020 at 03:42:12PM +0200, Ville Syrjälä wrote: > On Mon, Mar 02, 2020 at 04:08:59PM -0800, Manasi Navare wrote: > > Adaptive Sync is a VESA feature so add a DRM core helper to parse > > the EDID's detailed descritors to obtain the adaptive sync monitor range. > > Store this info as part fo drm_display_info so it can be used > > across all drivers. > > This part of the code is stripped out of amdgpu's function > > amdgpu_dm_update_freesync_caps() to make it generic and be used > > across all DRM drivers > > > > v3: > > * Remove the edid parsing restriction for just DP (Nicholas) > > * Use drm_for_each_detailed_block (Ville) > > * Make the drm_get_adaptive_sync_range function static (Harry, Jani) > > v2: > > * Change vmin and vmax to use u8 (Ville) > > * Dont store pixel clock since that is just a max dotclock > > and not related to VRR mode (Manasi) > > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Cc: Harry Wentland <harry.wentland@amd.com> > > Cc: Clinton A Taylor <clinton.a.taylor@intel.com> > > Cc: Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > --- > > drivers/gpu/drm/drm_edid.c | 44 +++++++++++++++++++++++++++++++++++++ > > include/drm/drm_connector.h | 22 +++++++++++++++++++ > > 2 files changed, 66 insertions(+) > > > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c > > index ad41764a4ebe..e3f152180b6b 100644 > > --- a/drivers/gpu/drm/drm_edid.c > > +++ b/drivers/gpu/drm/drm_edid.c > > @@ -4938,6 +4938,47 @@ static void drm_parse_cea_ext(struct drm_connector *connector, > > } > > } > > > > +static > > +void get_adaptive_sync_range(struct detailed_timing *timing, > > + void *info_adaptive_sync) > > +{ > > + struct drm_adaptive_sync_info *adaptive_sync = info_adaptive_sync; > > + const struct detailed_non_pixel *data = &timing->data.other_data; > > + const struct detailed_data_monitor_range *range = &data->data.range; > > + > > + if (data->type != EDID_DETAIL_MONITOR_RANGE)a > > is_display_descriptor() Will change to use is_display_descriptor() > > > + return; > > + > > + /* > > + * Check for flag range limits only. If flag == 1 then > > + * no additional timing information provided. > > + * Default GTF, GTF Secondary curve and CVT are not > > + * supported > > + */ > > + if (range->flags != 1) > > Pls name the flags. I dont see that we have any enum with the flag names, do you want me to define them looking at EDID spec? Manasi > > > + return; > > + > > + adaptive_sync->min_vfreq = range->min_vfreq; > > + adaptive_sync->max_vfreq = range->max_vfreq; > > +} > > + > > +static > > +void drm_get_adaptive_sync_range(struct drm_connector *connector, > > + const struct edid *edid) > > +{ > > + struct drm_display_info *info = &connector->display_info; > > + > > + if (!version_greater(edid, 1, 1)) > > + return; > > + > > + drm_for_each_detailed_block((u8 *)edid, get_adaptive_sync_range, > > + &info->adaptive_sync); > > + > > + DRM_DEBUG_KMS("Adaptive Sync refresh rate range is %d Hz - %d Hz\n", > > + info->adaptive_sync.min_vfreq, > > + info->adaptive_sync.max_vfreq); > > +} > > + > > /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset > > * all of the values which would have been set from EDID > > */ > > @@ -4960,6 +5001,7 @@ drm_reset_display_info(struct drm_connector *connector) > > memset(&info->hdmi, 0, sizeof(info->hdmi)); > > > > info->non_desktop = 0; > > + memset(&info->adaptive_sync, 0, sizeof(info->adaptive_sync)); > > } > > > > u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) > > @@ -4975,6 +5017,8 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi > > > > info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); > > > > + drm_get_adaptive_sync_range(connector, edid); > > + > > DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); > > > > if (edid->revision < 3) > > diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h > > index 0df7a95ca5d9..2b22c0fa42c4 100644 > > --- a/include/drm/drm_connector.h > > +++ b/include/drm/drm_connector.h > > @@ -254,6 +254,23 @@ enum drm_panel_orientation { > > DRM_MODE_PANEL_ORIENTATION_RIGHT_UP, > > }; > > > > +/** > > + * struct drm_adaptive_sync_info - Panel's Adaptive Sync capabilities for > > + * &drm_display_info > > + * > > + * This struct is used to store a Panel's Adaptive Sync capabilities > > + * as parsed from EDID's detailed monitor range descriptor block. > > + * > > + * @min_vfreq: This is the min supported refresh rate in Hz from > > + * EDID's detailed monitor range. > > + * @max_vfreq: This is the max supported refresh rate in Hz from > > + * EDID's detailed monitor range > > + */ > > +struct drm_adaptive_sync_info { > > + u8 min_vfreq; > > + u8 max_vfreq; > > +}; > > + > > /* > > * This is a consolidated colorimetry list supported by HDMI and > > * DP protocol standard. The respective connectors will register > > @@ -473,6 +490,11 @@ struct drm_display_info { > > * @non_desktop: Non desktop display (HMD). > > */ > > bool non_desktop; > > + > > + /** > > + * @adaptive_sync: Adaptive Sync capabilities of the DP/eDP sink > > + */ > > + struct drm_adaptive_sync_info adaptive_sync; > > }; > > > > int drm_display_info_set_bus_formats(struct drm_display_info *info, > > -- > > 2.19.1 > > -- > Ville Syrjälä > Intel > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH v3] drm/dp: Add function to parse EDID descriptors for adaptive sync limits @ 2020-03-04 17:36 ` Manasi Navare 0 siblings, 0 replies; 11+ messages in thread From: Manasi Navare @ 2020-03-04 17:36 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx, Kazlauskas, dri-devel, Nicholas On Tue, Mar 03, 2020 at 03:42:12PM +0200, Ville Syrjälä wrote: > On Mon, Mar 02, 2020 at 04:08:59PM -0800, Manasi Navare wrote: > > Adaptive Sync is a VESA feature so add a DRM core helper to parse > > the EDID's detailed descritors to obtain the adaptive sync monitor range. > > Store this info as part fo drm_display_info so it can be used > > across all drivers. > > This part of the code is stripped out of amdgpu's function > > amdgpu_dm_update_freesync_caps() to make it generic and be used > > across all DRM drivers > > > > v3: > > * Remove the edid parsing restriction for just DP (Nicholas) > > * Use drm_for_each_detailed_block (Ville) > > * Make the drm_get_adaptive_sync_range function static (Harry, Jani) > > v2: > > * Change vmin and vmax to use u8 (Ville) > > * Dont store pixel clock since that is just a max dotclock > > and not related to VRR mode (Manasi) > > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Cc: Harry Wentland <harry.wentland@amd.com> > > Cc: Clinton A Taylor <clinton.a.taylor@intel.com> > > Cc: Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > --- > > drivers/gpu/drm/drm_edid.c | 44 +++++++++++++++++++++++++++++++++++++ > > include/drm/drm_connector.h | 22 +++++++++++++++++++ > > 2 files changed, 66 insertions(+) > > > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c > > index ad41764a4ebe..e3f152180b6b 100644 > > --- a/drivers/gpu/drm/drm_edid.c > > +++ b/drivers/gpu/drm/drm_edid.c > > @@ -4938,6 +4938,47 @@ static void drm_parse_cea_ext(struct drm_connector *connector, > > } > > } > > > > +static > > +void get_adaptive_sync_range(struct detailed_timing *timing, > > + void *info_adaptive_sync) > > +{ > > + struct drm_adaptive_sync_info *adaptive_sync = info_adaptive_sync; > > + const struct detailed_non_pixel *data = &timing->data.other_data; > > + const struct detailed_data_monitor_range *range = &data->data.range; > > + > > + if (data->type != EDID_DETAIL_MONITOR_RANGE)a > > is_display_descriptor() Will change to use is_display_descriptor() > > > + return; > > + > > + /* > > + * Check for flag range limits only. If flag == 1 then > > + * no additional timing information provided. > > + * Default GTF, GTF Secondary curve and CVT are not > > + * supported > > + */ > > + if (range->flags != 1) > > Pls name the flags. I dont see that we have any enum with the flag names, do you want me to define them looking at EDID spec? Manasi > > > + return; > > + > > + adaptive_sync->min_vfreq = range->min_vfreq; > > + adaptive_sync->max_vfreq = range->max_vfreq; > > +} > > + > > +static > > +void drm_get_adaptive_sync_range(struct drm_connector *connector, > > + const struct edid *edid) > > +{ > > + struct drm_display_info *info = &connector->display_info; > > + > > + if (!version_greater(edid, 1, 1)) > > + return; > > + > > + drm_for_each_detailed_block((u8 *)edid, get_adaptive_sync_range, > > + &info->adaptive_sync); > > + > > + DRM_DEBUG_KMS("Adaptive Sync refresh rate range is %d Hz - %d Hz\n", > > + info->adaptive_sync.min_vfreq, > > + info->adaptive_sync.max_vfreq); > > +} > > + > > /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset > > * all of the values which would have been set from EDID > > */ > > @@ -4960,6 +5001,7 @@ drm_reset_display_info(struct drm_connector *connector) > > memset(&info->hdmi, 0, sizeof(info->hdmi)); > > > > info->non_desktop = 0; > > + memset(&info->adaptive_sync, 0, sizeof(info->adaptive_sync)); > > } > > > > u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) > > @@ -4975,6 +5017,8 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi > > > > info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); > > > > + drm_get_adaptive_sync_range(connector, edid); > > + > > DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); > > > > if (edid->revision < 3) > > diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h > > index 0df7a95ca5d9..2b22c0fa42c4 100644 > > --- a/include/drm/drm_connector.h > > +++ b/include/drm/drm_connector.h > > @@ -254,6 +254,23 @@ enum drm_panel_orientation { > > DRM_MODE_PANEL_ORIENTATION_RIGHT_UP, > > }; > > > > +/** > > + * struct drm_adaptive_sync_info - Panel's Adaptive Sync capabilities for > > + * &drm_display_info > > + * > > + * This struct is used to store a Panel's Adaptive Sync capabilities > > + * as parsed from EDID's detailed monitor range descriptor block. > > + * > > + * @min_vfreq: This is the min supported refresh rate in Hz from > > + * EDID's detailed monitor range. > > + * @max_vfreq: This is the max supported refresh rate in Hz from > > + * EDID's detailed monitor range > > + */ > > +struct drm_adaptive_sync_info { > > + u8 min_vfreq; > > + u8 max_vfreq; > > +}; > > + > > /* > > * This is a consolidated colorimetry list supported by HDMI and > > * DP protocol standard. The respective connectors will register > > @@ -473,6 +490,11 @@ struct drm_display_info { > > * @non_desktop: Non desktop display (HMD). > > */ > > bool non_desktop; > > + > > + /** > > + * @adaptive_sync: Adaptive Sync capabilities of the DP/eDP sink > > + */ > > + struct drm_adaptive_sync_info adaptive_sync; > > }; > > > > int drm_display_info_set_bus_formats(struct drm_display_info *info, > > -- > > 2.19.1 > > -- > Ville Syrjälä > Intel > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3] drm/dp: Add function to parse EDID descriptors for adaptive sync limits 2020-03-04 17:36 ` [Intel-gfx] " Manasi Navare @ 2020-03-04 18:31 ` Ville Syrjälä -1 siblings, 0 replies; 11+ messages in thread From: Ville Syrjälä @ 2020-03-04 18:31 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx, Kazlauskas, dri-devel, Nicholas On Wed, Mar 04, 2020 at 09:36:06AM -0800, Manasi Navare wrote: > On Tue, Mar 03, 2020 at 03:42:12PM +0200, Ville Syrjälä wrote: > > On Mon, Mar 02, 2020 at 04:08:59PM -0800, Manasi Navare wrote: > > > Adaptive Sync is a VESA feature so add a DRM core helper to parse > > > the EDID's detailed descritors to obtain the adaptive sync monitor range. > > > Store this info as part fo drm_display_info so it can be used > > > across all drivers. > > > This part of the code is stripped out of amdgpu's function > > > amdgpu_dm_update_freesync_caps() to make it generic and be used > > > across all DRM drivers > > > > > > v3: > > > * Remove the edid parsing restriction for just DP (Nicholas) > > > * Use drm_for_each_detailed_block (Ville) > > > * Make the drm_get_adaptive_sync_range function static (Harry, Jani) > > > v2: > > > * Change vmin and vmax to use u8 (Ville) > > > * Dont store pixel clock since that is just a max dotclock > > > and not related to VRR mode (Manasi) > > > > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > Cc: Harry Wentland <harry.wentland@amd.com> > > > Cc: Clinton A Taylor <clinton.a.taylor@intel.com> > > > Cc: Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com> > > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > > --- > > > drivers/gpu/drm/drm_edid.c | 44 +++++++++++++++++++++++++++++++++++++ > > > include/drm/drm_connector.h | 22 +++++++++++++++++++ > > > 2 files changed, 66 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c > > > index ad41764a4ebe..e3f152180b6b 100644 > > > --- a/drivers/gpu/drm/drm_edid.c > > > +++ b/drivers/gpu/drm/drm_edid.c > > > @@ -4938,6 +4938,47 @@ static void drm_parse_cea_ext(struct drm_connector *connector, > > > } > > > } > > > > > > +static > > > +void get_adaptive_sync_range(struct detailed_timing *timing, > > > + void *info_adaptive_sync) > > > +{ > > > + struct drm_adaptive_sync_info *adaptive_sync = info_adaptive_sync; > > > + const struct detailed_non_pixel *data = &timing->data.other_data; > > > + const struct detailed_data_monitor_range *range = &data->data.range; > > > + > > > + if (data->type != EDID_DETAIL_MONITOR_RANGE)a > > > > is_display_descriptor() > > Will change to use is_display_descriptor() > > > > > > + return; > > > + > > > + /* > > > + * Check for flag range limits only. If flag == 1 then > > > + * no additional timing information provided. > > > + * Default GTF, GTF Secondary curve and CVT are not > > > + * supported > > > + */ > > > + if (range->flags != 1) > > > > Pls name the flags. > > I dont see that we have any enum with the flag names, do you want me to define them looking > at EDID spec? What else? -- Ville Syrjälä Intel _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH v3] drm/dp: Add function to parse EDID descriptors for adaptive sync limits @ 2020-03-04 18:31 ` Ville Syrjälä 0 siblings, 0 replies; 11+ messages in thread From: Ville Syrjälä @ 2020-03-04 18:31 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx, Kazlauskas, dri-devel, Nicholas On Wed, Mar 04, 2020 at 09:36:06AM -0800, Manasi Navare wrote: > On Tue, Mar 03, 2020 at 03:42:12PM +0200, Ville Syrjälä wrote: > > On Mon, Mar 02, 2020 at 04:08:59PM -0800, Manasi Navare wrote: > > > Adaptive Sync is a VESA feature so add a DRM core helper to parse > > > the EDID's detailed descritors to obtain the adaptive sync monitor range. > > > Store this info as part fo drm_display_info so it can be used > > > across all drivers. > > > This part of the code is stripped out of amdgpu's function > > > amdgpu_dm_update_freesync_caps() to make it generic and be used > > > across all DRM drivers > > > > > > v3: > > > * Remove the edid parsing restriction for just DP (Nicholas) > > > * Use drm_for_each_detailed_block (Ville) > > > * Make the drm_get_adaptive_sync_range function static (Harry, Jani) > > > v2: > > > * Change vmin and vmax to use u8 (Ville) > > > * Dont store pixel clock since that is just a max dotclock > > > and not related to VRR mode (Manasi) > > > > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > Cc: Harry Wentland <harry.wentland@amd.com> > > > Cc: Clinton A Taylor <clinton.a.taylor@intel.com> > > > Cc: Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com> > > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > > --- > > > drivers/gpu/drm/drm_edid.c | 44 +++++++++++++++++++++++++++++++++++++ > > > include/drm/drm_connector.h | 22 +++++++++++++++++++ > > > 2 files changed, 66 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c > > > index ad41764a4ebe..e3f152180b6b 100644 > > > --- a/drivers/gpu/drm/drm_edid.c > > > +++ b/drivers/gpu/drm/drm_edid.c > > > @@ -4938,6 +4938,47 @@ static void drm_parse_cea_ext(struct drm_connector *connector, > > > } > > > } > > > > > > +static > > > +void get_adaptive_sync_range(struct detailed_timing *timing, > > > + void *info_adaptive_sync) > > > +{ > > > + struct drm_adaptive_sync_info *adaptive_sync = info_adaptive_sync; > > > + const struct detailed_non_pixel *data = &timing->data.other_data; > > > + const struct detailed_data_monitor_range *range = &data->data.range; > > > + > > > + if (data->type != EDID_DETAIL_MONITOR_RANGE)a > > > > is_display_descriptor() > > Will change to use is_display_descriptor() > > > > > > + return; > > > + > > > + /* > > > + * Check for flag range limits only. If flag == 1 then > > > + * no additional timing information provided. > > > + * Default GTF, GTF Secondary curve and CVT are not > > > + * supported > > > + */ > > > + if (range->flags != 1) > > > > Pls name the flags. > > I dont see that we have any enum with the flag names, do you want me to define them looking > at EDID spec? What else? -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/dp: Add function to parse EDID descriptors for adaptive sync limits (rev2) 2020-03-03 0:08 ` [Intel-gfx] " Manasi Navare ` (3 preceding siblings ...) (?) @ 2020-03-03 16:17 ` Patchwork -1 siblings, 0 replies; 11+ messages in thread From: Patchwork @ 2020-03-03 16:17 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx == Series Details == Series: drm/dp: Add function to parse EDID descriptors for adaptive sync limits (rev2) URL : https://patchwork.freedesktop.org/series/68488/ State : failure == Summary == CI Bug Log - changes from CI_DRM_8050_full -> Patchwork_16790_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_16790_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_16790_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_16790_full: ### IGT changes ### #### Possible regressions #### * igt@gem_exec_schedule@pi-common-bsd: - shard-skl: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-skl7/igt@gem_exec_schedule@pi-common-bsd.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-skl8/igt@gem_exec_schedule@pi-common-bsd.html * igt@gem_exec_whisper@basic-fds-priority: - shard-iclb: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-iclb1/igt@gem_exec_whisper@basic-fds-priority.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-iclb8/igt@gem_exec_whisper@basic-fds-priority.html Known issues ------------ Here are the changes found in Patchwork_16790_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_isolation@vcs1-nonpriv: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#112080]) +8 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-iclb3/igt@gem_ctx_isolation@vcs1-nonpriv.html * igt@gem_exec_schedule@implicit-both-bsd2: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / [i915#677]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-iclb2/igt@gem_exec_schedule@implicit-both-bsd2.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-iclb3/igt@gem_exec_schedule@implicit-both-bsd2.html * igt@gem_exec_schedule@implicit-read-write-bsd: - shard-iclb: [PASS][9] -> [SKIP][10] ([i915#677]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-iclb3/igt@gem_exec_schedule@implicit-read-write-bsd.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-iclb4/igt@gem_exec_schedule@implicit-read-write-bsd.html * igt@gem_exec_schedule@pi-distinct-iova-bsd1: - shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109276]) +7 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-iclb1/igt@gem_exec_schedule@pi-distinct-iova-bsd1.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-iclb8/igt@gem_exec_schedule@pi-distinct-iova-bsd1.html * igt@gem_exec_schedule@preempt-bsd: - shard-iclb: [PASS][13] -> [SKIP][14] ([fdo#112146]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-iclb8/igt@gem_exec_schedule@preempt-bsd.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-iclb4/igt@gem_exec_schedule@preempt-bsd.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#716]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-skl1/igt@gen9_exec_parse@allowed-single.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-skl10/igt@gen9_exec_parse@allowed-single.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-apl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html * igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen: - shard-skl: [PASS][21] -> [FAIL][22] ([i915#54]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-skl3/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu: - shard-skl: [PASS][23] -> [FAIL][24] ([i915#49]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html * igt@kms_hdr@bpc-switch: - shard-skl: [PASS][25] -> [FAIL][26] ([i915#1188]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-skl7/igt@kms_hdr@bpc-switch.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-skl6/igt@kms_hdr@bpc-switch.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [PASS][27] -> [FAIL][28] ([fdo#108145]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [PASS][29] -> [FAIL][30] ([fdo#108145] / [i915#265]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-glk: [PASS][31] -> [FAIL][32] ([i915#899]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-glk8/igt@kms_plane_lowres@pipe-a-tiling-y.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-glk7/igt@kms_plane_lowres@pipe-a-tiling-y.html * igt@kms_psr@psr2_cursor_plane_onoff: - shard-iclb: [PASS][33] -> [SKIP][34] ([fdo#109441]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-iclb3/igt@kms_psr@psr2_cursor_plane_onoff.html * igt@kms_setmode@basic: - shard-apl: [PASS][35] -> [FAIL][36] ([i915#31]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-apl7/igt@kms_setmode@basic.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-apl8/igt@kms_setmode@basic.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-skl: [PASS][37] -> [INCOMPLETE][38] ([i915#69]) +1 similar issue [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-skl5/igt@kms_vblank@pipe-a-ts-continuation-suspend.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-skl10/igt@kms_vblank@pipe-a-ts-continuation-suspend.html #### Possible fixes #### * igt@gem_busy@extended-parallel-vcs1: - shard-iclb: [SKIP][39] ([fdo#112080]) -> [PASS][40] +4 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-iclb5/igt@gem_busy@extended-parallel-vcs1.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-iclb4/igt@gem_busy@extended-parallel-vcs1.html * igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd: - shard-skl: [INCOMPLETE][41] ([i915#1197] / [i915#1239]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-skl1/igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-skl10/igt@gem_ctx_persistence@legacy-engines-mixed-process@bsd.html * igt@gem_ctx_persistence@legacy-engines-mixed-process@render: - shard-skl: [FAIL][43] ([i915#679]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-skl1/igt@gem_ctx_persistence@legacy-engines-mixed-process@render.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-skl10/igt@gem_ctx_persistence@legacy-engines-mixed-process@render.html * igt@gem_exec_schedule@implicit-read-write-bsd1: - shard-iclb: [SKIP][45] ([fdo#109276] / [i915#677]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-iclb5/igt@gem_exec_schedule@implicit-read-write-bsd1.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-iclb2/igt@gem_exec_schedule@implicit-read-write-bsd1.html * igt@gem_exec_schedule@in-order-bsd: - shard-iclb: [SKIP][47] ([fdo#112146]) -> [PASS][48] +2 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-iclb1/igt@gem_exec_schedule@in-order-bsd.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-iclb8/igt@gem_exec_schedule@in-order-bsd.html * igt@gem_exec_schedule@independent-bsd2: - shard-iclb: [SKIP][49] ([fdo#109276]) -> [PASS][50] +14 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-iclb3/igt@gem_exec_schedule@independent-bsd2.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-iclb4/igt@gem_exec_schedule@independent-bsd2.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [DMESG-WARN][51] ([i915#180]) -> [PASS][52] +1 similar issue [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-apl8/igt@i915_suspend@fence-restore-tiled2untiled.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-kbl: [DMESG-WARN][53] ([i915#180]) -> [PASS][54] +1 similar issue [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html * igt@kms_psr@primary_mmap_gtt: - shard-tglb: [SKIP][55] ([i915#668]) -> [PASS][56] +4 similar issues [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-tglb5/igt@kms_psr@primary_mmap_gtt.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-tglb8/igt@kms_psr@primary_mmap_gtt.html * igt@kms_psr@psr2_cursor_mmap_cpu: - shard-iclb: [SKIP][57] ([fdo#109441]) -> [PASS][58] +2 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-iclb5/igt@kms_psr@psr2_cursor_mmap_cpu.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html * igt@kms_universal_plane@cursor-fb-leak-pipe-a: - shard-snb: [SKIP][59] ([fdo#109271]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-snb5/igt@kms_universal_plane@cursor-fb-leak-pipe-a.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-snb4/igt@kms_universal_plane@cursor-fb-leak-pipe-a.html * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend: - shard-skl: [INCOMPLETE][61] ([i915#69]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-skl8/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-skl2/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html #### Warnings #### * igt@i915_pm_dc@dc6-psr: - shard-snb: [SKIP][63] ([fdo#109271]) -> [INCOMPLETE][64] ([i915#82]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8050/shard-snb2/igt@i915_pm_dc@dc6-psr.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/shard-snb2/igt@i915_pm_dc@dc6-psr.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080 [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1197]: https://gitlab.freedesktop.org/drm/intel/issues/1197 [i915#1239]: https://gitlab.freedesktop.org/drm/intel/issues/1239 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668 [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677 [i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82 [i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899 Participating hosts (9 -> 10) ------------------------------ Additional (1): pig-skl-6260u Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_8050 -> Patchwork_16790 CI-20190529: 20190529 CI_DRM_8050: 422d76f5669ce8b7cd0c579f60628877159cbe7c @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5484: 91b36b61e76901a2bd09fe93ac7bf7b8a60f258c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_16790: 2495771ecf20343ab2818cd325a319fb42577522 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16790/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-03-04 18:31 UTC | newest] Thread overview: 11+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-03-03 0:08 [PATCH v3] drm/dp: Add function to parse EDID descriptors for adaptive sync limits Manasi Navare 2020-03-03 0:08 ` [Intel-gfx] " Manasi Navare 2020-03-03 1:53 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/dp: Add function to parse EDID descriptors for adaptive sync limits (rev2) Patchwork 2020-03-03 2:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2020-03-03 13:42 ` [PATCH v3] drm/dp: Add function to parse EDID descriptors for adaptive sync limits Ville Syrjälä 2020-03-03 13:42 ` [Intel-gfx] " Ville Syrjälä 2020-03-04 17:36 ` Manasi Navare 2020-03-04 17:36 ` [Intel-gfx] " Manasi Navare 2020-03-04 18:31 ` Ville Syrjälä 2020-03-04 18:31 ` [Intel-gfx] " Ville Syrjälä 2020-03-03 16:17 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/dp: Add function to parse EDID descriptors for adaptive sync limits (rev2) Patchwork
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