From: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
To: Nadeem Athani <nadeem@cadence.com>
Cc: <tjoseph@cadence.com>, <lorenzo.pieralisi@arm.com>,
<robh@kernel.org>, <bhelgaas@google.com>, <kishon@ti.com>,
<linux-omap@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
mparab@cadence.com, pthombar@cadence.com, sjakhade@cadence.com
Subject: Re: [PATCH v6 2/2] PCI: cadence: Retrain Link to work around Gen2 training defect.
Date: Tue, 29 Dec 2020 22:31:46 +0100 [thread overview]
Message-ID: <20201229223146.3081aa50@windsurf> (raw)
In-Reply-To: <20201228140510.14641-3-nadeem@cadence.com>
On Mon, 28 Dec 2020 15:05:10 +0100
Nadeem Athani <nadeem@cadence.com> wrote:
> +static void cdns_pcie_retrain(struct cdns_pcie *pcie)
Shouldn't this propagate a return value ?
> +{
> + u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET;
> + u16 lnk_stat, lnk_ctl;
> +
> + /*
> + * Set retrain bit if current speed is 2.5 GB/s,
> + * but the PCIe root port support is > 2.5 GB/s.
> + */
> +
> + lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off +
> + PCI_EXP_LNKCAP));
> + if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
> + return;
> +
> + lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA);
> + if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
> + lnk_ctl = cdns_pcie_rp_readw(pcie,
> + pcie_cap_off + PCI_EXP_LNKCTL);
> + lnk_ctl |= PCI_EXP_LNKCTL_RL;
> + cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL,
> + lnk_ctl);
> +
> + if (cdns_pcie_host_wait_for_link(pcie))
> + return;
Here, shouldn't you return the status of
cdns_pcie_host_wait_for_link(), to propagate whether the PCIe link
indeed came up after the retrain ?
Thomas
--
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
WARNING: multiple messages have this Message-ID (diff)
From: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
To: Nadeem Athani <nadeem@cadence.com>
Cc: lorenzo.pieralisi@arm.com, mparab@cadence.com,
linux-pci@vger.kernel.org, pthombar@cadence.com,
linux-kernel@vger.kernel.org, kishon@ti.com, tjoseph@cadence.com,
sjakhade@cadence.com, bhelgaas@google.com,
linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v6 2/2] PCI: cadence: Retrain Link to work around Gen2 training defect.
Date: Tue, 29 Dec 2020 22:31:46 +0100 [thread overview]
Message-ID: <20201229223146.3081aa50@windsurf> (raw)
In-Reply-To: <20201228140510.14641-3-nadeem@cadence.com>
On Mon, 28 Dec 2020 15:05:10 +0100
Nadeem Athani <nadeem@cadence.com> wrote:
> +static void cdns_pcie_retrain(struct cdns_pcie *pcie)
Shouldn't this propagate a return value ?
> +{
> + u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET;
> + u16 lnk_stat, lnk_ctl;
> +
> + /*
> + * Set retrain bit if current speed is 2.5 GB/s,
> + * but the PCIe root port support is > 2.5 GB/s.
> + */
> +
> + lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off +
> + PCI_EXP_LNKCAP));
> + if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
> + return;
> +
> + lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA);
> + if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
> + lnk_ctl = cdns_pcie_rp_readw(pcie,
> + pcie_cap_off + PCI_EXP_LNKCTL);
> + lnk_ctl |= PCI_EXP_LNKCTL_RL;
> + cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL,
> + lnk_ctl);
> +
> + if (cdns_pcie_host_wait_for_link(pcie))
> + return;
Here, shouldn't you return the status of
cdns_pcie_host_wait_for_link(), to propagate whether the PCIe link
indeed came up after the retrain ?
Thomas
--
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-12-29 21:32 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-28 14:05 [PATCH v6 0/2] PCI: cadence: Retrain Link to work around Gen2 Nadeem Athani
2020-12-28 14:05 ` Nadeem Athani
2020-12-28 14:05 ` [PATCH v6 1/2] PCI: cadence: Retrain Link to work around Gen2 training defect Nadeem Athani
2020-12-28 14:05 ` Nadeem Athani
2020-12-29 21:22 ` Thomas Petazzoni
2020-12-29 21:22 ` Thomas Petazzoni
2020-12-28 14:05 ` [PATCH v6 2/2] " Nadeem Athani
2020-12-28 14:05 ` Nadeem Athani
2020-12-29 21:31 ` Thomas Petazzoni [this message]
2020-12-29 21:31 ` Thomas Petazzoni
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