* [PATCH v6 0/2] PCI: cadence: Retrain Link to work around Gen2 @ 2020-12-28 14:05 ` Nadeem Athani 0 siblings, 0 replies; 10+ messages in thread From: Nadeem Athani @ 2020-12-28 14:05 UTC (permalink / raw) To: tjoseph, lorenzo.pieralisi, robh, bhelgaas, kishon, linux-omap, linux-pci, linux-arm-kernel, linux-kernel Cc: nadeem, mparab, sjakhade, pthombar Cadence controller will not initiate autonomous speed change if strapped as Gen2. The Retrain Link bit is set as quirk to enable this speed change. Adding a quirk flag for defective IP. In future IP revisions this will not be applicable. Version history: Changes in v6: - Move the position of function cdns_pcie_host_wait_for_link to remove compilation error. No changes in code. Separate patch for this. Changes in v5: - Remove the compatible string based setting of quirk flag. - Removed additional Link Up Check - Removed quirk from pcie-cadence-plat.c and added in pci-j721e.c Changes in v4: - Added a quirk flag based on a new compatible string. - Change of api for link up: cdns_pcie_host_wait_for_link(). Changes in v3: - To set retrain link bit,checking device capability & link status. - 32bit read in place of 8bit. - Minor correction in patch comment. - Change in variable & macro name. Changes in v2: - 16bit read in place of 8bit. Nadeem Athani (2): PCI: cadence: Retrain Link to work around Gen2 training defect. PCI: cadence: Retrain Link to work around Gen2 training defect. drivers/pci/controller/cadence/pci-j721e.c | 3 + drivers/pci/controller/cadence/pcie-cadence-host.c | 65 ++++++++++++++++------ drivers/pci/controller/cadence/pcie-cadence.h | 11 +++- 3 files changed, 61 insertions(+), 18 deletions(-) -- 2.15.0 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v6 0/2] PCI: cadence: Retrain Link to work around Gen2 @ 2020-12-28 14:05 ` Nadeem Athani 0 siblings, 0 replies; 10+ messages in thread From: Nadeem Athani @ 2020-12-28 14:05 UTC (permalink / raw) To: tjoseph, lorenzo.pieralisi, robh, bhelgaas, kishon, linux-omap, linux-pci, linux-arm-kernel, linux-kernel Cc: mparab, nadeem, pthombar, sjakhade Cadence controller will not initiate autonomous speed change if strapped as Gen2. The Retrain Link bit is set as quirk to enable this speed change. Adding a quirk flag for defective IP. In future IP revisions this will not be applicable. Version history: Changes in v6: - Move the position of function cdns_pcie_host_wait_for_link to remove compilation error. No changes in code. Separate patch for this. Changes in v5: - Remove the compatible string based setting of quirk flag. - Removed additional Link Up Check - Removed quirk from pcie-cadence-plat.c and added in pci-j721e.c Changes in v4: - Added a quirk flag based on a new compatible string. - Change of api for link up: cdns_pcie_host_wait_for_link(). Changes in v3: - To set retrain link bit,checking device capability & link status. - 32bit read in place of 8bit. - Minor correction in patch comment. - Change in variable & macro name. Changes in v2: - 16bit read in place of 8bit. Nadeem Athani (2): PCI: cadence: Retrain Link to work around Gen2 training defect. PCI: cadence: Retrain Link to work around Gen2 training defect. drivers/pci/controller/cadence/pci-j721e.c | 3 + drivers/pci/controller/cadence/pcie-cadence-host.c | 65 ++++++++++++++++------ drivers/pci/controller/cadence/pcie-cadence.h | 11 +++- 3 files changed, 61 insertions(+), 18 deletions(-) -- 2.15.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v6 1/2] PCI: cadence: Retrain Link to work around Gen2 training defect. 2020-12-28 14:05 ` Nadeem Athani @ 2020-12-28 14:05 ` Nadeem Athani -1 siblings, 0 replies; 10+ messages in thread From: Nadeem Athani @ 2020-12-28 14:05 UTC (permalink / raw) To: tjoseph, lorenzo.pieralisi, robh, bhelgaas, kishon, linux-omap, linux-pci, linux-arm-kernel, linux-kernel Cc: nadeem, mparab, sjakhade, pthombar Moving the function above to remove compilation error. No changes in function. Signed-off-by: Nadeem Athani <nadeem@cadence.com> --- drivers/pci/controller/cadence/pcie-cadence-host.c | 33 +++++++++++----------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 811c1cb2e8de..9f7aa718c8d4 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -77,6 +77,22 @@ static struct pci_ops cdns_pcie_host_ops = { .write = pci_generic_config_write, }; +static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) +{ + struct device *dev = pcie->dev; + int retries; + + /* Check if the link is up or not */ + for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + if (cdns_pcie_link_up(pcie)) { + dev_info(dev, "Link up\n"); + return 0; + } + usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + } + + return -ETIMEDOUT; +} static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) { @@ -398,23 +414,6 @@ static int cdns_pcie_host_init(struct device *dev, return cdns_pcie_host_init_address_translation(rc); } -static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) -{ - struct device *dev = pcie->dev; - int retries; - - /* Check if the link is up or not */ - for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { - if (cdns_pcie_link_up(pcie)) { - dev_info(dev, "Link up\n"); - return 0; - } - usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); - } - - return -ETIMEDOUT; -} - int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) { struct device *dev = rc->pcie.dev; -- 2.15.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v6 1/2] PCI: cadence: Retrain Link to work around Gen2 training defect. @ 2020-12-28 14:05 ` Nadeem Athani 0 siblings, 0 replies; 10+ messages in thread From: Nadeem Athani @ 2020-12-28 14:05 UTC (permalink / raw) To: tjoseph, lorenzo.pieralisi, robh, bhelgaas, kishon, linux-omap, linux-pci, linux-arm-kernel, linux-kernel Cc: mparab, nadeem, pthombar, sjakhade Moving the function above to remove compilation error. No changes in function. Signed-off-by: Nadeem Athani <nadeem@cadence.com> --- drivers/pci/controller/cadence/pcie-cadence-host.c | 33 +++++++++++----------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 811c1cb2e8de..9f7aa718c8d4 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -77,6 +77,22 @@ static struct pci_ops cdns_pcie_host_ops = { .write = pci_generic_config_write, }; +static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) +{ + struct device *dev = pcie->dev; + int retries; + + /* Check if the link is up or not */ + for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + if (cdns_pcie_link_up(pcie)) { + dev_info(dev, "Link up\n"); + return 0; + } + usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + } + + return -ETIMEDOUT; +} static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) { @@ -398,23 +414,6 @@ static int cdns_pcie_host_init(struct device *dev, return cdns_pcie_host_init_address_translation(rc); } -static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) -{ - struct device *dev = pcie->dev; - int retries; - - /* Check if the link is up or not */ - for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { - if (cdns_pcie_link_up(pcie)) { - dev_info(dev, "Link up\n"); - return 0; - } - usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); - } - - return -ETIMEDOUT; -} - int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) { struct device *dev = rc->pcie.dev; -- 2.15.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v6 1/2] PCI: cadence: Retrain Link to work around Gen2 training defect. 2020-12-28 14:05 ` Nadeem Athani @ 2020-12-29 21:22 ` Thomas Petazzoni -1 siblings, 0 replies; 10+ messages in thread From: Thomas Petazzoni @ 2020-12-29 21:22 UTC (permalink / raw) To: Nadeem Athani Cc: tjoseph, lorenzo.pieralisi, robh, bhelgaas, kishon, linux-omap, linux-pci, linux-arm-kernel, linux-kernel, mparab, pthombar, sjakhade Hello, The commit title is incorrect, it doesn't match what the patch is doing. On Mon, 28 Dec 2020 15:05:09 +0100 Nadeem Athani <nadeem@cadence.com> wrote: > Moving the function above to remove compilation error. > No changes in function. Which compilation error? I guess there is no compilation error, except after your apply your PATCH 2/2. Is this correct ? If so, this should be explained in this commit log: "Move the function cdns_pcie_host_wait_for_link() further up in the file, as it's going to be used by upcoming additional code in the driver." Best regards, Thomas -- Thomas Petazzoni, CTO, Bootlin Embedded Linux and Kernel engineering https://bootlin.com ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v6 1/2] PCI: cadence: Retrain Link to work around Gen2 training defect. @ 2020-12-29 21:22 ` Thomas Petazzoni 0 siblings, 0 replies; 10+ messages in thread From: Thomas Petazzoni @ 2020-12-29 21:22 UTC (permalink / raw) To: Nadeem Athani Cc: lorenzo.pieralisi, mparab, linux-pci, pthombar, linux-kernel, kishon, tjoseph, sjakhade, bhelgaas, linux-omap, linux-arm-kernel Hello, The commit title is incorrect, it doesn't match what the patch is doing. On Mon, 28 Dec 2020 15:05:09 +0100 Nadeem Athani <nadeem@cadence.com> wrote: > Moving the function above to remove compilation error. > No changes in function. Which compilation error? I guess there is no compilation error, except after your apply your PATCH 2/2. Is this correct ? If so, this should be explained in this commit log: "Move the function cdns_pcie_host_wait_for_link() further up in the file, as it's going to be used by upcoming additional code in the driver." Best regards, Thomas -- Thomas Petazzoni, CTO, Bootlin Embedded Linux and Kernel engineering https://bootlin.com _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v6 2/2] PCI: cadence: Retrain Link to work around Gen2 training defect. 2020-12-28 14:05 ` Nadeem Athani @ 2020-12-28 14:05 ` Nadeem Athani -1 siblings, 0 replies; 10+ messages in thread From: Nadeem Athani @ 2020-12-28 14:05 UTC (permalink / raw) To: tjoseph, lorenzo.pieralisi, robh, bhelgaas, kishon, linux-omap, linux-pci, linux-arm-kernel, linux-kernel Cc: nadeem, mparab, sjakhade, pthombar Cadence controller will not initiate autonomous speed change if strapped as Gen2. The Retrain Link bit is set as quirk to enable this speed change. Signed-off-by: Nadeem Athani <nadeem@cadence.com> --- drivers/pci/controller/cadence/pci-j721e.c | 3 ++ drivers/pci/controller/cadence/pcie-cadence-host.c | 32 ++++++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 11 +++++++- 3 files changed, 45 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index dac1ac8a7615..23a30be207a5 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -64,6 +64,7 @@ enum j721e_pcie_mode { struct j721e_pcie_data { enum j721e_pcie_mode mode; + bool quirk_retrain_flag; }; static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) @@ -280,6 +281,7 @@ static struct pci_ops cdns_ti_pcie_host_ops = { static const struct j721e_pcie_data j721e_pcie_rc_data = { .mode = PCI_MODE_RC, + .quirk_retrain_flag = true, }; static const struct j721e_pcie_data j721e_pcie_ep_data = { @@ -388,6 +390,7 @@ static int j721e_pcie_probe(struct platform_device *pdev) bridge->ops = &cdns_ti_pcie_host_ops; rc = pci_host_bridge_priv(bridge); + rc->quirk_retrain_flag = data->quirk_retrain_flag; cdns_pcie = &rc->pcie; cdns_pcie->dev = dev; diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 9f7aa718c8d4..9d730c10083b 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -94,6 +94,34 @@ static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) return -ETIMEDOUT; } +static void cdns_pcie_retrain(struct cdns_pcie *pcie) +{ + u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; + u16 lnk_stat, lnk_ctl; + + /* + * Set retrain bit if current speed is 2.5 GB/s, + * but the PCIe root port support is > 2.5 GB/s. + */ + + lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + + PCI_EXP_LNKCAP)); + if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) + return; + + lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); + if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) { + lnk_ctl = cdns_pcie_rp_readw(pcie, + pcie_cap_off + PCI_EXP_LNKCTL); + lnk_ctl |= PCI_EXP_LNKCTL_RL; + cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, + lnk_ctl); + + if (cdns_pcie_host_wait_for_link(pcie)) + return; + } +} + static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) { struct cdns_pcie *pcie = &rc->pcie; @@ -459,6 +487,10 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) ret = cdns_pcie_host_wait_for_link(pcie); if (ret) dev_dbg(dev, "PCIe link never came up\n"); + else { + if (rc->quirk_retrain_flag) + cdns_pcie_retrain(pcie); + } for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) rc->avail_ib_bar[bar] = true; diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 30eba6cafe2c..0f29128a5d0a 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -119,7 +119,7 @@ * Root Port Registers (PCI configuration space for the root port function) */ #define CDNS_PCIE_RP_BASE 0x00200000 - +#define CDNS_PCIE_RP_CAP_OFFSET 0xc0 /* * Address Translation Registers @@ -291,6 +291,7 @@ struct cdns_pcie { * @device_id: PCI device ID * @avail_ib_bar: Satus of RP_BAR0, RP_BAR1 and RP_NO_BAR if it's free or * available + * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2 */ struct cdns_pcie_rc { struct cdns_pcie pcie; @@ -299,6 +300,7 @@ struct cdns_pcie_rc { u32 vendor_id; u32 device_id; bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; + bool quirk_retrain_flag; }; /** @@ -414,6 +416,13 @@ static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, cdns_pcie_write_sz(addr, 0x2, value); } +static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) +{ + void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; + + return cdns_pcie_read_sz(addr, 0x2); +} + /* Endpoint Function register access */ static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, u32 reg, u8 value) -- 2.15.0 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v6 2/2] PCI: cadence: Retrain Link to work around Gen2 training defect. @ 2020-12-28 14:05 ` Nadeem Athani 0 siblings, 0 replies; 10+ messages in thread From: Nadeem Athani @ 2020-12-28 14:05 UTC (permalink / raw) To: tjoseph, lorenzo.pieralisi, robh, bhelgaas, kishon, linux-omap, linux-pci, linux-arm-kernel, linux-kernel Cc: mparab, nadeem, pthombar, sjakhade Cadence controller will not initiate autonomous speed change if strapped as Gen2. The Retrain Link bit is set as quirk to enable this speed change. Signed-off-by: Nadeem Athani <nadeem@cadence.com> --- drivers/pci/controller/cadence/pci-j721e.c | 3 ++ drivers/pci/controller/cadence/pcie-cadence-host.c | 32 ++++++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 11 +++++++- 3 files changed, 45 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index dac1ac8a7615..23a30be207a5 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -64,6 +64,7 @@ enum j721e_pcie_mode { struct j721e_pcie_data { enum j721e_pcie_mode mode; + bool quirk_retrain_flag; }; static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) @@ -280,6 +281,7 @@ static struct pci_ops cdns_ti_pcie_host_ops = { static const struct j721e_pcie_data j721e_pcie_rc_data = { .mode = PCI_MODE_RC, + .quirk_retrain_flag = true, }; static const struct j721e_pcie_data j721e_pcie_ep_data = { @@ -388,6 +390,7 @@ static int j721e_pcie_probe(struct platform_device *pdev) bridge->ops = &cdns_ti_pcie_host_ops; rc = pci_host_bridge_priv(bridge); + rc->quirk_retrain_flag = data->quirk_retrain_flag; cdns_pcie = &rc->pcie; cdns_pcie->dev = dev; diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c index 9f7aa718c8d4..9d730c10083b 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -94,6 +94,34 @@ static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) return -ETIMEDOUT; } +static void cdns_pcie_retrain(struct cdns_pcie *pcie) +{ + u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; + u16 lnk_stat, lnk_ctl; + + /* + * Set retrain bit if current speed is 2.5 GB/s, + * but the PCIe root port support is > 2.5 GB/s. + */ + + lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + + PCI_EXP_LNKCAP)); + if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) + return; + + lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); + if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) { + lnk_ctl = cdns_pcie_rp_readw(pcie, + pcie_cap_off + PCI_EXP_LNKCTL); + lnk_ctl |= PCI_EXP_LNKCTL_RL; + cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, + lnk_ctl); + + if (cdns_pcie_host_wait_for_link(pcie)) + return; + } +} + static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) { struct cdns_pcie *pcie = &rc->pcie; @@ -459,6 +487,10 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) ret = cdns_pcie_host_wait_for_link(pcie); if (ret) dev_dbg(dev, "PCIe link never came up\n"); + else { + if (rc->quirk_retrain_flag) + cdns_pcie_retrain(pcie); + } for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) rc->avail_ib_bar[bar] = true; diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 30eba6cafe2c..0f29128a5d0a 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -119,7 +119,7 @@ * Root Port Registers (PCI configuration space for the root port function) */ #define CDNS_PCIE_RP_BASE 0x00200000 - +#define CDNS_PCIE_RP_CAP_OFFSET 0xc0 /* * Address Translation Registers @@ -291,6 +291,7 @@ struct cdns_pcie { * @device_id: PCI device ID * @avail_ib_bar: Satus of RP_BAR0, RP_BAR1 and RP_NO_BAR if it's free or * available + * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2 */ struct cdns_pcie_rc { struct cdns_pcie pcie; @@ -299,6 +300,7 @@ struct cdns_pcie_rc { u32 vendor_id; u32 device_id; bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; + bool quirk_retrain_flag; }; /** @@ -414,6 +416,13 @@ static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, cdns_pcie_write_sz(addr, 0x2, value); } +static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) +{ + void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; + + return cdns_pcie_read_sz(addr, 0x2); +} + /* Endpoint Function register access */ static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, u32 reg, u8 value) -- 2.15.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v6 2/2] PCI: cadence: Retrain Link to work around Gen2 training defect. 2020-12-28 14:05 ` Nadeem Athani @ 2020-12-29 21:31 ` Thomas Petazzoni -1 siblings, 0 replies; 10+ messages in thread From: Thomas Petazzoni @ 2020-12-29 21:31 UTC (permalink / raw) To: Nadeem Athani Cc: tjoseph, lorenzo.pieralisi, robh, bhelgaas, kishon, linux-omap, linux-pci, linux-arm-kernel, linux-kernel, mparab, pthombar, sjakhade On Mon, 28 Dec 2020 15:05:10 +0100 Nadeem Athani <nadeem@cadence.com> wrote: > +static void cdns_pcie_retrain(struct cdns_pcie *pcie) Shouldn't this propagate a return value ? > +{ > + u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; > + u16 lnk_stat, lnk_ctl; > + > + /* > + * Set retrain bit if current speed is 2.5 GB/s, > + * but the PCIe root port support is > 2.5 GB/s. > + */ > + > + lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + > + PCI_EXP_LNKCAP)); > + if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) > + return; > + > + lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); > + if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) { > + lnk_ctl = cdns_pcie_rp_readw(pcie, > + pcie_cap_off + PCI_EXP_LNKCTL); > + lnk_ctl |= PCI_EXP_LNKCTL_RL; > + cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, > + lnk_ctl); > + > + if (cdns_pcie_host_wait_for_link(pcie)) > + return; Here, shouldn't you return the status of cdns_pcie_host_wait_for_link(), to propagate whether the PCIe link indeed came up after the retrain ? Thomas -- Thomas Petazzoni, CTO, Bootlin Embedded Linux and Kernel engineering https://bootlin.com ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v6 2/2] PCI: cadence: Retrain Link to work around Gen2 training defect. @ 2020-12-29 21:31 ` Thomas Petazzoni 0 siblings, 0 replies; 10+ messages in thread From: Thomas Petazzoni @ 2020-12-29 21:31 UTC (permalink / raw) To: Nadeem Athani Cc: lorenzo.pieralisi, mparab, linux-pci, pthombar, linux-kernel, kishon, tjoseph, sjakhade, bhelgaas, linux-omap, linux-arm-kernel On Mon, 28 Dec 2020 15:05:10 +0100 Nadeem Athani <nadeem@cadence.com> wrote: > +static void cdns_pcie_retrain(struct cdns_pcie *pcie) Shouldn't this propagate a return value ? > +{ > + u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; > + u16 lnk_stat, lnk_ctl; > + > + /* > + * Set retrain bit if current speed is 2.5 GB/s, > + * but the PCIe root port support is > 2.5 GB/s. > + */ > + > + lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + > + PCI_EXP_LNKCAP)); > + if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) > + return; > + > + lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); > + if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) { > + lnk_ctl = cdns_pcie_rp_readw(pcie, > + pcie_cap_off + PCI_EXP_LNKCTL); > + lnk_ctl |= PCI_EXP_LNKCTL_RL; > + cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, > + lnk_ctl); > + > + if (cdns_pcie_host_wait_for_link(pcie)) > + return; Here, shouldn't you return the status of cdns_pcie_host_wait_for_link(), to propagate whether the PCIe link indeed came up after the retrain ? Thomas -- Thomas Petazzoni, CTO, Bootlin Embedded Linux and Kernel engineering https://bootlin.com _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-12-29 21:33 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-12-28 14:05 [PATCH v6 0/2] PCI: cadence: Retrain Link to work around Gen2 Nadeem Athani 2020-12-28 14:05 ` Nadeem Athani 2020-12-28 14:05 ` [PATCH v6 1/2] PCI: cadence: Retrain Link to work around Gen2 training defect Nadeem Athani 2020-12-28 14:05 ` Nadeem Athani 2020-12-29 21:22 ` Thomas Petazzoni 2020-12-29 21:22 ` Thomas Petazzoni 2020-12-28 14:05 ` [PATCH v6 2/2] " Nadeem Athani 2020-12-28 14:05 ` Nadeem Athani 2020-12-29 21:31 ` Thomas Petazzoni 2020-12-29 21:31 ` Thomas Petazzoni
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