* [PATCH v6 0/8] drm/mediatek: add support for mediatek SOC MT8192
@ 2021-02-02 8:12 ` Hsin-Yi Wang
0 siblings, 0 replies; 64+ messages in thread
From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw)
To: CK Hu, Philipp Zabel, Matthias Brugger
Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie,
linux-kernel, dri-devel, linux-mediatek, Daniel Vetter,
linux-arm-kernel
This series are based on kernel/git/chunkuang.hu/linux.git mediatek-drm-next
and following patch:
("soc: mediatek: add mtk mutex support for MT8183")
https://patchwork.kernel.org/project/linux-mediatek/patch/20210129092209.2584718-8-hsinyi@chromium.org/
This series also depends on component support in mmsys[1]:
- [v4,06/10] soc: mediatek: mmsys: add component OVL_2L2
- [v4,07/10] soc: mediatek: mmsys: add component POSTMASK
- [v4,08/10] soc: mediatek: mmsys: add component RDMA4
[1] https://patchwork.kernel.org/project/linux-mediatek/patch/1609815993-22744-7-git-send-email-yongqiang.niu@mediatek.com/
Change since v5:
- move postmask driver into mtk_drm_ddp_comp
- fix review comments
Change since v4:
- fix review comments
Change since v3:
- change several function to rebase to mediatek-drm-next
- drop pm runtime patches due to it's not related to mt8192 support
- fix review comments in v3
Changes since v2:
- fix review comment in v2
- add pm runtime for gamma and color
- move ddp path select patch to mmsys series
- remove some useless patch
Yongqiang Niu (8):
drm/mediatek: add component OVL_2L2
drm/mediatek: add component POSTMASK
drm/mediatek: add component RDMA4
drm/mediatek: separate ccorr module
drm/mediatek: Fix ccorr size config
drm/mediatek: add matrix_bits private data for ccorr
soc: mediatek: add mtk mutex support for MT8192
drm/mediatek: add support for mediatek SOC MT8192
drivers/gpu/drm/mediatek/Makefile | 3 +-
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 229 ++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 +
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 ++
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 187 ++++++----------
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 50 ++++-
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
drivers/soc/mediatek/mtk-mutex.c | 35 +++
10 files changed, 421 insertions(+), 120 deletions(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
--
2.30.0.365.g02bc693789-goog
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 64+ messages in thread* [PATCH v6 0/8] drm/mediatek: add support for mediatek SOC MT8192 @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel This series are based on kernel/git/chunkuang.hu/linux.git mediatek-drm-next and following patch: ("soc: mediatek: add mtk mutex support for MT8183") https://patchwork.kernel.org/project/linux-mediatek/patch/20210129092209.2584718-8-hsinyi@chromium.org/ This series also depends on component support in mmsys[1]: - [v4,06/10] soc: mediatek: mmsys: add component OVL_2L2 - [v4,07/10] soc: mediatek: mmsys: add component POSTMASK - [v4,08/10] soc: mediatek: mmsys: add component RDMA4 [1] https://patchwork.kernel.org/project/linux-mediatek/patch/1609815993-22744-7-git-send-email-yongqiang.niu@mediatek.com/ Change since v5: - move postmask driver into mtk_drm_ddp_comp - fix review comments Change since v4: - fix review comments Change since v3: - change several function to rebase to mediatek-drm-next - drop pm runtime patches due to it's not related to mt8192 support - fix review comments in v3 Changes since v2: - fix review comment in v2 - add pm runtime for gamma and color - move ddp path select patch to mmsys series - remove some useless patch Yongqiang Niu (8): drm/mediatek: add component OVL_2L2 drm/mediatek: add component POSTMASK drm/mediatek: add component RDMA4 drm/mediatek: separate ccorr module drm/mediatek: Fix ccorr size config drm/mediatek: add matrix_bits private data for ccorr soc: mediatek: add mtk mutex support for MT8192 drm/mediatek: add support for mediatek SOC MT8192 drivers/gpu/drm/mediatek/Makefile | 3 +- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 229 ++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 + drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 ++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 187 ++++++---------- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 50 ++++- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + drivers/soc/mediatek/mtk-mutex.c | 35 +++ 10 files changed, 421 insertions(+), 120 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c -- 2.30.0.365.g02bc693789-goog _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v6 0/8] drm/mediatek: add support for mediatek SOC MT8192 @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu This series are based on kernel/git/chunkuang.hu/linux.git mediatek-drm-next and following patch: ("soc: mediatek: add mtk mutex support for MT8183") https://patchwork.kernel.org/project/linux-mediatek/patch/20210129092209.2584718-8-hsinyi@chromium.org/ This series also depends on component support in mmsys[1]: - [v4,06/10] soc: mediatek: mmsys: add component OVL_2L2 - [v4,07/10] soc: mediatek: mmsys: add component POSTMASK - [v4,08/10] soc: mediatek: mmsys: add component RDMA4 [1] https://patchwork.kernel.org/project/linux-mediatek/patch/1609815993-22744-7-git-send-email-yongqiang.niu@mediatek.com/ Change since v5: - move postmask driver into mtk_drm_ddp_comp - fix review comments Change since v4: - fix review comments Change since v3: - change several function to rebase to mediatek-drm-next - drop pm runtime patches due to it's not related to mt8192 support - fix review comments in v3 Changes since v2: - fix review comment in v2 - add pm runtime for gamma and color - move ddp path select patch to mmsys series - remove some useless patch Yongqiang Niu (8): drm/mediatek: add component OVL_2L2 drm/mediatek: add component POSTMASK drm/mediatek: add component RDMA4 drm/mediatek: separate ccorr module drm/mediatek: Fix ccorr size config drm/mediatek: add matrix_bits private data for ccorr soc: mediatek: add mtk mutex support for MT8192 drm/mediatek: add support for mediatek SOC MT8192 drivers/gpu/drm/mediatek/Makefile | 3 +- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 229 ++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 + drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 ++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 187 ++++++---------- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 50 ++++- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + drivers/soc/mediatek/mtk-mutex.c | 35 +++ 10 files changed, 421 insertions(+), 120 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c -- 2.30.0.365.g02bc693789-goog ^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v6 0/8] drm/mediatek: add support for mediatek SOC MT8192 @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel This series are based on kernel/git/chunkuang.hu/linux.git mediatek-drm-next and following patch: ("soc: mediatek: add mtk mutex support for MT8183") https://patchwork.kernel.org/project/linux-mediatek/patch/20210129092209.2584718-8-hsinyi@chromium.org/ This series also depends on component support in mmsys[1]: - [v4,06/10] soc: mediatek: mmsys: add component OVL_2L2 - [v4,07/10] soc: mediatek: mmsys: add component POSTMASK - [v4,08/10] soc: mediatek: mmsys: add component RDMA4 [1] https://patchwork.kernel.org/project/linux-mediatek/patch/1609815993-22744-7-git-send-email-yongqiang.niu@mediatek.com/ Change since v5: - move postmask driver into mtk_drm_ddp_comp - fix review comments Change since v4: - fix review comments Change since v3: - change several function to rebase to mediatek-drm-next - drop pm runtime patches due to it's not related to mt8192 support - fix review comments in v3 Changes since v2: - fix review comment in v2 - add pm runtime for gamma and color - move ddp path select patch to mmsys series - remove some useless patch Yongqiang Niu (8): drm/mediatek: add component OVL_2L2 drm/mediatek: add component POSTMASK drm/mediatek: add component RDMA4 drm/mediatek: separate ccorr module drm/mediatek: Fix ccorr size config drm/mediatek: add matrix_bits private data for ccorr soc: mediatek: add mtk mutex support for MT8192 drm/mediatek: add support for mediatek SOC MT8192 drivers/gpu/drm/mediatek/Makefile | 3 +- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 229 ++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 + drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 ++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 187 ++++++---------- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 50 ++++- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + drivers/soc/mediatek/mtk-mutex.c | 35 +++ 10 files changed, 421 insertions(+), 120 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c -- 2.30.0.365.g02bc693789-goog _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v6 1/8] drm/mediatek: add component OVL_2L2 2021-02-02 8:12 ` Hsin-Yi Wang (?) (?) @ 2021-02-02 8:12 ` Hsin-Yi Wang -1 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> This patch add component OVL_2L2 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 0444b429daf00..b6c4e73031ca6 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -477,6 +477,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, -- 2.30.0.365.g02bc693789-goog _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 1/8] drm/mediatek: add component OVL_2L2 @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> This patch add component OVL_2L2 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 0444b429daf00..b6c4e73031ca6 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -477,6 +477,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, -- 2.30.0.365.g02bc693789-goog _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 1/8] drm/mediatek: add component OVL_2L2 @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu From: Yongqiang Niu <yongqiang.niu@mediatek.com> This patch add component OVL_2L2 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 0444b429daf00..b6c4e73031ca6 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -477,6 +477,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, -- 2.30.0.365.g02bc693789-goog ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 1/8] drm/mediatek: add component OVL_2L2 @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> This patch add component OVL_2L2 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 0444b429daf00..b6c4e73031ca6 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -477,6 +477,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, -- 2.30.0.365.g02bc693789-goog _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 2/8] drm/mediatek: add component POSTMASK 2021-02-02 8:12 ` Hsin-Yi Wang (?) (?) @ 2021-02-02 8:12 ` Hsin-Yi Wang -1 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> This patch add component POSTMASK. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 102 ++++++++++++++------ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + 2 files changed, 73 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index b6c4e73031ca6..0a84ae53eb72a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -64,6 +64,12 @@ #define AAL_EN BIT(0) +#define DISP_POSTMASK_EN 0x0000 +#define POSTMASK_EN BIT(0) +#define DISP_POSTMASK_CFG 0x0020 +#define POSTMASK_RELAY_MODE BIT(0) +#define DISP_POSTMASK_SIZE 0x0030 + #define DISP_DITHERING BIT(2) #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28) #define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24) @@ -204,6 +210,32 @@ static void mtk_ufoe_start(struct device *dev) writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START); } +void mtk_postmask_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, + DISP_POSTMASK_SIZE); + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg, + priv->regs, DISP_POSTMASK_CFG); +} + +void mtk_postmask_start(struct device *dev) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN); +} + +void mtk_postmask_stop(struct device *dev) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN); +} + static void mtk_aal_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { .bgclr_in_off = mtk_ovl_bgclr_in_off, }; +static const struct mtk_ddp_comp_funcs ddp_postmask = { + .clk_enable = mtk_ddp_clk_enable, + .clk_disable = mtk_ddp_clk_disable, + .config = mtk_postmask_config, + .start = mtk_postmask_start, + .stop = mtk_postmask_stop, +}; + static const struct mtk_ddp_comp_funcs ddp_rdma = { .clk_enable = mtk_rdma_clk_enable, .clk_disable = mtk_rdma_clk_disable, @@ -448,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_MUTEX] = "mutex", [MTK_DISP_OD] = "od", [MTK_DISP_BLS] = "bls", + [MTK_DISP_POSTMASK] = "postmask", }; struct mtk_ddp_comp_match { @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match { }; static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { - [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, - [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, - [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, - [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, - [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, - [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, - [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, - [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, - [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, - [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, - [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, - [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, - [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, - [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, - [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, - [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, - [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, - [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, - [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, - [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, - [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, - [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, - [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, - [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, - [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, - [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, - [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, - [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, + [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, + [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, + [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, + [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, + [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, + [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, + [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, + [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, + [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, + [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, + [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, + [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, + [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, + [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, + [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, + [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask }, + [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, + [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, + [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, + [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, + [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, + [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, + [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, }; static bool mtk_drm_find_comp_in_ddp(struct device *dev, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index bb914d976cf5d..cd1dec6b4cdf2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DSI, MTK_DPI, + MTK_DISP_POSTMASK, MTK_DISP_PWM, MTK_DISP_MUTEX, MTK_DISP_OD, -- 2.30.0.365.g02bc693789-goog _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 2/8] drm/mediatek: add component POSTMASK @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> This patch add component POSTMASK. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 102 ++++++++++++++------ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + 2 files changed, 73 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index b6c4e73031ca6..0a84ae53eb72a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -64,6 +64,12 @@ #define AAL_EN BIT(0) +#define DISP_POSTMASK_EN 0x0000 +#define POSTMASK_EN BIT(0) +#define DISP_POSTMASK_CFG 0x0020 +#define POSTMASK_RELAY_MODE BIT(0) +#define DISP_POSTMASK_SIZE 0x0030 + #define DISP_DITHERING BIT(2) #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28) #define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24) @@ -204,6 +210,32 @@ static void mtk_ufoe_start(struct device *dev) writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START); } +void mtk_postmask_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, + DISP_POSTMASK_SIZE); + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg, + priv->regs, DISP_POSTMASK_CFG); +} + +void mtk_postmask_start(struct device *dev) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN); +} + +void mtk_postmask_stop(struct device *dev) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN); +} + static void mtk_aal_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { .bgclr_in_off = mtk_ovl_bgclr_in_off, }; +static const struct mtk_ddp_comp_funcs ddp_postmask = { + .clk_enable = mtk_ddp_clk_enable, + .clk_disable = mtk_ddp_clk_disable, + .config = mtk_postmask_config, + .start = mtk_postmask_start, + .stop = mtk_postmask_stop, +}; + static const struct mtk_ddp_comp_funcs ddp_rdma = { .clk_enable = mtk_rdma_clk_enable, .clk_disable = mtk_rdma_clk_disable, @@ -448,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_MUTEX] = "mutex", [MTK_DISP_OD] = "od", [MTK_DISP_BLS] = "bls", + [MTK_DISP_POSTMASK] = "postmask", }; struct mtk_ddp_comp_match { @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match { }; static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { - [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, - [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, - [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, - [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, - [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, - [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, - [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, - [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, - [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, - [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, - [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, - [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, - [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, - [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, - [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, - [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, - [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, - [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, - [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, - [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, - [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, - [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, - [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, - [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, - [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, - [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, - [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, - [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, + [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, + [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, + [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, + [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, + [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, + [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, + [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, + [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, + [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, + [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, + [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, + [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, + [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, + [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, + [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, + [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask }, + [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, + [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, + [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, + [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, + [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, + [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, + [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, }; static bool mtk_drm_find_comp_in_ddp(struct device *dev, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index bb914d976cf5d..cd1dec6b4cdf2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DSI, MTK_DPI, + MTK_DISP_POSTMASK, MTK_DISP_PWM, MTK_DISP_MUTEX, MTK_DISP_OD, -- 2.30.0.365.g02bc693789-goog _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 2/8] drm/mediatek: add component POSTMASK @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu From: Yongqiang Niu <yongqiang.niu@mediatek.com> This patch add component POSTMASK. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 102 ++++++++++++++------ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + 2 files changed, 73 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index b6c4e73031ca6..0a84ae53eb72a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -64,6 +64,12 @@ #define AAL_EN BIT(0) +#define DISP_POSTMASK_EN 0x0000 +#define POSTMASK_EN BIT(0) +#define DISP_POSTMASK_CFG 0x0020 +#define POSTMASK_RELAY_MODE BIT(0) +#define DISP_POSTMASK_SIZE 0x0030 + #define DISP_DITHERING BIT(2) #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28) #define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24) @@ -204,6 +210,32 @@ static void mtk_ufoe_start(struct device *dev) writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START); } +void mtk_postmask_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, + DISP_POSTMASK_SIZE); + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg, + priv->regs, DISP_POSTMASK_CFG); +} + +void mtk_postmask_start(struct device *dev) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN); +} + +void mtk_postmask_stop(struct device *dev) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN); +} + static void mtk_aal_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { .bgclr_in_off = mtk_ovl_bgclr_in_off, }; +static const struct mtk_ddp_comp_funcs ddp_postmask = { + .clk_enable = mtk_ddp_clk_enable, + .clk_disable = mtk_ddp_clk_disable, + .config = mtk_postmask_config, + .start = mtk_postmask_start, + .stop = mtk_postmask_stop, +}; + static const struct mtk_ddp_comp_funcs ddp_rdma = { .clk_enable = mtk_rdma_clk_enable, .clk_disable = mtk_rdma_clk_disable, @@ -448,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_MUTEX] = "mutex", [MTK_DISP_OD] = "od", [MTK_DISP_BLS] = "bls", + [MTK_DISP_POSTMASK] = "postmask", }; struct mtk_ddp_comp_match { @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match { }; static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { - [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, - [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, - [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, - [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, - [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, - [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, - [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, - [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, - [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, - [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, - [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, - [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, - [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, - [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, - [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, - [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, - [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, - [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, - [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, - [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, - [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, - [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, - [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, - [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, - [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, - [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, - [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, - [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, + [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, + [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, + [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, + [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, + [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, + [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, + [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, + [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, + [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, + [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, + [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, + [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, + [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, + [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, + [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, + [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask }, + [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, + [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, + [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, + [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, + [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, + [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, + [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, }; static bool mtk_drm_find_comp_in_ddp(struct device *dev, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index bb914d976cf5d..cd1dec6b4cdf2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DSI, MTK_DPI, + MTK_DISP_POSTMASK, MTK_DISP_PWM, MTK_DISP_MUTEX, MTK_DISP_OD, -- 2.30.0.365.g02bc693789-goog ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 2/8] drm/mediatek: add component POSTMASK @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> This patch add component POSTMASK. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 102 ++++++++++++++------ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + 2 files changed, 73 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index b6c4e73031ca6..0a84ae53eb72a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -64,6 +64,12 @@ #define AAL_EN BIT(0) +#define DISP_POSTMASK_EN 0x0000 +#define POSTMASK_EN BIT(0) +#define DISP_POSTMASK_CFG 0x0020 +#define POSTMASK_RELAY_MODE BIT(0) +#define DISP_POSTMASK_SIZE 0x0030 + #define DISP_DITHERING BIT(2) #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28) #define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24) @@ -204,6 +210,32 @@ static void mtk_ufoe_start(struct device *dev) writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START); } +void mtk_postmask_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, + DISP_POSTMASK_SIZE); + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg, + priv->regs, DISP_POSTMASK_CFG); +} + +void mtk_postmask_start(struct device *dev) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN); +} + +void mtk_postmask_stop(struct device *dev) +{ + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); + + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN); +} + static void mtk_aal_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { .bgclr_in_off = mtk_ovl_bgclr_in_off, }; +static const struct mtk_ddp_comp_funcs ddp_postmask = { + .clk_enable = mtk_ddp_clk_enable, + .clk_disable = mtk_ddp_clk_disable, + .config = mtk_postmask_config, + .start = mtk_postmask_start, + .stop = mtk_postmask_stop, +}; + static const struct mtk_ddp_comp_funcs ddp_rdma = { .clk_enable = mtk_rdma_clk_enable, .clk_disable = mtk_rdma_clk_disable, @@ -448,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_MUTEX] = "mutex", [MTK_DISP_OD] = "od", [MTK_DISP_BLS] = "bls", + [MTK_DISP_POSTMASK] = "postmask", }; struct mtk_ddp_comp_match { @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match { }; static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { - [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, - [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, - [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, - [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, - [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, - [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, - [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, - [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, - [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, - [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, - [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, - [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, - [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, - [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, - [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, - [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, - [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, - [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, - [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, - [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, - [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, - [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, - [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, - [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, - [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, - [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, - [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, - [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, + [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, + [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, + [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, + [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, + [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, + [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, + [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, + [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, + [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, + [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, + [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, + [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, + [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, + [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, + [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, + [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask }, + [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, + [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, + [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, + [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, + [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, + [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, + [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, }; static bool mtk_drm_find_comp_in_ddp(struct device *dev, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index bb914d976cf5d..cd1dec6b4cdf2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DSI, MTK_DPI, + MTK_DISP_POSTMASK, MTK_DISP_PWM, MTK_DISP_MUTEX, MTK_DISP_OD, -- 2.30.0.365.g02bc693789-goog _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 64+ messages in thread
* Re: [PATCH v6 2/8] drm/mediatek: add component POSTMASK 2021-02-02 8:12 ` Hsin-Yi Wang (?) (?) @ 2021-02-02 9:09 ` CK Hu -1 siblings, 0 replies; 64+ messages in thread From: CK Hu @ 2021-02-02 9:09 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie, linux-kernel, dri-devel, Yongqiang Niu, linux-mediatek, Daniel Vetter, Matthias Brugger, linux-arm-kernel Hi, Hsin-Yi: On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > This patch add component POSTMASK. Reviewed-by: CK Hu <ck.hu@mediatek.com> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 102 ++++++++++++++------ > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + > 2 files changed, 73 insertions(+), 30 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index b6c4e73031ca6..0a84ae53eb72a 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -64,6 +64,12 @@ > > #define AAL_EN BIT(0) > > +#define DISP_POSTMASK_EN 0x0000 > +#define POSTMASK_EN BIT(0) > +#define DISP_POSTMASK_CFG 0x0020 > +#define POSTMASK_RELAY_MODE BIT(0) > +#define DISP_POSTMASK_SIZE 0x0030 > + > #define DISP_DITHERING BIT(2) > #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28) > #define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24) > @@ -204,6 +210,32 @@ static void mtk_ufoe_start(struct device *dev) > writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START); > } > > +void mtk_postmask_config(struct device *dev, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, > + DISP_POSTMASK_SIZE); > + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg, > + priv->regs, DISP_POSTMASK_CFG); > +} > + > +void mtk_postmask_start(struct device *dev) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN); > +} > + > +void mtk_postmask_stop(struct device *dev) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN); > +} > + > static void mtk_aal_config(struct device *dev, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { > .bgclr_in_off = mtk_ovl_bgclr_in_off, > }; > > +static const struct mtk_ddp_comp_funcs ddp_postmask = { > + .clk_enable = mtk_ddp_clk_enable, > + .clk_disable = mtk_ddp_clk_disable, > + .config = mtk_postmask_config, > + .start = mtk_postmask_start, > + .stop = mtk_postmask_stop, > +}; > + > static const struct mtk_ddp_comp_funcs ddp_rdma = { > .clk_enable = mtk_rdma_clk_enable, > .clk_disable = mtk_rdma_clk_disable, > @@ -448,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { > [MTK_DISP_MUTEX] = "mutex", > [MTK_DISP_OD] = "od", > [MTK_DISP_BLS] = "bls", > + [MTK_DISP_POSTMASK] = "postmask", > }; > > struct mtk_ddp_comp_match { > @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match { > }; > > static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > - [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > - [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > - [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > - [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > - [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, > - [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, > - [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, > - [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, > - [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, > - [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, > - [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, > - [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > - [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > - [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > - [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, > - [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, > - [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > - [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > - [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > - [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, > - [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, > - [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, > - [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, > - [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, > - [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, > + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > + [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > + [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > + [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > + [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > + [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, > + [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, > + [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, > + [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, > + [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, > + [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, > + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, > + [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > + [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, > + [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, > + [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask }, > + [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > + [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, > + [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, > + [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, > + [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, > + [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, > + [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, > }; > > static bool mtk_drm_find_comp_in_ddp(struct device *dev, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index bb914d976cf5d..cd1dec6b4cdf2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { > MTK_DISP_UFOE, > MTK_DSI, > MTK_DPI, > + MTK_DISP_POSTMASK, > MTK_DISP_PWM, > MTK_DISP_MUTEX, > MTK_DISP_OD, _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 2/8] drm/mediatek: add component POSTMASK @ 2021-02-02 9:09 ` CK Hu 0 siblings, 0 replies; 64+ messages in thread From: CK Hu @ 2021-02-02 9:09 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, Yongqiang Niu, linux-mediatek, Matthias Brugger, linux-arm-kernel Hi, Hsin-Yi: On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > This patch add component POSTMASK. Reviewed-by: CK Hu <ck.hu@mediatek.com> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 102 ++++++++++++++------ > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + > 2 files changed, 73 insertions(+), 30 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index b6c4e73031ca6..0a84ae53eb72a 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -64,6 +64,12 @@ > > #define AAL_EN BIT(0) > > +#define DISP_POSTMASK_EN 0x0000 > +#define POSTMASK_EN BIT(0) > +#define DISP_POSTMASK_CFG 0x0020 > +#define POSTMASK_RELAY_MODE BIT(0) > +#define DISP_POSTMASK_SIZE 0x0030 > + > #define DISP_DITHERING BIT(2) > #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28) > #define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24) > @@ -204,6 +210,32 @@ static void mtk_ufoe_start(struct device *dev) > writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START); > } > > +void mtk_postmask_config(struct device *dev, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, > + DISP_POSTMASK_SIZE); > + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg, > + priv->regs, DISP_POSTMASK_CFG); > +} > + > +void mtk_postmask_start(struct device *dev) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN); > +} > + > +void mtk_postmask_stop(struct device *dev) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN); > +} > + > static void mtk_aal_config(struct device *dev, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { > .bgclr_in_off = mtk_ovl_bgclr_in_off, > }; > > +static const struct mtk_ddp_comp_funcs ddp_postmask = { > + .clk_enable = mtk_ddp_clk_enable, > + .clk_disable = mtk_ddp_clk_disable, > + .config = mtk_postmask_config, > + .start = mtk_postmask_start, > + .stop = mtk_postmask_stop, > +}; > + > static const struct mtk_ddp_comp_funcs ddp_rdma = { > .clk_enable = mtk_rdma_clk_enable, > .clk_disable = mtk_rdma_clk_disable, > @@ -448,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { > [MTK_DISP_MUTEX] = "mutex", > [MTK_DISP_OD] = "od", > [MTK_DISP_BLS] = "bls", > + [MTK_DISP_POSTMASK] = "postmask", > }; > > struct mtk_ddp_comp_match { > @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match { > }; > > static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > - [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > - [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > - [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > - [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > - [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, > - [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, > - [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, > - [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, > - [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, > - [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, > - [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, > - [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > - [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > - [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > - [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, > - [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, > - [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > - [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > - [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > - [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, > - [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, > - [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, > - [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, > - [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, > - [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, > + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > + [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > + [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > + [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > + [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > + [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, > + [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, > + [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, > + [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, > + [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, > + [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, > + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, > + [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > + [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, > + [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, > + [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask }, > + [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > + [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, > + [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, > + [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, > + [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, > + [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, > + [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, > }; > > static bool mtk_drm_find_comp_in_ddp(struct device *dev, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index bb914d976cf5d..cd1dec6b4cdf2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { > MTK_DISP_UFOE, > MTK_DSI, > MTK_DPI, > + MTK_DISP_POSTMASK, > MTK_DISP_PWM, > MTK_DISP_MUTEX, > MTK_DISP_OD, _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 2/8] drm/mediatek: add component POSTMASK @ 2021-02-02 9:09 ` CK Hu 0 siblings, 0 replies; 64+ messages in thread From: CK Hu @ 2021-02-02 9:09 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Philipp Zabel, Matthias Brugger, David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu Hi, Hsin-Yi: On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > This patch add component POSTMASK. Reviewed-by: CK Hu <ck.hu@mediatek.com> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 102 ++++++++++++++------ > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + > 2 files changed, 73 insertions(+), 30 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index b6c4e73031ca6..0a84ae53eb72a 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -64,6 +64,12 @@ > > #define AAL_EN BIT(0) > > +#define DISP_POSTMASK_EN 0x0000 > +#define POSTMASK_EN BIT(0) > +#define DISP_POSTMASK_CFG 0x0020 > +#define POSTMASK_RELAY_MODE BIT(0) > +#define DISP_POSTMASK_SIZE 0x0030 > + > #define DISP_DITHERING BIT(2) > #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28) > #define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24) > @@ -204,6 +210,32 @@ static void mtk_ufoe_start(struct device *dev) > writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START); > } > > +void mtk_postmask_config(struct device *dev, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, > + DISP_POSTMASK_SIZE); > + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg, > + priv->regs, DISP_POSTMASK_CFG); > +} > + > +void mtk_postmask_start(struct device *dev) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN); > +} > + > +void mtk_postmask_stop(struct device *dev) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN); > +} > + > static void mtk_aal_config(struct device *dev, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { > .bgclr_in_off = mtk_ovl_bgclr_in_off, > }; > > +static const struct mtk_ddp_comp_funcs ddp_postmask = { > + .clk_enable = mtk_ddp_clk_enable, > + .clk_disable = mtk_ddp_clk_disable, > + .config = mtk_postmask_config, > + .start = mtk_postmask_start, > + .stop = mtk_postmask_stop, > +}; > + > static const struct mtk_ddp_comp_funcs ddp_rdma = { > .clk_enable = mtk_rdma_clk_enable, > .clk_disable = mtk_rdma_clk_disable, > @@ -448,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { > [MTK_DISP_MUTEX] = "mutex", > [MTK_DISP_OD] = "od", > [MTK_DISP_BLS] = "bls", > + [MTK_DISP_POSTMASK] = "postmask", > }; > > struct mtk_ddp_comp_match { > @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match { > }; > > static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > - [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > - [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > - [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > - [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > - [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, > - [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, > - [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, > - [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, > - [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, > - [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, > - [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, > - [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > - [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > - [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > - [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, > - [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, > - [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > - [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > - [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > - [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, > - [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, > - [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, > - [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, > - [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, > - [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, > + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > + [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > + [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > + [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > + [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > + [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, > + [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, > + [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, > + [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, > + [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, > + [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, > + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, > + [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > + [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, > + [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, > + [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask }, > + [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > + [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, > + [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, > + [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, > + [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, > + [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, > + [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, > }; > > static bool mtk_drm_find_comp_in_ddp(struct device *dev, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index bb914d976cf5d..cd1dec6b4cdf2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { > MTK_DISP_UFOE, > MTK_DSI, > MTK_DPI, > + MTK_DISP_POSTMASK, > MTK_DISP_PWM, > MTK_DISP_MUTEX, > MTK_DISP_OD, ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 2/8] drm/mediatek: add component POSTMASK @ 2021-02-02 9:09 ` CK Hu 0 siblings, 0 replies; 64+ messages in thread From: CK Hu @ 2021-02-02 9:09 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie, linux-kernel, dri-devel, Yongqiang Niu, linux-mediatek, Daniel Vetter, Matthias Brugger, linux-arm-kernel Hi, Hsin-Yi: On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > This patch add component POSTMASK. Reviewed-by: CK Hu <ck.hu@mediatek.com> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 102 ++++++++++++++------ > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + > 2 files changed, 73 insertions(+), 30 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index b6c4e73031ca6..0a84ae53eb72a 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -64,6 +64,12 @@ > > #define AAL_EN BIT(0) > > +#define DISP_POSTMASK_EN 0x0000 > +#define POSTMASK_EN BIT(0) > +#define DISP_POSTMASK_CFG 0x0020 > +#define POSTMASK_RELAY_MODE BIT(0) > +#define DISP_POSTMASK_SIZE 0x0030 > + > #define DISP_DITHERING BIT(2) > #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28) > #define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24) > @@ -204,6 +210,32 @@ static void mtk_ufoe_start(struct device *dev) > writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START); > } > > +void mtk_postmask_config(struct device *dev, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, > + DISP_POSTMASK_SIZE); > + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg, > + priv->regs, DISP_POSTMASK_CFG); > +} > + > +void mtk_postmask_start(struct device *dev) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN); > +} > + > +void mtk_postmask_stop(struct device *dev) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN); > +} > + > static void mtk_aal_config(struct device *dev, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { > .bgclr_in_off = mtk_ovl_bgclr_in_off, > }; > > +static const struct mtk_ddp_comp_funcs ddp_postmask = { > + .clk_enable = mtk_ddp_clk_enable, > + .clk_disable = mtk_ddp_clk_disable, > + .config = mtk_postmask_config, > + .start = mtk_postmask_start, > + .stop = mtk_postmask_stop, > +}; > + > static const struct mtk_ddp_comp_funcs ddp_rdma = { > .clk_enable = mtk_rdma_clk_enable, > .clk_disable = mtk_rdma_clk_disable, > @@ -448,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { > [MTK_DISP_MUTEX] = "mutex", > [MTK_DISP_OD] = "od", > [MTK_DISP_BLS] = "bls", > + [MTK_DISP_POSTMASK] = "postmask", > }; > > struct mtk_ddp_comp_match { > @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match { > }; > > static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > - [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > - [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > - [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > - [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > - [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, > - [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, > - [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, > - [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, > - [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, > - [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, > - [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, > - [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > - [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > - [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > - [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, > - [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, > - [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > - [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > - [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > - [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, > - [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, > - [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, > - [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, > - [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, > - [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, > + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > + [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > + [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > + [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > + [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > + [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, > + [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, > + [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, > + [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, > + [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, > + [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, > + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, > + [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > + [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, > + [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, > + [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask }, > + [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > + [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, > + [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, > + [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, > + [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, > + [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, > + [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, > }; > > static bool mtk_drm_find_comp_in_ddp(struct device *dev, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index bb914d976cf5d..cd1dec6b4cdf2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { > MTK_DISP_UFOE, > MTK_DSI, > MTK_DPI, > + MTK_DISP_POSTMASK, > MTK_DISP_PWM, > MTK_DISP_MUTEX, > MTK_DISP_OD, _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 2/8] drm/mediatek: add component POSTMASK 2021-02-02 8:12 ` Hsin-Yi Wang (?) (?) @ 2021-02-09 15:32 ` Guenter Roeck -1 siblings, 0 replies; 64+ messages in thread From: Guenter Roeck @ 2021-02-09 15:32 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie, linux-kernel, dri-devel, Matthias Brugger, linux-mediatek, Yongqiang Niu, CK Hu, Daniel Vetter, linux-arm-kernel On Tue, Feb 02, 2021 at 04:12:31PM +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > This patch add component POSTMASK. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > Reviewed-by: CK Hu <ck.hu@mediatek.com> > --- [ ... ] > > +void mtk_postmask_config(struct device *dev, unsigned int w, static > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, > + DISP_POSTMASK_SIZE); > + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg, > + priv->regs, DISP_POSTMASK_CFG); > +} > + > +void mtk_postmask_start(struct device *dev) static > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN); > +} > + > +void mtk_postmask_stop(struct device *dev) static > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN); > +} > + > static void mtk_aal_config(struct device *dev, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { > .bgclr_in_off = mtk_ovl_bgclr_in_off, > }; > > +static const struct mtk_ddp_comp_funcs ddp_postmask = { > + .clk_enable = mtk_ddp_clk_enable, > + .clk_disable = mtk_ddp_clk_disable, > + .config = mtk_postmask_config, > + .start = mtk_postmask_start, > + .stop = mtk_postmask_stop, > +}; > + > static const struct mtk_ddp_comp_funcs ddp_rdma = { > .clk_enable = mtk_rdma_clk_enable, > .clk_disable = mtk_rdma_clk_disable, > @@ -448,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { > [MTK_DISP_MUTEX] = "mutex", > [MTK_DISP_OD] = "od", > [MTK_DISP_BLS] = "bls", > + [MTK_DISP_POSTMASK] = "postmask", > }; > > struct mtk_ddp_comp_match { > @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match { > }; > > static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > - [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > - [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > - [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > - [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > - [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, > - [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, > - [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, > - [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, > - [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, > - [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, > - [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, > - [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > - [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > - [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > - [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, > - [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, > - [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > - [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > - [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > - [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, > - [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, > - [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, > - [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, > - [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, > - [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, > + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > + [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > + [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > + [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > + [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > + [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, > + [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, > + [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, > + [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, > + [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, > + [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, > + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, > + [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > + [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, > + [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, > + [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask }, > + [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > + [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, > + [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, > + [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, > + [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, > + [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, > + [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, > }; > > static bool mtk_drm_find_comp_in_ddp(struct device *dev, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index bb914d976cf5d..cd1dec6b4cdf2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { > MTK_DISP_UFOE, > MTK_DSI, > MTK_DPI, > + MTK_DISP_POSTMASK, > MTK_DISP_PWM, > MTK_DISP_MUTEX, > MTK_DISP_OD, _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 2/8] drm/mediatek: add component POSTMASK @ 2021-02-09 15:32 ` Guenter Roeck 0 siblings, 0 replies; 64+ messages in thread From: Guenter Roeck @ 2021-02-09 15:32 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, Matthias Brugger, linux-mediatek, Yongqiang Niu, linux-arm-kernel On Tue, Feb 02, 2021 at 04:12:31PM +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > This patch add component POSTMASK. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > Reviewed-by: CK Hu <ck.hu@mediatek.com> > --- [ ... ] > > +void mtk_postmask_config(struct device *dev, unsigned int w, static > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, > + DISP_POSTMASK_SIZE); > + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg, > + priv->regs, DISP_POSTMASK_CFG); > +} > + > +void mtk_postmask_start(struct device *dev) static > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN); > +} > + > +void mtk_postmask_stop(struct device *dev) static > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN); > +} > + > static void mtk_aal_config(struct device *dev, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { > .bgclr_in_off = mtk_ovl_bgclr_in_off, > }; > > +static const struct mtk_ddp_comp_funcs ddp_postmask = { > + .clk_enable = mtk_ddp_clk_enable, > + .clk_disable = mtk_ddp_clk_disable, > + .config = mtk_postmask_config, > + .start = mtk_postmask_start, > + .stop = mtk_postmask_stop, > +}; > + > static const struct mtk_ddp_comp_funcs ddp_rdma = { > .clk_enable = mtk_rdma_clk_enable, > .clk_disable = mtk_rdma_clk_disable, > @@ -448,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { > [MTK_DISP_MUTEX] = "mutex", > [MTK_DISP_OD] = "od", > [MTK_DISP_BLS] = "bls", > + [MTK_DISP_POSTMASK] = "postmask", > }; > > struct mtk_ddp_comp_match { > @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match { > }; > > static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > - [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > - [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > - [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > - [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > - [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, > - [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, > - [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, > - [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, > - [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, > - [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, > - [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, > - [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > - [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > - [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > - [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, > - [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, > - [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > - [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > - [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > - [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, > - [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, > - [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, > - [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, > - [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, > - [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, > + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > + [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > + [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > + [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > + [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > + [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, > + [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, > + [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, > + [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, > + [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, > + [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, > + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, > + [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > + [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, > + [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, > + [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask }, > + [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > + [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, > + [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, > + [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, > + [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, > + [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, > + [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, > }; > > static bool mtk_drm_find_comp_in_ddp(struct device *dev, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index bb914d976cf5d..cd1dec6b4cdf2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { > MTK_DISP_UFOE, > MTK_DSI, > MTK_DPI, > + MTK_DISP_POSTMASK, > MTK_DISP_PWM, > MTK_DISP_MUTEX, > MTK_DISP_OD, _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 2/8] drm/mediatek: add component POSTMASK @ 2021-02-09 15:32 ` Guenter Roeck 0 siblings, 0 replies; 64+ messages in thread From: Guenter Roeck @ 2021-02-09 15:32 UTC (permalink / raw) To: Hsin-Yi Wang Cc: CK Hu, Philipp Zabel, Matthias Brugger, Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel On Tue, Feb 02, 2021 at 04:12:31PM +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > This patch add component POSTMASK. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > Reviewed-by: CK Hu <ck.hu@mediatek.com> > --- [ ... ] > > +void mtk_postmask_config(struct device *dev, unsigned int w, static > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, > + DISP_POSTMASK_SIZE); > + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg, > + priv->regs, DISP_POSTMASK_CFG); > +} > + > +void mtk_postmask_start(struct device *dev) static > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN); > +} > + > +void mtk_postmask_stop(struct device *dev) static > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN); > +} > + > static void mtk_aal_config(struct device *dev, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { > .bgclr_in_off = mtk_ovl_bgclr_in_off, > }; > > +static const struct mtk_ddp_comp_funcs ddp_postmask = { > + .clk_enable = mtk_ddp_clk_enable, > + .clk_disable = mtk_ddp_clk_disable, > + .config = mtk_postmask_config, > + .start = mtk_postmask_start, > + .stop = mtk_postmask_stop, > +}; > + > static const struct mtk_ddp_comp_funcs ddp_rdma = { > .clk_enable = mtk_rdma_clk_enable, > .clk_disable = mtk_rdma_clk_disable, > @@ -448,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { > [MTK_DISP_MUTEX] = "mutex", > [MTK_DISP_OD] = "od", > [MTK_DISP_BLS] = "bls", > + [MTK_DISP_POSTMASK] = "postmask", > }; > > struct mtk_ddp_comp_match { > @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match { > }; > > static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > - [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > - [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > - [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > - [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > - [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, > - [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, > - [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, > - [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, > - [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, > - [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, > - [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, > - [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > - [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > - [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > - [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, > - [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, > - [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > - [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > - [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > - [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, > - [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, > - [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, > - [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, > - [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, > - [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, > + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > + [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > + [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > + [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > + [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > + [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, > + [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, > + [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, > + [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, > + [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, > + [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, > + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, > + [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > + [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, > + [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, > + [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask }, > + [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > + [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, > + [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, > + [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, > + [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, > + [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, > + [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, > }; > > static bool mtk_drm_find_comp_in_ddp(struct device *dev, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index bb914d976cf5d..cd1dec6b4cdf2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { > MTK_DISP_UFOE, > MTK_DSI, > MTK_DPI, > + MTK_DISP_POSTMASK, > MTK_DISP_PWM, > MTK_DISP_MUTEX, > MTK_DISP_OD, ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 2/8] drm/mediatek: add component POSTMASK @ 2021-02-09 15:32 ` Guenter Roeck 0 siblings, 0 replies; 64+ messages in thread From: Guenter Roeck @ 2021-02-09 15:32 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie, linux-kernel, dri-devel, Matthias Brugger, linux-mediatek, Yongqiang Niu, CK Hu, Daniel Vetter, linux-arm-kernel On Tue, Feb 02, 2021 at 04:12:31PM +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > This patch add component POSTMASK. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > Reviewed-by: CK Hu <ck.hu@mediatek.com> > --- [ ... ] > > +void mtk_postmask_config(struct device *dev, unsigned int w, static > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, > + DISP_POSTMASK_SIZE); > + mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg, > + priv->regs, DISP_POSTMASK_CFG); > +} > + > +void mtk_postmask_start(struct device *dev) static > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN); > +} > + > +void mtk_postmask_stop(struct device *dev) static > +{ > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > + > + writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN); > +} > + > static void mtk_aal_config(struct device *dev, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > @@ -413,6 +445,14 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = { > .bgclr_in_off = mtk_ovl_bgclr_in_off, > }; > > +static const struct mtk_ddp_comp_funcs ddp_postmask = { > + .clk_enable = mtk_ddp_clk_enable, > + .clk_disable = mtk_ddp_clk_disable, > + .config = mtk_postmask_config, > + .start = mtk_postmask_start, > + .stop = mtk_postmask_stop, > +}; > + > static const struct mtk_ddp_comp_funcs ddp_rdma = { > .clk_enable = mtk_rdma_clk_enable, > .clk_disable = mtk_rdma_clk_disable, > @@ -448,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { > [MTK_DISP_MUTEX] = "mutex", > [MTK_DISP_OD] = "od", > [MTK_DISP_BLS] = "bls", > + [MTK_DISP_POSTMASK] = "postmask", > }; > > struct mtk_ddp_comp_match { > @@ -457,36 +498,37 @@ struct mtk_ddp_comp_match { > }; > > static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { > - [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > - [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > - [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > - [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > - [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > - [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > - [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, > - [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, > - [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, > - [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, > - [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, > - [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, > - [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, > - [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > - [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > - [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > - [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, > - [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, > - [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, > - [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > - [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > - [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > - [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, > - [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, > - [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, > - [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, > - [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, > - [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, > + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, > + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, > + [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, > + [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr }, > + [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color }, > + [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color }, > + [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither }, > + [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi }, > + [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, > + [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, > + [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, > + [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, > + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi }, > + [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, > + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, > + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, > + [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl }, > + [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl }, > + [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl }, > + [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask }, > + [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > + [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, > + [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, > + [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, > + [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, > + [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, > + [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, > }; > > static bool mtk_drm_find_comp_in_ddp(struct device *dev, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index bb914d976cf5d..cd1dec6b4cdf2 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -30,6 +30,7 @@ enum mtk_ddp_comp_type { > MTK_DISP_UFOE, > MTK_DSI, > MTK_DPI, > + MTK_DISP_POSTMASK, > MTK_DISP_PWM, > MTK_DISP_MUTEX, > MTK_DISP_OD, _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v6 3/8] drm/mediatek: add component RDMA4 2021-02-02 8:12 ` Hsin-Yi Wang (?) (?) @ 2021-02-02 8:12 ` Hsin-Yi Wang -1 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> This patch add component RDMA4 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 0a84ae53eb72a..7f5614a6faab8 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -526,6 +526,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, + [DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, &ddp_rdma }, [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, -- 2.30.0.365.g02bc693789-goog _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 3/8] drm/mediatek: add component RDMA4 @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> This patch add component RDMA4 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 0a84ae53eb72a..7f5614a6faab8 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -526,6 +526,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, + [DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, &ddp_rdma }, [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, -- 2.30.0.365.g02bc693789-goog _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 3/8] drm/mediatek: add component RDMA4 @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu From: Yongqiang Niu <yongqiang.niu@mediatek.com> This patch add component RDMA4 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 0a84ae53eb72a..7f5614a6faab8 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -526,6 +526,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, + [DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, &ddp_rdma }, [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, -- 2.30.0.365.g02bc693789-goog ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 3/8] drm/mediatek: add component RDMA4 @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> This patch add component RDMA4 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 0a84ae53eb72a..7f5614a6faab8 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -526,6 +526,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma }, [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma }, [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma }, + [DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, &ddp_rdma }, [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe }, [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL }, [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL }, -- 2.30.0.365.g02bc693789-goog _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 4/8] drm/mediatek: separate ccorr module 2021-02-02 8:12 ` Hsin-Yi Wang (?) (?) @ 2021-02-02 8:12 ` Hsin-Yi Wang -1 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> ccorr ctm matrix bits will be different in mt8192 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> --- drivers/gpu/drm/mediatek/Makefile | 3 +- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 216 ++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 95 +-------- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 6 files changed, 236 insertions(+), 96 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index b64674b944860..dc54a7a690054 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 -mediatek-drm-y := mtk_disp_color.o \ +mediatek-drm-y := mtk_disp_ccorr.o \ + mtk_disp_color.o \ mtk_disp_gamma.o \ mtk_disp_ovl.o \ mtk_disp_rdma.o \ diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c new file mode 100644 index 0000000000000..6ee2431e6b843 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 MediaTek Inc. + */ + +#include <linux/clk.h> +#include <linux/component.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-cmdq.h> + +#include "mtk_disp_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h" + +#define DISP_CCORR_EN 0x0000 +#define CCORR_EN BIT(0) +#define DISP_CCORR_CFG 0x0020 +#define CCORR_RELAY_MODE BIT(0) +#define CCORR_ENGINE_EN BIT(1) +#define CCORR_GAMMA_OFF BIT(2) +#define CCORR_WGAMUT_SRC_CLIP BIT(3) +#define DISP_CCORR_SIZE 0x0030 +#define DISP_CCORR_COEF_0 0x0080 +#define DISP_CCORR_COEF_1 0x0084 +#define DISP_CCORR_COEF_2 0x0088 +#define DISP_CCORR_COEF_3 0x008C +#define DISP_CCORR_COEF_4 0x0090 + +struct mtk_disp_ccorr_data { + u32 reserved; +}; + +/** + * struct mtk_disp_ccorr - DISP_CCORR driver structure + * @ddp_comp - structure containing type enum and hardware resources + * @crtc - associated crtc to report irq events to + */ +struct mtk_disp_ccorr { + struct clk *clk; + void __iomem *regs; + struct cmdq_client_reg cmdq_reg; + const struct mtk_disp_ccorr_data *data; +}; + +int mtk_ccorr_clk_enable(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + return clk_prepare_enable(ccorr->clk); +} + +void mtk_ccorr_clk_disable(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + clk_disable_unprepare(ccorr->clk); +} + +void mtk_ccorr_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs, + DISP_CCORR_SIZE); + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, + DISP_CCORR_CFG); +} + +void mtk_ccorr_start(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + writel(CCORR_EN, ccorr->regs + DISP_CCORR_EN); +} + +void mtk_ccorr_stop(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); +} + +/* Converts a DRM S31.32 value to the HW S1.10 format. */ +static u16 mtk_ctm_s31_32_to_s1_10(u64 in) +{ + u16 r; + + /* Sign bit. */ + r = in & BIT_ULL(63) ? BIT(11) : 0; + + if ((in & GENMASK_ULL(62, 33)) > 0) { + /* identity value 0x100000000 -> 0x400, */ + /* if bigger this, set it to max 0x7ff. */ + r |= GENMASK(10, 0); + } else { + /* take the 11 most important bits. */ + r |= (in >> 22) & GENMASK(10, 0); + } + + return r; +} + +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + struct drm_property_blob *blob = state->ctm; + struct drm_color_ctm *ctm; + const u64 *input; + uint16_t coeffs[9] = { 0 }; + int i; + struct cmdq_pkt *cmdq_pkt = NULL; + + if (!blob) + return; + + ctm = (struct drm_color_ctm *)blob->data; + input = ctm->matrix; + + for (i = 0; i < ARRAY_SIZE(coeffs); i++) + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); + + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_1); + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_2); + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3); + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4); +} + +static int mtk_disp_ccorr_bind(struct device *dev, struct device *master, + void *data) +{ + return 0; +} + +static void mtk_disp_ccorr_unbind(struct device *dev, struct device *master, + void *data) +{ +} + +static const struct component_ops mtk_disp_ccorr_component_ops = { + .bind = mtk_disp_ccorr_bind, + .unbind = mtk_disp_ccorr_unbind, +}; + +static int mtk_disp_ccorr_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_disp_ccorr *priv; + struct resource *res; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(dev, "failed to get ccorr clk\n"); + return PTR_ERR(priv->clk); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->regs)) { + dev_err(dev, "failed to ioremap ccorr\n"); + return PTR_ERR(priv->regs); + } + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); + if (ret) + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); +#endif + + priv->data = of_device_get_match_data(dev); + platform_set_drvdata(pdev, priv); + + ret = component_add(dev, &mtk_disp_ccorr_component_ops); + if (ret) + dev_err(dev, "Failed to add component: %d\n", ret); + + return ret; +} + +static int mtk_disp_ccorr_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &mtk_disp_ccorr_component_ops); + + return 0; +} + +static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { + { .compatible = "mediatek,mt8183-disp-ccorr"}, + {}, +}; +MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); + +struct platform_driver mtk_disp_ccorr_driver = { + .probe = mtk_disp_ccorr_probe, + .remove = mtk_disp_ccorr_remove, + .driver = { + .name = "mediatek-disp-ccorr", + .owner = THIS_MODULE, + .of_match_table = mtk_disp_ccorr_driver_dt_match, + }, +}; diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index cdb0383f99061..cafd9df2d63bb 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -9,6 +9,15 @@ #include <linux/soc/mediatek/mtk-cmdq.h> #include "mtk_drm_plane.h" +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state); +int mtk_ccorr_clk_enable(struct device *dev); +void mtk_ccorr_clk_disable(struct device *dev); +void mtk_ccorr_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +void mtk_ccorr_start(struct device *dev); +void mtk_ccorr_stop(struct device *dev); + void mtk_color_bypass_shadow(struct device *dev); int mtk_color_clk_enable(struct device *dev); void mtk_color_clk_disable(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 7f5614a6faab8..445ea805d43f3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -35,20 +35,6 @@ #define DISP_AAL_EN 0x0000 #define DISP_AAL_SIZE 0x0030 -#define DISP_CCORR_EN 0x0000 -#define CCORR_EN BIT(0) -#define DISP_CCORR_CFG 0x0020 -#define CCORR_RELAY_MODE BIT(0) -#define CCORR_ENGINE_EN BIT(1) -#define CCORR_GAMMA_OFF BIT(2) -#define CCORR_WGAMUT_SRC_CLIP BIT(3) -#define DISP_CCORR_SIZE 0x0030 -#define DISP_CCORR_COEF_0 0x0080 -#define DISP_CCORR_COEF_1 0x0084 -#define DISP_CCORR_COEF_2 0x0088 -#define DISP_CCORR_COEF_3 0x008C -#define DISP_CCORR_COEF_4 0x0090 - #define DISP_DITHER_EN 0x0000 #define DITHER_EN BIT(0) #define DISP_DITHER_CFG 0x0020 @@ -266,82 +252,6 @@ static void mtk_aal_stop(struct device *dev) writel_relaxed(0x0, priv->regs + DISP_AAL_EN); } -static void mtk_ccorr_config(struct device *dev, unsigned int w, - unsigned int h, unsigned int vrefresh, - unsigned int bpc, struct cmdq_pkt *cmdq_pkt) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_CCORR_SIZE); - mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &priv->cmdq_reg, priv->regs, DISP_CCORR_CFG); -} - -static void mtk_ccorr_start(struct device *dev) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - writel(CCORR_EN, priv->regs + DISP_CCORR_EN); -} - -static void mtk_ccorr_stop(struct device *dev) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - writel_relaxed(0x0, priv->regs + DISP_CCORR_EN); -} - -/* Converts a DRM S31.32 value to the HW S1.10 format. */ -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) -{ - u16 r; - - /* Sign bit. */ - r = in & BIT_ULL(63) ? BIT(11) : 0; - - if ((in & GENMASK_ULL(62, 33)) > 0) { - /* identity value 0x100000000 -> 0x400, */ - /* if bigger this, set it to max 0x7ff. */ - r |= GENMASK(10, 0); - } else { - /* take the 11 most important bits. */ - r |= (in >> 22) & GENMASK(10, 0); - } - - return r; -} - -static void mtk_ccorr_ctm_set(struct device *dev, - struct drm_crtc_state *state) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - struct drm_property_blob *blob = state->ctm; - struct drm_color_ctm *ctm; - const u64 *input; - uint16_t coeffs[9] = { 0 }; - int i; - struct cmdq_pkt *cmdq_pkt = NULL; - - if (!blob) - return; - - ctm = (struct drm_color_ctm *)blob->data; - input = ctm->matrix; - - for (i = 0; i < ARRAY_SIZE(coeffs); i++) - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); - - mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_0); - mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_1); - mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_2); - mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_3); - mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_4); -} - static void mtk_dither_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -380,8 +290,8 @@ static const struct mtk_ddp_comp_funcs ddp_aal = { }; static const struct mtk_ddp_comp_funcs ddp_ccorr = { - .clk_enable = mtk_ddp_clk_enable, - .clk_disable = mtk_ddp_clk_disable, + .clk_enable = mtk_ccorr_clk_enable, + .clk_disable = mtk_ccorr_clk_disable, .config = mtk_ccorr_config, .start = mtk_ccorr_start, .stop = mtk_ccorr_stop, @@ -642,6 +552,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, } if (type == MTK_DISP_BLS || + type == MTK_DISP_CCORR || type == MTK_DISP_COLOR || type == MTK_DISP_GAMMA || type == MTK_DPI || diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 486e73e675ad5..b013d56d27773 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -531,11 +531,12 @@ static int mtk_drm_probe(struct platform_device *pdev) private->comp_node[comp_id] = of_node_get(node); /* - * Currently only the COLOR, GAMMA, OVL, RDMA, DSI, and DPI blocks have - * separate component platform drivers and initialize their own + * Currently only the CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI + * blocks have separate component platform drivers and initialize their own * DDP component structure. The others are initialized here. */ - if (comp_type == MTK_DISP_COLOR || + if (comp_type == MTK_DISP_CCORR || + comp_type == MTK_DISP_COLOR || comp_type == MTK_DISP_GAMMA || comp_type == MTK_DISP_OVL || comp_type == MTK_DISP_OVL_2L || @@ -634,6 +635,7 @@ static struct platform_driver mtk_drm_platform_driver = { }; static struct platform_driver * const mtk_drm_drivers[] = { + &mtk_disp_ccorr_driver, &mtk_disp_color_driver, &mtk_disp_gamma_driver, &mtk_disp_ovl_driver, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index 0e54e3d51014a..637f5669e8954 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -46,6 +46,7 @@ struct mtk_drm_private { struct drm_atomic_state *suspend_state; }; +extern struct platform_driver mtk_disp_ccorr_driver; extern struct platform_driver mtk_disp_color_driver; extern struct platform_driver mtk_disp_gamma_driver; extern struct platform_driver mtk_disp_ovl_driver; -- 2.30.0.365.g02bc693789-goog _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 4/8] drm/mediatek: separate ccorr module @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> ccorr ctm matrix bits will be different in mt8192 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> --- drivers/gpu/drm/mediatek/Makefile | 3 +- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 216 ++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 95 +-------- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 6 files changed, 236 insertions(+), 96 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index b64674b944860..dc54a7a690054 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 -mediatek-drm-y := mtk_disp_color.o \ +mediatek-drm-y := mtk_disp_ccorr.o \ + mtk_disp_color.o \ mtk_disp_gamma.o \ mtk_disp_ovl.o \ mtk_disp_rdma.o \ diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c new file mode 100644 index 0000000000000..6ee2431e6b843 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 MediaTek Inc. + */ + +#include <linux/clk.h> +#include <linux/component.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-cmdq.h> + +#include "mtk_disp_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h" + +#define DISP_CCORR_EN 0x0000 +#define CCORR_EN BIT(0) +#define DISP_CCORR_CFG 0x0020 +#define CCORR_RELAY_MODE BIT(0) +#define CCORR_ENGINE_EN BIT(1) +#define CCORR_GAMMA_OFF BIT(2) +#define CCORR_WGAMUT_SRC_CLIP BIT(3) +#define DISP_CCORR_SIZE 0x0030 +#define DISP_CCORR_COEF_0 0x0080 +#define DISP_CCORR_COEF_1 0x0084 +#define DISP_CCORR_COEF_2 0x0088 +#define DISP_CCORR_COEF_3 0x008C +#define DISP_CCORR_COEF_4 0x0090 + +struct mtk_disp_ccorr_data { + u32 reserved; +}; + +/** + * struct mtk_disp_ccorr - DISP_CCORR driver structure + * @ddp_comp - structure containing type enum and hardware resources + * @crtc - associated crtc to report irq events to + */ +struct mtk_disp_ccorr { + struct clk *clk; + void __iomem *regs; + struct cmdq_client_reg cmdq_reg; + const struct mtk_disp_ccorr_data *data; +}; + +int mtk_ccorr_clk_enable(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + return clk_prepare_enable(ccorr->clk); +} + +void mtk_ccorr_clk_disable(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + clk_disable_unprepare(ccorr->clk); +} + +void mtk_ccorr_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs, + DISP_CCORR_SIZE); + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, + DISP_CCORR_CFG); +} + +void mtk_ccorr_start(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + writel(CCORR_EN, ccorr->regs + DISP_CCORR_EN); +} + +void mtk_ccorr_stop(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); +} + +/* Converts a DRM S31.32 value to the HW S1.10 format. */ +static u16 mtk_ctm_s31_32_to_s1_10(u64 in) +{ + u16 r; + + /* Sign bit. */ + r = in & BIT_ULL(63) ? BIT(11) : 0; + + if ((in & GENMASK_ULL(62, 33)) > 0) { + /* identity value 0x100000000 -> 0x400, */ + /* if bigger this, set it to max 0x7ff. */ + r |= GENMASK(10, 0); + } else { + /* take the 11 most important bits. */ + r |= (in >> 22) & GENMASK(10, 0); + } + + return r; +} + +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + struct drm_property_blob *blob = state->ctm; + struct drm_color_ctm *ctm; + const u64 *input; + uint16_t coeffs[9] = { 0 }; + int i; + struct cmdq_pkt *cmdq_pkt = NULL; + + if (!blob) + return; + + ctm = (struct drm_color_ctm *)blob->data; + input = ctm->matrix; + + for (i = 0; i < ARRAY_SIZE(coeffs); i++) + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); + + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_1); + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_2); + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3); + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4); +} + +static int mtk_disp_ccorr_bind(struct device *dev, struct device *master, + void *data) +{ + return 0; +} + +static void mtk_disp_ccorr_unbind(struct device *dev, struct device *master, + void *data) +{ +} + +static const struct component_ops mtk_disp_ccorr_component_ops = { + .bind = mtk_disp_ccorr_bind, + .unbind = mtk_disp_ccorr_unbind, +}; + +static int mtk_disp_ccorr_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_disp_ccorr *priv; + struct resource *res; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(dev, "failed to get ccorr clk\n"); + return PTR_ERR(priv->clk); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->regs)) { + dev_err(dev, "failed to ioremap ccorr\n"); + return PTR_ERR(priv->regs); + } + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); + if (ret) + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); +#endif + + priv->data = of_device_get_match_data(dev); + platform_set_drvdata(pdev, priv); + + ret = component_add(dev, &mtk_disp_ccorr_component_ops); + if (ret) + dev_err(dev, "Failed to add component: %d\n", ret); + + return ret; +} + +static int mtk_disp_ccorr_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &mtk_disp_ccorr_component_ops); + + return 0; +} + +static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { + { .compatible = "mediatek,mt8183-disp-ccorr"}, + {}, +}; +MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); + +struct platform_driver mtk_disp_ccorr_driver = { + .probe = mtk_disp_ccorr_probe, + .remove = mtk_disp_ccorr_remove, + .driver = { + .name = "mediatek-disp-ccorr", + .owner = THIS_MODULE, + .of_match_table = mtk_disp_ccorr_driver_dt_match, + }, +}; diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index cdb0383f99061..cafd9df2d63bb 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -9,6 +9,15 @@ #include <linux/soc/mediatek/mtk-cmdq.h> #include "mtk_drm_plane.h" +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state); +int mtk_ccorr_clk_enable(struct device *dev); +void mtk_ccorr_clk_disable(struct device *dev); +void mtk_ccorr_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +void mtk_ccorr_start(struct device *dev); +void mtk_ccorr_stop(struct device *dev); + void mtk_color_bypass_shadow(struct device *dev); int mtk_color_clk_enable(struct device *dev); void mtk_color_clk_disable(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 7f5614a6faab8..445ea805d43f3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -35,20 +35,6 @@ #define DISP_AAL_EN 0x0000 #define DISP_AAL_SIZE 0x0030 -#define DISP_CCORR_EN 0x0000 -#define CCORR_EN BIT(0) -#define DISP_CCORR_CFG 0x0020 -#define CCORR_RELAY_MODE BIT(0) -#define CCORR_ENGINE_EN BIT(1) -#define CCORR_GAMMA_OFF BIT(2) -#define CCORR_WGAMUT_SRC_CLIP BIT(3) -#define DISP_CCORR_SIZE 0x0030 -#define DISP_CCORR_COEF_0 0x0080 -#define DISP_CCORR_COEF_1 0x0084 -#define DISP_CCORR_COEF_2 0x0088 -#define DISP_CCORR_COEF_3 0x008C -#define DISP_CCORR_COEF_4 0x0090 - #define DISP_DITHER_EN 0x0000 #define DITHER_EN BIT(0) #define DISP_DITHER_CFG 0x0020 @@ -266,82 +252,6 @@ static void mtk_aal_stop(struct device *dev) writel_relaxed(0x0, priv->regs + DISP_AAL_EN); } -static void mtk_ccorr_config(struct device *dev, unsigned int w, - unsigned int h, unsigned int vrefresh, - unsigned int bpc, struct cmdq_pkt *cmdq_pkt) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_CCORR_SIZE); - mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &priv->cmdq_reg, priv->regs, DISP_CCORR_CFG); -} - -static void mtk_ccorr_start(struct device *dev) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - writel(CCORR_EN, priv->regs + DISP_CCORR_EN); -} - -static void mtk_ccorr_stop(struct device *dev) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - writel_relaxed(0x0, priv->regs + DISP_CCORR_EN); -} - -/* Converts a DRM S31.32 value to the HW S1.10 format. */ -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) -{ - u16 r; - - /* Sign bit. */ - r = in & BIT_ULL(63) ? BIT(11) : 0; - - if ((in & GENMASK_ULL(62, 33)) > 0) { - /* identity value 0x100000000 -> 0x400, */ - /* if bigger this, set it to max 0x7ff. */ - r |= GENMASK(10, 0); - } else { - /* take the 11 most important bits. */ - r |= (in >> 22) & GENMASK(10, 0); - } - - return r; -} - -static void mtk_ccorr_ctm_set(struct device *dev, - struct drm_crtc_state *state) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - struct drm_property_blob *blob = state->ctm; - struct drm_color_ctm *ctm; - const u64 *input; - uint16_t coeffs[9] = { 0 }; - int i; - struct cmdq_pkt *cmdq_pkt = NULL; - - if (!blob) - return; - - ctm = (struct drm_color_ctm *)blob->data; - input = ctm->matrix; - - for (i = 0; i < ARRAY_SIZE(coeffs); i++) - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); - - mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_0); - mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_1); - mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_2); - mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_3); - mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_4); -} - static void mtk_dither_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -380,8 +290,8 @@ static const struct mtk_ddp_comp_funcs ddp_aal = { }; static const struct mtk_ddp_comp_funcs ddp_ccorr = { - .clk_enable = mtk_ddp_clk_enable, - .clk_disable = mtk_ddp_clk_disable, + .clk_enable = mtk_ccorr_clk_enable, + .clk_disable = mtk_ccorr_clk_disable, .config = mtk_ccorr_config, .start = mtk_ccorr_start, .stop = mtk_ccorr_stop, @@ -642,6 +552,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, } if (type == MTK_DISP_BLS || + type == MTK_DISP_CCORR || type == MTK_DISP_COLOR || type == MTK_DISP_GAMMA || type == MTK_DPI || diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 486e73e675ad5..b013d56d27773 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -531,11 +531,12 @@ static int mtk_drm_probe(struct platform_device *pdev) private->comp_node[comp_id] = of_node_get(node); /* - * Currently only the COLOR, GAMMA, OVL, RDMA, DSI, and DPI blocks have - * separate component platform drivers and initialize their own + * Currently only the CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI + * blocks have separate component platform drivers and initialize their own * DDP component structure. The others are initialized here. */ - if (comp_type == MTK_DISP_COLOR || + if (comp_type == MTK_DISP_CCORR || + comp_type == MTK_DISP_COLOR || comp_type == MTK_DISP_GAMMA || comp_type == MTK_DISP_OVL || comp_type == MTK_DISP_OVL_2L || @@ -634,6 +635,7 @@ static struct platform_driver mtk_drm_platform_driver = { }; static struct platform_driver * const mtk_drm_drivers[] = { + &mtk_disp_ccorr_driver, &mtk_disp_color_driver, &mtk_disp_gamma_driver, &mtk_disp_ovl_driver, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index 0e54e3d51014a..637f5669e8954 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -46,6 +46,7 @@ struct mtk_drm_private { struct drm_atomic_state *suspend_state; }; +extern struct platform_driver mtk_disp_ccorr_driver; extern struct platform_driver mtk_disp_color_driver; extern struct platform_driver mtk_disp_gamma_driver; extern struct platform_driver mtk_disp_ovl_driver; -- 2.30.0.365.g02bc693789-goog _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 4/8] drm/mediatek: separate ccorr module @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu From: Yongqiang Niu <yongqiang.niu@mediatek.com> ccorr ctm matrix bits will be different in mt8192 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> --- drivers/gpu/drm/mediatek/Makefile | 3 +- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 216 ++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 95 +-------- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 6 files changed, 236 insertions(+), 96 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index b64674b944860..dc54a7a690054 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 -mediatek-drm-y := mtk_disp_color.o \ +mediatek-drm-y := mtk_disp_ccorr.o \ + mtk_disp_color.o \ mtk_disp_gamma.o \ mtk_disp_ovl.o \ mtk_disp_rdma.o \ diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c new file mode 100644 index 0000000000000..6ee2431e6b843 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 MediaTek Inc. + */ + +#include <linux/clk.h> +#include <linux/component.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-cmdq.h> + +#include "mtk_disp_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h" + +#define DISP_CCORR_EN 0x0000 +#define CCORR_EN BIT(0) +#define DISP_CCORR_CFG 0x0020 +#define CCORR_RELAY_MODE BIT(0) +#define CCORR_ENGINE_EN BIT(1) +#define CCORR_GAMMA_OFF BIT(2) +#define CCORR_WGAMUT_SRC_CLIP BIT(3) +#define DISP_CCORR_SIZE 0x0030 +#define DISP_CCORR_COEF_0 0x0080 +#define DISP_CCORR_COEF_1 0x0084 +#define DISP_CCORR_COEF_2 0x0088 +#define DISP_CCORR_COEF_3 0x008C +#define DISP_CCORR_COEF_4 0x0090 + +struct mtk_disp_ccorr_data { + u32 reserved; +}; + +/** + * struct mtk_disp_ccorr - DISP_CCORR driver structure + * @ddp_comp - structure containing type enum and hardware resources + * @crtc - associated crtc to report irq events to + */ +struct mtk_disp_ccorr { + struct clk *clk; + void __iomem *regs; + struct cmdq_client_reg cmdq_reg; + const struct mtk_disp_ccorr_data *data; +}; + +int mtk_ccorr_clk_enable(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + return clk_prepare_enable(ccorr->clk); +} + +void mtk_ccorr_clk_disable(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + clk_disable_unprepare(ccorr->clk); +} + +void mtk_ccorr_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs, + DISP_CCORR_SIZE); + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, + DISP_CCORR_CFG); +} + +void mtk_ccorr_start(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + writel(CCORR_EN, ccorr->regs + DISP_CCORR_EN); +} + +void mtk_ccorr_stop(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); +} + +/* Converts a DRM S31.32 value to the HW S1.10 format. */ +static u16 mtk_ctm_s31_32_to_s1_10(u64 in) +{ + u16 r; + + /* Sign bit. */ + r = in & BIT_ULL(63) ? BIT(11) : 0; + + if ((in & GENMASK_ULL(62, 33)) > 0) { + /* identity value 0x100000000 -> 0x400, */ + /* if bigger this, set it to max 0x7ff. */ + r |= GENMASK(10, 0); + } else { + /* take the 11 most important bits. */ + r |= (in >> 22) & GENMASK(10, 0); + } + + return r; +} + +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + struct drm_property_blob *blob = state->ctm; + struct drm_color_ctm *ctm; + const u64 *input; + uint16_t coeffs[9] = { 0 }; + int i; + struct cmdq_pkt *cmdq_pkt = NULL; + + if (!blob) + return; + + ctm = (struct drm_color_ctm *)blob->data; + input = ctm->matrix; + + for (i = 0; i < ARRAY_SIZE(coeffs); i++) + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); + + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_1); + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_2); + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3); + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4); +} + +static int mtk_disp_ccorr_bind(struct device *dev, struct device *master, + void *data) +{ + return 0; +} + +static void mtk_disp_ccorr_unbind(struct device *dev, struct device *master, + void *data) +{ +} + +static const struct component_ops mtk_disp_ccorr_component_ops = { + .bind = mtk_disp_ccorr_bind, + .unbind = mtk_disp_ccorr_unbind, +}; + +static int mtk_disp_ccorr_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_disp_ccorr *priv; + struct resource *res; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(dev, "failed to get ccorr clk\n"); + return PTR_ERR(priv->clk); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->regs)) { + dev_err(dev, "failed to ioremap ccorr\n"); + return PTR_ERR(priv->regs); + } + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); + if (ret) + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); +#endif + + priv->data = of_device_get_match_data(dev); + platform_set_drvdata(pdev, priv); + + ret = component_add(dev, &mtk_disp_ccorr_component_ops); + if (ret) + dev_err(dev, "Failed to add component: %d\n", ret); + + return ret; +} + +static int mtk_disp_ccorr_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &mtk_disp_ccorr_component_ops); + + return 0; +} + +static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { + { .compatible = "mediatek,mt8183-disp-ccorr"}, + {}, +}; +MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); + +struct platform_driver mtk_disp_ccorr_driver = { + .probe = mtk_disp_ccorr_probe, + .remove = mtk_disp_ccorr_remove, + .driver = { + .name = "mediatek-disp-ccorr", + .owner = THIS_MODULE, + .of_match_table = mtk_disp_ccorr_driver_dt_match, + }, +}; diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index cdb0383f99061..cafd9df2d63bb 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -9,6 +9,15 @@ #include <linux/soc/mediatek/mtk-cmdq.h> #include "mtk_drm_plane.h" +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state); +int mtk_ccorr_clk_enable(struct device *dev); +void mtk_ccorr_clk_disable(struct device *dev); +void mtk_ccorr_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +void mtk_ccorr_start(struct device *dev); +void mtk_ccorr_stop(struct device *dev); + void mtk_color_bypass_shadow(struct device *dev); int mtk_color_clk_enable(struct device *dev); void mtk_color_clk_disable(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 7f5614a6faab8..445ea805d43f3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -35,20 +35,6 @@ #define DISP_AAL_EN 0x0000 #define DISP_AAL_SIZE 0x0030 -#define DISP_CCORR_EN 0x0000 -#define CCORR_EN BIT(0) -#define DISP_CCORR_CFG 0x0020 -#define CCORR_RELAY_MODE BIT(0) -#define CCORR_ENGINE_EN BIT(1) -#define CCORR_GAMMA_OFF BIT(2) -#define CCORR_WGAMUT_SRC_CLIP BIT(3) -#define DISP_CCORR_SIZE 0x0030 -#define DISP_CCORR_COEF_0 0x0080 -#define DISP_CCORR_COEF_1 0x0084 -#define DISP_CCORR_COEF_2 0x0088 -#define DISP_CCORR_COEF_3 0x008C -#define DISP_CCORR_COEF_4 0x0090 - #define DISP_DITHER_EN 0x0000 #define DITHER_EN BIT(0) #define DISP_DITHER_CFG 0x0020 @@ -266,82 +252,6 @@ static void mtk_aal_stop(struct device *dev) writel_relaxed(0x0, priv->regs + DISP_AAL_EN); } -static void mtk_ccorr_config(struct device *dev, unsigned int w, - unsigned int h, unsigned int vrefresh, - unsigned int bpc, struct cmdq_pkt *cmdq_pkt) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_CCORR_SIZE); - mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &priv->cmdq_reg, priv->regs, DISP_CCORR_CFG); -} - -static void mtk_ccorr_start(struct device *dev) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - writel(CCORR_EN, priv->regs + DISP_CCORR_EN); -} - -static void mtk_ccorr_stop(struct device *dev) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - writel_relaxed(0x0, priv->regs + DISP_CCORR_EN); -} - -/* Converts a DRM S31.32 value to the HW S1.10 format. */ -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) -{ - u16 r; - - /* Sign bit. */ - r = in & BIT_ULL(63) ? BIT(11) : 0; - - if ((in & GENMASK_ULL(62, 33)) > 0) { - /* identity value 0x100000000 -> 0x400, */ - /* if bigger this, set it to max 0x7ff. */ - r |= GENMASK(10, 0); - } else { - /* take the 11 most important bits. */ - r |= (in >> 22) & GENMASK(10, 0); - } - - return r; -} - -static void mtk_ccorr_ctm_set(struct device *dev, - struct drm_crtc_state *state) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - struct drm_property_blob *blob = state->ctm; - struct drm_color_ctm *ctm; - const u64 *input; - uint16_t coeffs[9] = { 0 }; - int i; - struct cmdq_pkt *cmdq_pkt = NULL; - - if (!blob) - return; - - ctm = (struct drm_color_ctm *)blob->data; - input = ctm->matrix; - - for (i = 0; i < ARRAY_SIZE(coeffs); i++) - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); - - mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_0); - mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_1); - mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_2); - mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_3); - mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_4); -} - static void mtk_dither_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -380,8 +290,8 @@ static const struct mtk_ddp_comp_funcs ddp_aal = { }; static const struct mtk_ddp_comp_funcs ddp_ccorr = { - .clk_enable = mtk_ddp_clk_enable, - .clk_disable = mtk_ddp_clk_disable, + .clk_enable = mtk_ccorr_clk_enable, + .clk_disable = mtk_ccorr_clk_disable, .config = mtk_ccorr_config, .start = mtk_ccorr_start, .stop = mtk_ccorr_stop, @@ -642,6 +552,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, } if (type == MTK_DISP_BLS || + type == MTK_DISP_CCORR || type == MTK_DISP_COLOR || type == MTK_DISP_GAMMA || type == MTK_DPI || diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 486e73e675ad5..b013d56d27773 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -531,11 +531,12 @@ static int mtk_drm_probe(struct platform_device *pdev) private->comp_node[comp_id] = of_node_get(node); /* - * Currently only the COLOR, GAMMA, OVL, RDMA, DSI, and DPI blocks have - * separate component platform drivers and initialize their own + * Currently only the CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI + * blocks have separate component platform drivers and initialize their own * DDP component structure. The others are initialized here. */ - if (comp_type == MTK_DISP_COLOR || + if (comp_type == MTK_DISP_CCORR || + comp_type == MTK_DISP_COLOR || comp_type == MTK_DISP_GAMMA || comp_type == MTK_DISP_OVL || comp_type == MTK_DISP_OVL_2L || @@ -634,6 +635,7 @@ static struct platform_driver mtk_drm_platform_driver = { }; static struct platform_driver * const mtk_drm_drivers[] = { + &mtk_disp_ccorr_driver, &mtk_disp_color_driver, &mtk_disp_gamma_driver, &mtk_disp_ovl_driver, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index 0e54e3d51014a..637f5669e8954 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -46,6 +46,7 @@ struct mtk_drm_private { struct drm_atomic_state *suspend_state; }; +extern struct platform_driver mtk_disp_ccorr_driver; extern struct platform_driver mtk_disp_color_driver; extern struct platform_driver mtk_disp_gamma_driver; extern struct platform_driver mtk_disp_ovl_driver; -- 2.30.0.365.g02bc693789-goog ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 4/8] drm/mediatek: separate ccorr module @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> ccorr ctm matrix bits will be different in mt8192 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> --- drivers/gpu/drm/mediatek/Makefile | 3 +- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 216 ++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 95 +-------- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 6 files changed, 236 insertions(+), 96 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index b64674b944860..dc54a7a690054 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 -mediatek-drm-y := mtk_disp_color.o \ +mediatek-drm-y := mtk_disp_ccorr.o \ + mtk_disp_color.o \ mtk_disp_gamma.o \ mtk_disp_ovl.o \ mtk_disp_rdma.o \ diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c new file mode 100644 index 0000000000000..6ee2431e6b843 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 MediaTek Inc. + */ + +#include <linux/clk.h> +#include <linux/component.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-cmdq.h> + +#include "mtk_disp_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h" + +#define DISP_CCORR_EN 0x0000 +#define CCORR_EN BIT(0) +#define DISP_CCORR_CFG 0x0020 +#define CCORR_RELAY_MODE BIT(0) +#define CCORR_ENGINE_EN BIT(1) +#define CCORR_GAMMA_OFF BIT(2) +#define CCORR_WGAMUT_SRC_CLIP BIT(3) +#define DISP_CCORR_SIZE 0x0030 +#define DISP_CCORR_COEF_0 0x0080 +#define DISP_CCORR_COEF_1 0x0084 +#define DISP_CCORR_COEF_2 0x0088 +#define DISP_CCORR_COEF_3 0x008C +#define DISP_CCORR_COEF_4 0x0090 + +struct mtk_disp_ccorr_data { + u32 reserved; +}; + +/** + * struct mtk_disp_ccorr - DISP_CCORR driver structure + * @ddp_comp - structure containing type enum and hardware resources + * @crtc - associated crtc to report irq events to + */ +struct mtk_disp_ccorr { + struct clk *clk; + void __iomem *regs; + struct cmdq_client_reg cmdq_reg; + const struct mtk_disp_ccorr_data *data; +}; + +int mtk_ccorr_clk_enable(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + return clk_prepare_enable(ccorr->clk); +} + +void mtk_ccorr_clk_disable(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + clk_disable_unprepare(ccorr->clk); +} + +void mtk_ccorr_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs, + DISP_CCORR_SIZE); + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, + DISP_CCORR_CFG); +} + +void mtk_ccorr_start(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + writel(CCORR_EN, ccorr->regs + DISP_CCORR_EN); +} + +void mtk_ccorr_stop(struct device *dev) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + + writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); +} + +/* Converts a DRM S31.32 value to the HW S1.10 format. */ +static u16 mtk_ctm_s31_32_to_s1_10(u64 in) +{ + u16 r; + + /* Sign bit. */ + r = in & BIT_ULL(63) ? BIT(11) : 0; + + if ((in & GENMASK_ULL(62, 33)) > 0) { + /* identity value 0x100000000 -> 0x400, */ + /* if bigger this, set it to max 0x7ff. */ + r |= GENMASK(10, 0); + } else { + /* take the 11 most important bits. */ + r |= (in >> 22) & GENMASK(10, 0); + } + + return r; +} + +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) +{ + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); + struct drm_property_blob *blob = state->ctm; + struct drm_color_ctm *ctm; + const u64 *input; + uint16_t coeffs[9] = { 0 }; + int i; + struct cmdq_pkt *cmdq_pkt = NULL; + + if (!blob) + return; + + ctm = (struct drm_color_ctm *)blob->data; + input = ctm->matrix; + + for (i = 0; i < ARRAY_SIZE(coeffs); i++) + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); + + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_1); + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_2); + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3); + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4); +} + +static int mtk_disp_ccorr_bind(struct device *dev, struct device *master, + void *data) +{ + return 0; +} + +static void mtk_disp_ccorr_unbind(struct device *dev, struct device *master, + void *data) +{ +} + +static const struct component_ops mtk_disp_ccorr_component_ops = { + .bind = mtk_disp_ccorr_bind, + .unbind = mtk_disp_ccorr_unbind, +}; + +static int mtk_disp_ccorr_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_disp_ccorr *priv; + struct resource *res; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(dev, "failed to get ccorr clk\n"); + return PTR_ERR(priv->clk); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->regs)) { + dev_err(dev, "failed to ioremap ccorr\n"); + return PTR_ERR(priv->regs); + } + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); + if (ret) + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); +#endif + + priv->data = of_device_get_match_data(dev); + platform_set_drvdata(pdev, priv); + + ret = component_add(dev, &mtk_disp_ccorr_component_ops); + if (ret) + dev_err(dev, "Failed to add component: %d\n", ret); + + return ret; +} + +static int mtk_disp_ccorr_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &mtk_disp_ccorr_component_ops); + + return 0; +} + +static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { + { .compatible = "mediatek,mt8183-disp-ccorr"}, + {}, +}; +MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); + +struct platform_driver mtk_disp_ccorr_driver = { + .probe = mtk_disp_ccorr_probe, + .remove = mtk_disp_ccorr_remove, + .driver = { + .name = "mediatek-disp-ccorr", + .owner = THIS_MODULE, + .of_match_table = mtk_disp_ccorr_driver_dt_match, + }, +}; diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index cdb0383f99061..cafd9df2d63bb 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -9,6 +9,15 @@ #include <linux/soc/mediatek/mtk-cmdq.h> #include "mtk_drm_plane.h" +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state); +int mtk_ccorr_clk_enable(struct device *dev); +void mtk_ccorr_clk_disable(struct device *dev); +void mtk_ccorr_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +void mtk_ccorr_start(struct device *dev); +void mtk_ccorr_stop(struct device *dev); + void mtk_color_bypass_shadow(struct device *dev); int mtk_color_clk_enable(struct device *dev); void mtk_color_clk_disable(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 7f5614a6faab8..445ea805d43f3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -35,20 +35,6 @@ #define DISP_AAL_EN 0x0000 #define DISP_AAL_SIZE 0x0030 -#define DISP_CCORR_EN 0x0000 -#define CCORR_EN BIT(0) -#define DISP_CCORR_CFG 0x0020 -#define CCORR_RELAY_MODE BIT(0) -#define CCORR_ENGINE_EN BIT(1) -#define CCORR_GAMMA_OFF BIT(2) -#define CCORR_WGAMUT_SRC_CLIP BIT(3) -#define DISP_CCORR_SIZE 0x0030 -#define DISP_CCORR_COEF_0 0x0080 -#define DISP_CCORR_COEF_1 0x0084 -#define DISP_CCORR_COEF_2 0x0088 -#define DISP_CCORR_COEF_3 0x008C -#define DISP_CCORR_COEF_4 0x0090 - #define DISP_DITHER_EN 0x0000 #define DITHER_EN BIT(0) #define DISP_DITHER_CFG 0x0020 @@ -266,82 +252,6 @@ static void mtk_aal_stop(struct device *dev) writel_relaxed(0x0, priv->regs + DISP_AAL_EN); } -static void mtk_ccorr_config(struct device *dev, unsigned int w, - unsigned int h, unsigned int vrefresh, - unsigned int bpc, struct cmdq_pkt *cmdq_pkt) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_CCORR_SIZE); - mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &priv->cmdq_reg, priv->regs, DISP_CCORR_CFG); -} - -static void mtk_ccorr_start(struct device *dev) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - writel(CCORR_EN, priv->regs + DISP_CCORR_EN); -} - -static void mtk_ccorr_stop(struct device *dev) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - - writel_relaxed(0x0, priv->regs + DISP_CCORR_EN); -} - -/* Converts a DRM S31.32 value to the HW S1.10 format. */ -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) -{ - u16 r; - - /* Sign bit. */ - r = in & BIT_ULL(63) ? BIT(11) : 0; - - if ((in & GENMASK_ULL(62, 33)) > 0) { - /* identity value 0x100000000 -> 0x400, */ - /* if bigger this, set it to max 0x7ff. */ - r |= GENMASK(10, 0); - } else { - /* take the 11 most important bits. */ - r |= (in >> 22) & GENMASK(10, 0); - } - - return r; -} - -static void mtk_ccorr_ctm_set(struct device *dev, - struct drm_crtc_state *state) -{ - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - struct drm_property_blob *blob = state->ctm; - struct drm_color_ctm *ctm; - const u64 *input; - uint16_t coeffs[9] = { 0 }; - int i; - struct cmdq_pkt *cmdq_pkt = NULL; - - if (!blob) - return; - - ctm = (struct drm_color_ctm *)blob->data; - input = ctm->matrix; - - for (i = 0; i < ARRAY_SIZE(coeffs); i++) - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); - - mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_0); - mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_1); - mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_2); - mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_3); - mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_4); -} - static void mtk_dither_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -380,8 +290,8 @@ static const struct mtk_ddp_comp_funcs ddp_aal = { }; static const struct mtk_ddp_comp_funcs ddp_ccorr = { - .clk_enable = mtk_ddp_clk_enable, - .clk_disable = mtk_ddp_clk_disable, + .clk_enable = mtk_ccorr_clk_enable, + .clk_disable = mtk_ccorr_clk_disable, .config = mtk_ccorr_config, .start = mtk_ccorr_start, .stop = mtk_ccorr_stop, @@ -642,6 +552,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, } if (type == MTK_DISP_BLS || + type == MTK_DISP_CCORR || type == MTK_DISP_COLOR || type == MTK_DISP_GAMMA || type == MTK_DPI || diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 486e73e675ad5..b013d56d27773 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -531,11 +531,12 @@ static int mtk_drm_probe(struct platform_device *pdev) private->comp_node[comp_id] = of_node_get(node); /* - * Currently only the COLOR, GAMMA, OVL, RDMA, DSI, and DPI blocks have - * separate component platform drivers and initialize their own + * Currently only the CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI + * blocks have separate component platform drivers and initialize their own * DDP component structure. The others are initialized here. */ - if (comp_type == MTK_DISP_COLOR || + if (comp_type == MTK_DISP_CCORR || + comp_type == MTK_DISP_COLOR || comp_type == MTK_DISP_GAMMA || comp_type == MTK_DISP_OVL || comp_type == MTK_DISP_OVL_2L || @@ -634,6 +635,7 @@ static struct platform_driver mtk_drm_platform_driver = { }; static struct platform_driver * const mtk_drm_drivers[] = { + &mtk_disp_ccorr_driver, &mtk_disp_color_driver, &mtk_disp_gamma_driver, &mtk_disp_ovl_driver, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index 0e54e3d51014a..637f5669e8954 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -46,6 +46,7 @@ struct mtk_drm_private { struct drm_atomic_state *suspend_state; }; +extern struct platform_driver mtk_disp_ccorr_driver; extern struct platform_driver mtk_disp_color_driver; extern struct platform_driver mtk_disp_gamma_driver; extern struct platform_driver mtk_disp_ovl_driver; -- 2.30.0.365.g02bc693789-goog _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 64+ messages in thread
* Re: [PATCH v6 4/8] drm/mediatek: separate ccorr module 2021-02-02 8:12 ` Hsin-Yi Wang (?) (?) @ 2021-02-03 16:13 ` Chun-Kuang Hu -1 siblings, 0 replies; 64+ messages in thread From: Chun-Kuang Hu @ 2021-02-03 16:13 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Mark Rutland, DTML, Philipp Zabel, David Airlie, linux-kernel, DRI Development, Matthias Brugger, moderated list:ARM/Mediatek SoC support, Yongqiang Niu, CK Hu, Daniel Vetter, Linux ARM Hi, Hsin-Yi: Hsin-Yi Wang <hsinyi@chromium.org> 於 2021年2月2日 週二 下午4:13寫道： > > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > ccorr ctm matrix bits will be different in mt8192 Applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, Chun-Kuang. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > Reviewed-by: CK Hu <ck.hu@mediatek.com> > --- > drivers/gpu/drm/mediatek/Makefile | 3 +- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 216 ++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 + > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 95 +-------- > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +- > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + > 6 files changed, 236 insertions(+), 96 deletions(-) > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > > diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile > index b64674b944860..dc54a7a690054 100644 > --- a/drivers/gpu/drm/mediatek/Makefile > +++ b/drivers/gpu/drm/mediatek/Makefile > @@ -1,6 +1,7 @@ > # SPDX-License-Identifier: GPL-2.0 > > -mediatek-drm-y := mtk_disp_color.o \ > +mediatek-drm-y := mtk_disp_ccorr.o \ > + mtk_disp_color.o \ > mtk_disp_gamma.o \ > mtk_disp_ovl.o \ > mtk_disp_rdma.o \ > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > new file mode 100644 > index 0000000000000..6ee2431e6b843 > --- /dev/null > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -0,0 +1,216 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2021 MediaTek Inc. > + */ > + > +#include <linux/clk.h> > +#include <linux/component.h> > +#include <linux/module.h> > +#include <linux/of_device.h> > +#include <linux/of_irq.h> > +#include <linux/platform_device.h> > +#include <linux/soc/mediatek/mtk-cmdq.h> > + > +#include "mtk_disp_drv.h" > +#include "mtk_drm_crtc.h" > +#include "mtk_drm_ddp_comp.h" > + > +#define DISP_CCORR_EN 0x0000 > +#define CCORR_EN BIT(0) > +#define DISP_CCORR_CFG 0x0020 > +#define CCORR_RELAY_MODE BIT(0) > +#define CCORR_ENGINE_EN BIT(1) > +#define CCORR_GAMMA_OFF BIT(2) > +#define CCORR_WGAMUT_SRC_CLIP BIT(3) > +#define DISP_CCORR_SIZE 0x0030 > +#define DISP_CCORR_COEF_0 0x0080 > +#define DISP_CCORR_COEF_1 0x0084 > +#define DISP_CCORR_COEF_2 0x0088 > +#define DISP_CCORR_COEF_3 0x008C > +#define DISP_CCORR_COEF_4 0x0090 > + > +struct mtk_disp_ccorr_data { > + u32 reserved; > +}; > + > +/** > + * struct mtk_disp_ccorr - DISP_CCORR driver structure > + * @ddp_comp - structure containing type enum and hardware resources > + * @crtc - associated crtc to report irq events to > + */ > +struct mtk_disp_ccorr { > + struct clk *clk; > + void __iomem *regs; > + struct cmdq_client_reg cmdq_reg; > + const struct mtk_disp_ccorr_data *data; > +}; > + > +int mtk_ccorr_clk_enable(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + return clk_prepare_enable(ccorr->clk); > +} > + > +void mtk_ccorr_clk_disable(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + clk_disable_unprepare(ccorr->clk); > +} > + > +void mtk_ccorr_config(struct device *dev, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs, > + DISP_CCORR_SIZE); > + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, > + DISP_CCORR_CFG); > +} > + > +void mtk_ccorr_start(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + writel(CCORR_EN, ccorr->regs + DISP_CCORR_EN); > +} > + > +void mtk_ccorr_stop(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); > +} > + > +/* Converts a DRM S31.32 value to the HW S1.10 format. */ > +static u16 mtk_ctm_s31_32_to_s1_10(u64 in) > +{ > + u16 r; > + > + /* Sign bit. */ > + r = in & BIT_ULL(63) ? BIT(11) : 0; > + > + if ((in & GENMASK_ULL(62, 33)) > 0) { > + /* identity value 0x100000000 -> 0x400, */ > + /* if bigger this, set it to max 0x7ff. */ > + r |= GENMASK(10, 0); > + } else { > + /* take the 11 most important bits. */ > + r |= (in >> 22) & GENMASK(10, 0); > + } > + > + return r; > +} > + > +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + struct drm_property_blob *blob = state->ctm; > + struct drm_color_ctm *ctm; > + const u64 *input; > + uint16_t coeffs[9] = { 0 }; > + int i; > + struct cmdq_pkt *cmdq_pkt = NULL; > + > + if (!blob) > + return; > + > + ctm = (struct drm_color_ctm *)blob->data; > + input = ctm->matrix; > + > + for (i = 0; i < ARRAY_SIZE(coeffs); i++) > + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > + > + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); > + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_1); > + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_2); > + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3); > + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4); > +} > + > +static int mtk_disp_ccorr_bind(struct device *dev, struct device *master, > + void *data) > +{ > + return 0; > +} > + > +static void mtk_disp_ccorr_unbind(struct device *dev, struct device *master, > + void *data) > +{ > +} > + > +static const struct component_ops mtk_disp_ccorr_component_ops = { > + .bind = mtk_disp_ccorr_bind, > + .unbind = mtk_disp_ccorr_unbind, > +}; > + > +static int mtk_disp_ccorr_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct mtk_disp_ccorr *priv; > + struct resource *res; > + int ret; > + > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + priv->clk = devm_clk_get(dev, NULL); > + if (IS_ERR(priv->clk)) { > + dev_err(dev, "failed to get ccorr clk\n"); > + return PTR_ERR(priv->clk); > + } > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + priv->regs = devm_ioremap_resource(dev, res); > + if (IS_ERR(priv->regs)) { > + dev_err(dev, "failed to ioremap ccorr\n"); > + return PTR_ERR(priv->regs); > + } > + > +#if IS_REACHABLE(CONFIG_MTK_CMDQ) > + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); > + if (ret) > + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); > +#endif > + > + priv->data = of_device_get_match_data(dev); > + platform_set_drvdata(pdev, priv); > + > + ret = component_add(dev, &mtk_disp_ccorr_component_ops); > + if (ret) > + dev_err(dev, "Failed to add component: %d\n", ret); > + > + return ret; > +} > + > +static int mtk_disp_ccorr_remove(struct platform_device *pdev) > +{ > + component_del(&pdev->dev, &mtk_disp_ccorr_component_ops); > + > + return 0; > +} > + > +static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { > + { .compatible = "mediatek,mt8183-disp-ccorr"}, > + {}, > +}; > +MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); > + > +struct platform_driver mtk_disp_ccorr_driver = { > + .probe = mtk_disp_ccorr_probe, > + .remove = mtk_disp_ccorr_remove, > + .driver = { > + .name = "mediatek-disp-ccorr", > + .owner = THIS_MODULE, > + .of_match_table = mtk_disp_ccorr_driver_dt_match, > + }, > +}; > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > index cdb0383f99061..cafd9df2d63bb 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > @@ -9,6 +9,15 @@ > #include <linux/soc/mediatek/mtk-cmdq.h> > #include "mtk_drm_plane.h" > > +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state); > +int mtk_ccorr_clk_enable(struct device *dev); > +void mtk_ccorr_clk_disable(struct device *dev); > +void mtk_ccorr_config(struct device *dev, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); > +void mtk_ccorr_start(struct device *dev); > +void mtk_ccorr_stop(struct device *dev); > + > void mtk_color_bypass_shadow(struct device *dev); > int mtk_color_clk_enable(struct device *dev); > void mtk_color_clk_disable(struct device *dev); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index 7f5614a6faab8..445ea805d43f3 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -35,20 +35,6 @@ > #define DISP_AAL_EN 0x0000 > #define DISP_AAL_SIZE 0x0030 > > -#define DISP_CCORR_EN 0x0000 > -#define CCORR_EN BIT(0) > -#define DISP_CCORR_CFG 0x0020 > -#define CCORR_RELAY_MODE BIT(0) > -#define CCORR_ENGINE_EN BIT(1) > -#define CCORR_GAMMA_OFF BIT(2) > -#define CCORR_WGAMUT_SRC_CLIP BIT(3) > -#define DISP_CCORR_SIZE 0x0030 > -#define DISP_CCORR_COEF_0 0x0080 > -#define DISP_CCORR_COEF_1 0x0084 > -#define DISP_CCORR_COEF_2 0x0088 > -#define DISP_CCORR_COEF_3 0x008C > -#define DISP_CCORR_COEF_4 0x0090 > - > #define DISP_DITHER_EN 0x0000 > #define DITHER_EN BIT(0) > #define DISP_DITHER_CFG 0x0020 > @@ -266,82 +252,6 @@ static void mtk_aal_stop(struct device *dev) > writel_relaxed(0x0, priv->regs + DISP_AAL_EN); > } > > -static void mtk_ccorr_config(struct device *dev, unsigned int w, > - unsigned int h, unsigned int vrefresh, > - unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_CCORR_SIZE); > - mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &priv->cmdq_reg, priv->regs, DISP_CCORR_CFG); > -} > - > -static void mtk_ccorr_start(struct device *dev) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - > - writel(CCORR_EN, priv->regs + DISP_CCORR_EN); > -} > - > -static void mtk_ccorr_stop(struct device *dev) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - > - writel_relaxed(0x0, priv->regs + DISP_CCORR_EN); > -} > - > -/* Converts a DRM S31.32 value to the HW S1.10 format. */ > -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) > -{ > - u16 r; > - > - /* Sign bit. */ > - r = in & BIT_ULL(63) ? BIT(11) : 0; > - > - if ((in & GENMASK_ULL(62, 33)) > 0) { > - /* identity value 0x100000000 -> 0x400, */ > - /* if bigger this, set it to max 0x7ff. */ > - r |= GENMASK(10, 0); > - } else { > - /* take the 11 most important bits. */ > - r |= (in >> 22) & GENMASK(10, 0); > - } > - > - return r; > -} > - > -static void mtk_ccorr_ctm_set(struct device *dev, > - struct drm_crtc_state *state) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - struct drm_property_blob *blob = state->ctm; > - struct drm_color_ctm *ctm; > - const u64 *input; > - uint16_t coeffs[9] = { 0 }; > - int i; > - struct cmdq_pkt *cmdq_pkt = NULL; > - > - if (!blob) > - return; > - > - ctm = (struct drm_color_ctm *)blob->data; > - input = ctm->matrix; > - > - for (i = 0; i < ARRAY_SIZE(coeffs); i++) > - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > - > - mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_0); > - mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_1); > - mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_2); > - mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_3); > - mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_4); > -} > - > static void mtk_dither_config(struct device *dev, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > @@ -380,8 +290,8 @@ static const struct mtk_ddp_comp_funcs ddp_aal = { > }; > > static const struct mtk_ddp_comp_funcs ddp_ccorr = { > - .clk_enable = mtk_ddp_clk_enable, > - .clk_disable = mtk_ddp_clk_disable, > + .clk_enable = mtk_ccorr_clk_enable, > + .clk_disable = mtk_ccorr_clk_disable, > .config = mtk_ccorr_config, > .start = mtk_ccorr_start, > .stop = mtk_ccorr_stop, > @@ -642,6 +552,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, > } > > if (type == MTK_DISP_BLS || > + type == MTK_DISP_CCORR || > type == MTK_DISP_COLOR || > type == MTK_DISP_GAMMA || > type == MTK_DPI || > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index 486e73e675ad5..b013d56d27773 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -531,11 +531,12 @@ static int mtk_drm_probe(struct platform_device *pdev) > private->comp_node[comp_id] = of_node_get(node); > > /* > - * Currently only the COLOR, GAMMA, OVL, RDMA, DSI, and DPI blocks have > - * separate component platform drivers and initialize their own > + * Currently only the CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI > + * blocks have separate component platform drivers and initialize their own > * DDP component structure. The others are initialized here. > */ > - if (comp_type == MTK_DISP_COLOR || > + if (comp_type == MTK_DISP_CCORR || > + comp_type == MTK_DISP_COLOR || > comp_type == MTK_DISP_GAMMA || > comp_type == MTK_DISP_OVL || > comp_type == MTK_DISP_OVL_2L || > @@ -634,6 +635,7 @@ static struct platform_driver mtk_drm_platform_driver = { > }; > > static struct platform_driver * const mtk_drm_drivers[] = { > + &mtk_disp_ccorr_driver, > &mtk_disp_color_driver, > &mtk_disp_gamma_driver, > &mtk_disp_ovl_driver, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > index 0e54e3d51014a..637f5669e8954 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > @@ -46,6 +46,7 @@ struct mtk_drm_private { > struct drm_atomic_state *suspend_state; > }; > > +extern struct platform_driver mtk_disp_ccorr_driver; > extern struct platform_driver mtk_disp_color_driver; > extern struct platform_driver mtk_disp_gamma_driver; > extern struct platform_driver mtk_disp_ovl_driver; > -- > 2.30.0.365.g02bc693789-goog > > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 4/8] drm/mediatek: separate ccorr module @ 2021-02-03 16:13 ` Chun-Kuang Hu 0 siblings, 0 replies; 64+ messages in thread From: Chun-Kuang Hu @ 2021-02-03 16:13 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Mark Rutland, DTML, David Airlie, linux-kernel, DRI Development, Matthias Brugger, moderated list:ARM/Mediatek SoC support, Yongqiang Niu, Linux ARM Hi, Hsin-Yi: Hsin-Yi Wang <hsinyi@chromium.org> 於 2021年2月2日 週二 下午4:13寫道： > > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > ccorr ctm matrix bits will be different in mt8192 Applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, Chun-Kuang. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > Reviewed-by: CK Hu <ck.hu@mediatek.com> > --- > drivers/gpu/drm/mediatek/Makefile | 3 +- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 216 ++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 + > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 95 +-------- > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +- > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + > 6 files changed, 236 insertions(+), 96 deletions(-) > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > > diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile > index b64674b944860..dc54a7a690054 100644 > --- a/drivers/gpu/drm/mediatek/Makefile > +++ b/drivers/gpu/drm/mediatek/Makefile > @@ -1,6 +1,7 @@ > # SPDX-License-Identifier: GPL-2.0 > > -mediatek-drm-y := mtk_disp_color.o \ > +mediatek-drm-y := mtk_disp_ccorr.o \ > + mtk_disp_color.o \ > mtk_disp_gamma.o \ > mtk_disp_ovl.o \ > mtk_disp_rdma.o \ > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > new file mode 100644 > index 0000000000000..6ee2431e6b843 > --- /dev/null > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -0,0 +1,216 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2021 MediaTek Inc. > + */ > + > +#include <linux/clk.h> > +#include <linux/component.h> > +#include <linux/module.h> > +#include <linux/of_device.h> > +#include <linux/of_irq.h> > +#include <linux/platform_device.h> > +#include <linux/soc/mediatek/mtk-cmdq.h> > + > +#include "mtk_disp_drv.h" > +#include "mtk_drm_crtc.h" > +#include "mtk_drm_ddp_comp.h" > + > +#define DISP_CCORR_EN 0x0000 > +#define CCORR_EN BIT(0) > +#define DISP_CCORR_CFG 0x0020 > +#define CCORR_RELAY_MODE BIT(0) > +#define CCORR_ENGINE_EN BIT(1) > +#define CCORR_GAMMA_OFF BIT(2) > +#define CCORR_WGAMUT_SRC_CLIP BIT(3) > +#define DISP_CCORR_SIZE 0x0030 > +#define DISP_CCORR_COEF_0 0x0080 > +#define DISP_CCORR_COEF_1 0x0084 > +#define DISP_CCORR_COEF_2 0x0088 > +#define DISP_CCORR_COEF_3 0x008C > +#define DISP_CCORR_COEF_4 0x0090 > + > +struct mtk_disp_ccorr_data { > + u32 reserved; > +}; > + > +/** > + * struct mtk_disp_ccorr - DISP_CCORR driver structure > + * @ddp_comp - structure containing type enum and hardware resources > + * @crtc - associated crtc to report irq events to > + */ > +struct mtk_disp_ccorr { > + struct clk *clk; > + void __iomem *regs; > + struct cmdq_client_reg cmdq_reg; > + const struct mtk_disp_ccorr_data *data; > +}; > + > +int mtk_ccorr_clk_enable(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + return clk_prepare_enable(ccorr->clk); > +} > + > +void mtk_ccorr_clk_disable(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + clk_disable_unprepare(ccorr->clk); > +} > + > +void mtk_ccorr_config(struct device *dev, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs, > + DISP_CCORR_SIZE); > + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, > + DISP_CCORR_CFG); > +} > + > +void mtk_ccorr_start(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + writel(CCORR_EN, ccorr->regs + DISP_CCORR_EN); > +} > + > +void mtk_ccorr_stop(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); > +} > + > +/* Converts a DRM S31.32 value to the HW S1.10 format. */ > +static u16 mtk_ctm_s31_32_to_s1_10(u64 in) > +{ > + u16 r; > + > + /* Sign bit. */ > + r = in & BIT_ULL(63) ? BIT(11) : 0; > + > + if ((in & GENMASK_ULL(62, 33)) > 0) { > + /* identity value 0x100000000 -> 0x400, */ > + /* if bigger this, set it to max 0x7ff. */ > + r |= GENMASK(10, 0); > + } else { > + /* take the 11 most important bits. */ > + r |= (in >> 22) & GENMASK(10, 0); > + } > + > + return r; > +} > + > +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + struct drm_property_blob *blob = state->ctm; > + struct drm_color_ctm *ctm; > + const u64 *input; > + uint16_t coeffs[9] = { 0 }; > + int i; > + struct cmdq_pkt *cmdq_pkt = NULL; > + > + if (!blob) > + return; > + > + ctm = (struct drm_color_ctm *)blob->data; > + input = ctm->matrix; > + > + for (i = 0; i < ARRAY_SIZE(coeffs); i++) > + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > + > + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); > + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_1); > + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_2); > + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3); > + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4); > +} > + > +static int mtk_disp_ccorr_bind(struct device *dev, struct device *master, > + void *data) > +{ > + return 0; > +} > + > +static void mtk_disp_ccorr_unbind(struct device *dev, struct device *master, > + void *data) > +{ > +} > + > +static const struct component_ops mtk_disp_ccorr_component_ops = { > + .bind = mtk_disp_ccorr_bind, > + .unbind = mtk_disp_ccorr_unbind, > +}; > + > +static int mtk_disp_ccorr_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct mtk_disp_ccorr *priv; > + struct resource *res; > + int ret; > + > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + priv->clk = devm_clk_get(dev, NULL); > + if (IS_ERR(priv->clk)) { > + dev_err(dev, "failed to get ccorr clk\n"); > + return PTR_ERR(priv->clk); > + } > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + priv->regs = devm_ioremap_resource(dev, res); > + if (IS_ERR(priv->regs)) { > + dev_err(dev, "failed to ioremap ccorr\n"); > + return PTR_ERR(priv->regs); > + } > + > +#if IS_REACHABLE(CONFIG_MTK_CMDQ) > + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); > + if (ret) > + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); > +#endif > + > + priv->data = of_device_get_match_data(dev); > + platform_set_drvdata(pdev, priv); > + > + ret = component_add(dev, &mtk_disp_ccorr_component_ops); > + if (ret) > + dev_err(dev, "Failed to add component: %d\n", ret); > + > + return ret; > +} > + > +static int mtk_disp_ccorr_remove(struct platform_device *pdev) > +{ > + component_del(&pdev->dev, &mtk_disp_ccorr_component_ops); > + > + return 0; > +} > + > +static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { > + { .compatible = "mediatek,mt8183-disp-ccorr"}, > + {}, > +}; > +MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); > + > +struct platform_driver mtk_disp_ccorr_driver = { > + .probe = mtk_disp_ccorr_probe, > + .remove = mtk_disp_ccorr_remove, > + .driver = { > + .name = "mediatek-disp-ccorr", > + .owner = THIS_MODULE, > + .of_match_table = mtk_disp_ccorr_driver_dt_match, > + }, > +}; > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > index cdb0383f99061..cafd9df2d63bb 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > @@ -9,6 +9,15 @@ > #include <linux/soc/mediatek/mtk-cmdq.h> > #include "mtk_drm_plane.h" > > +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state); > +int mtk_ccorr_clk_enable(struct device *dev); > +void mtk_ccorr_clk_disable(struct device *dev); > +void mtk_ccorr_config(struct device *dev, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); > +void mtk_ccorr_start(struct device *dev); > +void mtk_ccorr_stop(struct device *dev); > + > void mtk_color_bypass_shadow(struct device *dev); > int mtk_color_clk_enable(struct device *dev); > void mtk_color_clk_disable(struct device *dev); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index 7f5614a6faab8..445ea805d43f3 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -35,20 +35,6 @@ > #define DISP_AAL_EN 0x0000 > #define DISP_AAL_SIZE 0x0030 > > -#define DISP_CCORR_EN 0x0000 > -#define CCORR_EN BIT(0) > -#define DISP_CCORR_CFG 0x0020 > -#define CCORR_RELAY_MODE BIT(0) > -#define CCORR_ENGINE_EN BIT(1) > -#define CCORR_GAMMA_OFF BIT(2) > -#define CCORR_WGAMUT_SRC_CLIP BIT(3) > -#define DISP_CCORR_SIZE 0x0030 > -#define DISP_CCORR_COEF_0 0x0080 > -#define DISP_CCORR_COEF_1 0x0084 > -#define DISP_CCORR_COEF_2 0x0088 > -#define DISP_CCORR_COEF_3 0x008C > -#define DISP_CCORR_COEF_4 0x0090 > - > #define DISP_DITHER_EN 0x0000 > #define DITHER_EN BIT(0) > #define DISP_DITHER_CFG 0x0020 > @@ -266,82 +252,6 @@ static void mtk_aal_stop(struct device *dev) > writel_relaxed(0x0, priv->regs + DISP_AAL_EN); > } > > -static void mtk_ccorr_config(struct device *dev, unsigned int w, > - unsigned int h, unsigned int vrefresh, > - unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_CCORR_SIZE); > - mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &priv->cmdq_reg, priv->regs, DISP_CCORR_CFG); > -} > - > -static void mtk_ccorr_start(struct device *dev) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - > - writel(CCORR_EN, priv->regs + DISP_CCORR_EN); > -} > - > -static void mtk_ccorr_stop(struct device *dev) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - > - writel_relaxed(0x0, priv->regs + DISP_CCORR_EN); > -} > - > -/* Converts a DRM S31.32 value to the HW S1.10 format. */ > -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) > -{ > - u16 r; > - > - /* Sign bit. */ > - r = in & BIT_ULL(63) ? BIT(11) : 0; > - > - if ((in & GENMASK_ULL(62, 33)) > 0) { > - /* identity value 0x100000000 -> 0x400, */ > - /* if bigger this, set it to max 0x7ff. */ > - r |= GENMASK(10, 0); > - } else { > - /* take the 11 most important bits. */ > - r |= (in >> 22) & GENMASK(10, 0); > - } > - > - return r; > -} > - > -static void mtk_ccorr_ctm_set(struct device *dev, > - struct drm_crtc_state *state) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - struct drm_property_blob *blob = state->ctm; > - struct drm_color_ctm *ctm; > - const u64 *input; > - uint16_t coeffs[9] = { 0 }; > - int i; > - struct cmdq_pkt *cmdq_pkt = NULL; > - > - if (!blob) > - return; > - > - ctm = (struct drm_color_ctm *)blob->data; > - input = ctm->matrix; > - > - for (i = 0; i < ARRAY_SIZE(coeffs); i++) > - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > - > - mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_0); > - mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_1); > - mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_2); > - mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_3); > - mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_4); > -} > - > static void mtk_dither_config(struct device *dev, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > @@ -380,8 +290,8 @@ static const struct mtk_ddp_comp_funcs ddp_aal = { > }; > > static const struct mtk_ddp_comp_funcs ddp_ccorr = { > - .clk_enable = mtk_ddp_clk_enable, > - .clk_disable = mtk_ddp_clk_disable, > + .clk_enable = mtk_ccorr_clk_enable, > + .clk_disable = mtk_ccorr_clk_disable, > .config = mtk_ccorr_config, > .start = mtk_ccorr_start, > .stop = mtk_ccorr_stop, > @@ -642,6 +552,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, > } > > if (type == MTK_DISP_BLS || > + type == MTK_DISP_CCORR || > type == MTK_DISP_COLOR || > type == MTK_DISP_GAMMA || > type == MTK_DPI || > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index 486e73e675ad5..b013d56d27773 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -531,11 +531,12 @@ static int mtk_drm_probe(struct platform_device *pdev) > private->comp_node[comp_id] = of_node_get(node); > > /* > - * Currently only the COLOR, GAMMA, OVL, RDMA, DSI, and DPI blocks have > - * separate component platform drivers and initialize their own > + * Currently only the CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI > + * blocks have separate component platform drivers and initialize their own > * DDP component structure. The others are initialized here. > */ > - if (comp_type == MTK_DISP_COLOR || > + if (comp_type == MTK_DISP_CCORR || > + comp_type == MTK_DISP_COLOR || > comp_type == MTK_DISP_GAMMA || > comp_type == MTK_DISP_OVL || > comp_type == MTK_DISP_OVL_2L || > @@ -634,6 +635,7 @@ static struct platform_driver mtk_drm_platform_driver = { > }; > > static struct platform_driver * const mtk_drm_drivers[] = { > + &mtk_disp_ccorr_driver, > &mtk_disp_color_driver, > &mtk_disp_gamma_driver, > &mtk_disp_ovl_driver, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > index 0e54e3d51014a..637f5669e8954 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > @@ -46,6 +46,7 @@ struct mtk_drm_private { > struct drm_atomic_state *suspend_state; > }; > > +extern struct platform_driver mtk_disp_ccorr_driver; > extern struct platform_driver mtk_disp_color_driver; > extern struct platform_driver mtk_disp_gamma_driver; > extern struct platform_driver mtk_disp_ovl_driver; > -- > 2.30.0.365.g02bc693789-goog > > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 4/8] drm/mediatek: separate ccorr module @ 2021-02-03 16:13 ` Chun-Kuang Hu 0 siblings, 0 replies; 64+ messages in thread From: Chun-Kuang Hu @ 2021-02-03 16:13 UTC (permalink / raw) To: Hsin-Yi Wang Cc: CK Hu, Philipp Zabel, Matthias Brugger, Mark Rutland, DTML, Yongqiang Niu, David Airlie, linux-kernel, DRI Development, moderated list:ARM/Mediatek SoC support, Daniel Vetter, Linux ARM Hi, Hsin-Yi: Hsin-Yi Wang <hsinyi@chromium.org> 於 2021年2月2日 週二 下午4:13寫道： > > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > ccorr ctm matrix bits will be different in mt8192 Applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, Chun-Kuang. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > Reviewed-by: CK Hu <ck.hu@mediatek.com> > --- > drivers/gpu/drm/mediatek/Makefile | 3 +- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 216 ++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 + > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 95 +-------- > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +- > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + > 6 files changed, 236 insertions(+), 96 deletions(-) > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > > diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile > index b64674b944860..dc54a7a690054 100644 > --- a/drivers/gpu/drm/mediatek/Makefile > +++ b/drivers/gpu/drm/mediatek/Makefile > @@ -1,6 +1,7 @@ > # SPDX-License-Identifier: GPL-2.0 > > -mediatek-drm-y := mtk_disp_color.o \ > +mediatek-drm-y := mtk_disp_ccorr.o \ > + mtk_disp_color.o \ > mtk_disp_gamma.o \ > mtk_disp_ovl.o \ > mtk_disp_rdma.o \ > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > new file mode 100644 > index 0000000000000..6ee2431e6b843 > --- /dev/null > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -0,0 +1,216 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2021 MediaTek Inc. > + */ > + > +#include <linux/clk.h> > +#include <linux/component.h> > +#include <linux/module.h> > +#include <linux/of_device.h> > +#include <linux/of_irq.h> > +#include <linux/platform_device.h> > +#include <linux/soc/mediatek/mtk-cmdq.h> > + > +#include "mtk_disp_drv.h" > +#include "mtk_drm_crtc.h" > +#include "mtk_drm_ddp_comp.h" > + > +#define DISP_CCORR_EN 0x0000 > +#define CCORR_EN BIT(0) > +#define DISP_CCORR_CFG 0x0020 > +#define CCORR_RELAY_MODE BIT(0) > +#define CCORR_ENGINE_EN BIT(1) > +#define CCORR_GAMMA_OFF BIT(2) > +#define CCORR_WGAMUT_SRC_CLIP BIT(3) > +#define DISP_CCORR_SIZE 0x0030 > +#define DISP_CCORR_COEF_0 0x0080 > +#define DISP_CCORR_COEF_1 0x0084 > +#define DISP_CCORR_COEF_2 0x0088 > +#define DISP_CCORR_COEF_3 0x008C > +#define DISP_CCORR_COEF_4 0x0090 > + > +struct mtk_disp_ccorr_data { > + u32 reserved; > +}; > + > +/** > + * struct mtk_disp_ccorr - DISP_CCORR driver structure > + * @ddp_comp - structure containing type enum and hardware resources > + * @crtc - associated crtc to report irq events to > + */ > +struct mtk_disp_ccorr { > + struct clk *clk; > + void __iomem *regs; > + struct cmdq_client_reg cmdq_reg; > + const struct mtk_disp_ccorr_data *data; > +}; > + > +int mtk_ccorr_clk_enable(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + return clk_prepare_enable(ccorr->clk); > +} > + > +void mtk_ccorr_clk_disable(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + clk_disable_unprepare(ccorr->clk); > +} > + > +void mtk_ccorr_config(struct device *dev, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs, > + DISP_CCORR_SIZE); > + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, > + DISP_CCORR_CFG); > +} > + > +void mtk_ccorr_start(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + writel(CCORR_EN, ccorr->regs + DISP_CCORR_EN); > +} > + > +void mtk_ccorr_stop(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); > +} > + > +/* Converts a DRM S31.32 value to the HW S1.10 format. */ > +static u16 mtk_ctm_s31_32_to_s1_10(u64 in) > +{ > + u16 r; > + > + /* Sign bit. */ > + r = in & BIT_ULL(63) ? BIT(11) : 0; > + > + if ((in & GENMASK_ULL(62, 33)) > 0) { > + /* identity value 0x100000000 -> 0x400, */ > + /* if bigger this, set it to max 0x7ff. */ > + r |= GENMASK(10, 0); > + } else { > + /* take the 11 most important bits. */ > + r |= (in >> 22) & GENMASK(10, 0); > + } > + > + return r; > +} > + > +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + struct drm_property_blob *blob = state->ctm; > + struct drm_color_ctm *ctm; > + const u64 *input; > + uint16_t coeffs[9] = { 0 }; > + int i; > + struct cmdq_pkt *cmdq_pkt = NULL; > + > + if (!blob) > + return; > + > + ctm = (struct drm_color_ctm *)blob->data; > + input = ctm->matrix; > + > + for (i = 0; i < ARRAY_SIZE(coeffs); i++) > + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > + > + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); > + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_1); > + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_2); > + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3); > + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4); > +} > + > +static int mtk_disp_ccorr_bind(struct device *dev, struct device *master, > + void *data) > +{ > + return 0; > +} > + > +static void mtk_disp_ccorr_unbind(struct device *dev, struct device *master, > + void *data) > +{ > +} > + > +static const struct component_ops mtk_disp_ccorr_component_ops = { > + .bind = mtk_disp_ccorr_bind, > + .unbind = mtk_disp_ccorr_unbind, > +}; > + > +static int mtk_disp_ccorr_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct mtk_disp_ccorr *priv; > + struct resource *res; > + int ret; > + > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + priv->clk = devm_clk_get(dev, NULL); > + if (IS_ERR(priv->clk)) { > + dev_err(dev, "failed to get ccorr clk\n"); > + return PTR_ERR(priv->clk); > + } > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + priv->regs = devm_ioremap_resource(dev, res); > + if (IS_ERR(priv->regs)) { > + dev_err(dev, "failed to ioremap ccorr\n"); > + return PTR_ERR(priv->regs); > + } > + > +#if IS_REACHABLE(CONFIG_MTK_CMDQ) > + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); > + if (ret) > + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); > +#endif > + > + priv->data = of_device_get_match_data(dev); > + platform_set_drvdata(pdev, priv); > + > + ret = component_add(dev, &mtk_disp_ccorr_component_ops); > + if (ret) > + dev_err(dev, "Failed to add component: %d\n", ret); > + > + return ret; > +} > + > +static int mtk_disp_ccorr_remove(struct platform_device *pdev) > +{ > + component_del(&pdev->dev, &mtk_disp_ccorr_component_ops); > + > + return 0; > +} > + > +static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { > + { .compatible = "mediatek,mt8183-disp-ccorr"}, > + {}, > +}; > +MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); > + > +struct platform_driver mtk_disp_ccorr_driver = { > + .probe = mtk_disp_ccorr_probe, > + .remove = mtk_disp_ccorr_remove, > + .driver = { > + .name = "mediatek-disp-ccorr", > + .owner = THIS_MODULE, > + .of_match_table = mtk_disp_ccorr_driver_dt_match, > + }, > +}; > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > index cdb0383f99061..cafd9df2d63bb 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > @@ -9,6 +9,15 @@ > #include <linux/soc/mediatek/mtk-cmdq.h> > #include "mtk_drm_plane.h" > > +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state); > +int mtk_ccorr_clk_enable(struct device *dev); > +void mtk_ccorr_clk_disable(struct device *dev); > +void mtk_ccorr_config(struct device *dev, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); > +void mtk_ccorr_start(struct device *dev); > +void mtk_ccorr_stop(struct device *dev); > + > void mtk_color_bypass_shadow(struct device *dev); > int mtk_color_clk_enable(struct device *dev); > void mtk_color_clk_disable(struct device *dev); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index 7f5614a6faab8..445ea805d43f3 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -35,20 +35,6 @@ > #define DISP_AAL_EN 0x0000 > #define DISP_AAL_SIZE 0x0030 > > -#define DISP_CCORR_EN 0x0000 > -#define CCORR_EN BIT(0) > -#define DISP_CCORR_CFG 0x0020 > -#define CCORR_RELAY_MODE BIT(0) > -#define CCORR_ENGINE_EN BIT(1) > -#define CCORR_GAMMA_OFF BIT(2) > -#define CCORR_WGAMUT_SRC_CLIP BIT(3) > -#define DISP_CCORR_SIZE 0x0030 > -#define DISP_CCORR_COEF_0 0x0080 > -#define DISP_CCORR_COEF_1 0x0084 > -#define DISP_CCORR_COEF_2 0x0088 > -#define DISP_CCORR_COEF_3 0x008C > -#define DISP_CCORR_COEF_4 0x0090 > - > #define DISP_DITHER_EN 0x0000 > #define DITHER_EN BIT(0) > #define DISP_DITHER_CFG 0x0020 > @@ -266,82 +252,6 @@ static void mtk_aal_stop(struct device *dev) > writel_relaxed(0x0, priv->regs + DISP_AAL_EN); > } > > -static void mtk_ccorr_config(struct device *dev, unsigned int w, > - unsigned int h, unsigned int vrefresh, > - unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_CCORR_SIZE); > - mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &priv->cmdq_reg, priv->regs, DISP_CCORR_CFG); > -} > - > -static void mtk_ccorr_start(struct device *dev) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - > - writel(CCORR_EN, priv->regs + DISP_CCORR_EN); > -} > - > -static void mtk_ccorr_stop(struct device *dev) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - > - writel_relaxed(0x0, priv->regs + DISP_CCORR_EN); > -} > - > -/* Converts a DRM S31.32 value to the HW S1.10 format. */ > -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) > -{ > - u16 r; > - > - /* Sign bit. */ > - r = in & BIT_ULL(63) ? BIT(11) : 0; > - > - if ((in & GENMASK_ULL(62, 33)) > 0) { > - /* identity value 0x100000000 -> 0x400, */ > - /* if bigger this, set it to max 0x7ff. */ > - r |= GENMASK(10, 0); > - } else { > - /* take the 11 most important bits. */ > - r |= (in >> 22) & GENMASK(10, 0); > - } > - > - return r; > -} > - > -static void mtk_ccorr_ctm_set(struct device *dev, > - struct drm_crtc_state *state) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - struct drm_property_blob *blob = state->ctm; > - struct drm_color_ctm *ctm; > - const u64 *input; > - uint16_t coeffs[9] = { 0 }; > - int i; > - struct cmdq_pkt *cmdq_pkt = NULL; > - > - if (!blob) > - return; > - > - ctm = (struct drm_color_ctm *)blob->data; > - input = ctm->matrix; > - > - for (i = 0; i < ARRAY_SIZE(coeffs); i++) > - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > - > - mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_0); > - mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_1); > - mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_2); > - mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_3); > - mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_4); > -} > - > static void mtk_dither_config(struct device *dev, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > @@ -380,8 +290,8 @@ static const struct mtk_ddp_comp_funcs ddp_aal = { > }; > > static const struct mtk_ddp_comp_funcs ddp_ccorr = { > - .clk_enable = mtk_ddp_clk_enable, > - .clk_disable = mtk_ddp_clk_disable, > + .clk_enable = mtk_ccorr_clk_enable, > + .clk_disable = mtk_ccorr_clk_disable, > .config = mtk_ccorr_config, > .start = mtk_ccorr_start, > .stop = mtk_ccorr_stop, > @@ -642,6 +552,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, > } > > if (type == MTK_DISP_BLS || > + type == MTK_DISP_CCORR || > type == MTK_DISP_COLOR || > type == MTK_DISP_GAMMA || > type == MTK_DPI || > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index 486e73e675ad5..b013d56d27773 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -531,11 +531,12 @@ static int mtk_drm_probe(struct platform_device *pdev) > private->comp_node[comp_id] = of_node_get(node); > > /* > - * Currently only the COLOR, GAMMA, OVL, RDMA, DSI, and DPI blocks have > - * separate component platform drivers and initialize their own > + * Currently only the CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI > + * blocks have separate component platform drivers and initialize their own > * DDP component structure. The others are initialized here. > */ > - if (comp_type == MTK_DISP_COLOR || > + if (comp_type == MTK_DISP_CCORR || > + comp_type == MTK_DISP_COLOR || > comp_type == MTK_DISP_GAMMA || > comp_type == MTK_DISP_OVL || > comp_type == MTK_DISP_OVL_2L || > @@ -634,6 +635,7 @@ static struct platform_driver mtk_drm_platform_driver = { > }; > > static struct platform_driver * const mtk_drm_drivers[] = { > + &mtk_disp_ccorr_driver, > &mtk_disp_color_driver, > &mtk_disp_gamma_driver, > &mtk_disp_ovl_driver, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > index 0e54e3d51014a..637f5669e8954 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > @@ -46,6 +46,7 @@ struct mtk_drm_private { > struct drm_atomic_state *suspend_state; > }; > > +extern struct platform_driver mtk_disp_ccorr_driver; > extern struct platform_driver mtk_disp_color_driver; > extern struct platform_driver mtk_disp_gamma_driver; > extern struct platform_driver mtk_disp_ovl_driver; > -- > 2.30.0.365.g02bc693789-goog > > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 4/8] drm/mediatek: separate ccorr module @ 2021-02-03 16:13 ` Chun-Kuang Hu 0 siblings, 0 replies; 64+ messages in thread From: Chun-Kuang Hu @ 2021-02-03 16:13 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Mark Rutland, DTML, Philipp Zabel, David Airlie, linux-kernel, DRI Development, Matthias Brugger, moderated list:ARM/Mediatek SoC support, Yongqiang Niu, CK Hu, Daniel Vetter, Linux ARM Hi, Hsin-Yi: Hsin-Yi Wang <hsinyi@chromium.org> 於 2021年2月2日 週二 下午4:13寫道： > > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > ccorr ctm matrix bits will be different in mt8192 Applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, Chun-Kuang. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > Reviewed-by: CK Hu <ck.hu@mediatek.com> > --- > drivers/gpu/drm/mediatek/Makefile | 3 +- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 216 ++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 + > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 95 +-------- > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +- > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + > 6 files changed, 236 insertions(+), 96 deletions(-) > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > > diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile > index b64674b944860..dc54a7a690054 100644 > --- a/drivers/gpu/drm/mediatek/Makefile > +++ b/drivers/gpu/drm/mediatek/Makefile > @@ -1,6 +1,7 @@ > # SPDX-License-Identifier: GPL-2.0 > > -mediatek-drm-y := mtk_disp_color.o \ > +mediatek-drm-y := mtk_disp_ccorr.o \ > + mtk_disp_color.o \ > mtk_disp_gamma.o \ > mtk_disp_ovl.o \ > mtk_disp_rdma.o \ > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > new file mode 100644 > index 0000000000000..6ee2431e6b843 > --- /dev/null > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -0,0 +1,216 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2021 MediaTek Inc. > + */ > + > +#include <linux/clk.h> > +#include <linux/component.h> > +#include <linux/module.h> > +#include <linux/of_device.h> > +#include <linux/of_irq.h> > +#include <linux/platform_device.h> > +#include <linux/soc/mediatek/mtk-cmdq.h> > + > +#include "mtk_disp_drv.h" > +#include "mtk_drm_crtc.h" > +#include "mtk_drm_ddp_comp.h" > + > +#define DISP_CCORR_EN 0x0000 > +#define CCORR_EN BIT(0) > +#define DISP_CCORR_CFG 0x0020 > +#define CCORR_RELAY_MODE BIT(0) > +#define CCORR_ENGINE_EN BIT(1) > +#define CCORR_GAMMA_OFF BIT(2) > +#define CCORR_WGAMUT_SRC_CLIP BIT(3) > +#define DISP_CCORR_SIZE 0x0030 > +#define DISP_CCORR_COEF_0 0x0080 > +#define DISP_CCORR_COEF_1 0x0084 > +#define DISP_CCORR_COEF_2 0x0088 > +#define DISP_CCORR_COEF_3 0x008C > +#define DISP_CCORR_COEF_4 0x0090 > + > +struct mtk_disp_ccorr_data { > + u32 reserved; > +}; > + > +/** > + * struct mtk_disp_ccorr - DISP_CCORR driver structure > + * @ddp_comp - structure containing type enum and hardware resources > + * @crtc - associated crtc to report irq events to > + */ > +struct mtk_disp_ccorr { > + struct clk *clk; > + void __iomem *regs; > + struct cmdq_client_reg cmdq_reg; > + const struct mtk_disp_ccorr_data *data; > +}; > + > +int mtk_ccorr_clk_enable(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + return clk_prepare_enable(ccorr->clk); > +} > + > +void mtk_ccorr_clk_disable(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + clk_disable_unprepare(ccorr->clk); > +} > + > +void mtk_ccorr_config(struct device *dev, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs, > + DISP_CCORR_SIZE); > + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, > + DISP_CCORR_CFG); > +} > + > +void mtk_ccorr_start(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + writel(CCORR_EN, ccorr->regs + DISP_CCORR_EN); > +} > + > +void mtk_ccorr_stop(struct device *dev) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + > + writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); > +} > + > +/* Converts a DRM S31.32 value to the HW S1.10 format. */ > +static u16 mtk_ctm_s31_32_to_s1_10(u64 in) > +{ > + u16 r; > + > + /* Sign bit. */ > + r = in & BIT_ULL(63) ? BIT(11) : 0; > + > + if ((in & GENMASK_ULL(62, 33)) > 0) { > + /* identity value 0x100000000 -> 0x400, */ > + /* if bigger this, set it to max 0x7ff. */ > + r |= GENMASK(10, 0); > + } else { > + /* take the 11 most important bits. */ > + r |= (in >> 22) & GENMASK(10, 0); > + } > + > + return r; > +} > + > +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > +{ > + struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > + struct drm_property_blob *blob = state->ctm; > + struct drm_color_ctm *ctm; > + const u64 *input; > + uint16_t coeffs[9] = { 0 }; > + int i; > + struct cmdq_pkt *cmdq_pkt = NULL; > + > + if (!blob) > + return; > + > + ctm = (struct drm_color_ctm *)blob->data; > + input = ctm->matrix; > + > + for (i = 0; i < ARRAY_SIZE(coeffs); i++) > + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > + > + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); > + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_1); > + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_2); > + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3); > + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, > + &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4); > +} > + > +static int mtk_disp_ccorr_bind(struct device *dev, struct device *master, > + void *data) > +{ > + return 0; > +} > + > +static void mtk_disp_ccorr_unbind(struct device *dev, struct device *master, > + void *data) > +{ > +} > + > +static const struct component_ops mtk_disp_ccorr_component_ops = { > + .bind = mtk_disp_ccorr_bind, > + .unbind = mtk_disp_ccorr_unbind, > +}; > + > +static int mtk_disp_ccorr_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct mtk_disp_ccorr *priv; > + struct resource *res; > + int ret; > + > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + priv->clk = devm_clk_get(dev, NULL); > + if (IS_ERR(priv->clk)) { > + dev_err(dev, "failed to get ccorr clk\n"); > + return PTR_ERR(priv->clk); > + } > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + priv->regs = devm_ioremap_resource(dev, res); > + if (IS_ERR(priv->regs)) { > + dev_err(dev, "failed to ioremap ccorr\n"); > + return PTR_ERR(priv->regs); > + } > + > +#if IS_REACHABLE(CONFIG_MTK_CMDQ) > + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); > + if (ret) > + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n"); > +#endif > + > + priv->data = of_device_get_match_data(dev); > + platform_set_drvdata(pdev, priv); > + > + ret = component_add(dev, &mtk_disp_ccorr_component_ops); > + if (ret) > + dev_err(dev, "Failed to add component: %d\n", ret); > + > + return ret; > +} > + > +static int mtk_disp_ccorr_remove(struct platform_device *pdev) > +{ > + component_del(&pdev->dev, &mtk_disp_ccorr_component_ops); > + > + return 0; > +} > + > +static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { > + { .compatible = "mediatek,mt8183-disp-ccorr"}, > + {}, > +}; > +MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); > + > +struct platform_driver mtk_disp_ccorr_driver = { > + .probe = mtk_disp_ccorr_probe, > + .remove = mtk_disp_ccorr_remove, > + .driver = { > + .name = "mediatek-disp-ccorr", > + .owner = THIS_MODULE, > + .of_match_table = mtk_disp_ccorr_driver_dt_match, > + }, > +}; > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > index cdb0383f99061..cafd9df2d63bb 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h > @@ -9,6 +9,15 @@ > #include <linux/soc/mediatek/mtk-cmdq.h> > #include "mtk_drm_plane.h" > > +void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state); > +int mtk_ccorr_clk_enable(struct device *dev); > +void mtk_ccorr_clk_disable(struct device *dev); > +void mtk_ccorr_config(struct device *dev, unsigned int w, > + unsigned int h, unsigned int vrefresh, > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); > +void mtk_ccorr_start(struct device *dev); > +void mtk_ccorr_stop(struct device *dev); > + > void mtk_color_bypass_shadow(struct device *dev); > int mtk_color_clk_enable(struct device *dev); > void mtk_color_clk_disable(struct device *dev); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index 7f5614a6faab8..445ea805d43f3 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -35,20 +35,6 @@ > #define DISP_AAL_EN 0x0000 > #define DISP_AAL_SIZE 0x0030 > > -#define DISP_CCORR_EN 0x0000 > -#define CCORR_EN BIT(0) > -#define DISP_CCORR_CFG 0x0020 > -#define CCORR_RELAY_MODE BIT(0) > -#define CCORR_ENGINE_EN BIT(1) > -#define CCORR_GAMMA_OFF BIT(2) > -#define CCORR_WGAMUT_SRC_CLIP BIT(3) > -#define DISP_CCORR_SIZE 0x0030 > -#define DISP_CCORR_COEF_0 0x0080 > -#define DISP_CCORR_COEF_1 0x0084 > -#define DISP_CCORR_COEF_2 0x0088 > -#define DISP_CCORR_COEF_3 0x008C > -#define DISP_CCORR_COEF_4 0x0090 > - > #define DISP_DITHER_EN 0x0000 > #define DITHER_EN BIT(0) > #define DISP_DITHER_CFG 0x0020 > @@ -266,82 +252,6 @@ static void mtk_aal_stop(struct device *dev) > writel_relaxed(0x0, priv->regs + DISP_AAL_EN); > } > > -static void mtk_ccorr_config(struct device *dev, unsigned int w, > - unsigned int h, unsigned int vrefresh, > - unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_CCORR_SIZE); > - mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &priv->cmdq_reg, priv->regs, DISP_CCORR_CFG); > -} > - > -static void mtk_ccorr_start(struct device *dev) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - > - writel(CCORR_EN, priv->regs + DISP_CCORR_EN); > -} > - > -static void mtk_ccorr_stop(struct device *dev) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - > - writel_relaxed(0x0, priv->regs + DISP_CCORR_EN); > -} > - > -/* Converts a DRM S31.32 value to the HW S1.10 format. */ > -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) > -{ > - u16 r; > - > - /* Sign bit. */ > - r = in & BIT_ULL(63) ? BIT(11) : 0; > - > - if ((in & GENMASK_ULL(62, 33)) > 0) { > - /* identity value 0x100000000 -> 0x400, */ > - /* if bigger this, set it to max 0x7ff. */ > - r |= GENMASK(10, 0); > - } else { > - /* take the 11 most important bits. */ > - r |= (in >> 22) & GENMASK(10, 0); > - } > - > - return r; > -} > - > -static void mtk_ccorr_ctm_set(struct device *dev, > - struct drm_crtc_state *state) > -{ > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > - struct drm_property_blob *blob = state->ctm; > - struct drm_color_ctm *ctm; > - const u64 *input; > - uint16_t coeffs[9] = { 0 }; > - int i; > - struct cmdq_pkt *cmdq_pkt = NULL; > - > - if (!blob) > - return; > - > - ctm = (struct drm_color_ctm *)blob->data; > - input = ctm->matrix; > - > - for (i = 0; i < ARRAY_SIZE(coeffs); i++) > - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > - > - mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_0); > - mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_1); > - mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_2); > - mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_3); > - mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, > - &priv->cmdq_reg, priv->regs, DISP_CCORR_COEF_4); > -} > - > static void mtk_dither_config(struct device *dev, unsigned int w, > unsigned int h, unsigned int vrefresh, > unsigned int bpc, struct cmdq_pkt *cmdq_pkt) > @@ -380,8 +290,8 @@ static const struct mtk_ddp_comp_funcs ddp_aal = { > }; > > static const struct mtk_ddp_comp_funcs ddp_ccorr = { > - .clk_enable = mtk_ddp_clk_enable, > - .clk_disable = mtk_ddp_clk_disable, > + .clk_enable = mtk_ccorr_clk_enable, > + .clk_disable = mtk_ccorr_clk_disable, > .config = mtk_ccorr_config, > .start = mtk_ccorr_start, > .stop = mtk_ccorr_stop, > @@ -642,6 +552,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, > } > > if (type == MTK_DISP_BLS || > + type == MTK_DISP_CCORR || > type == MTK_DISP_COLOR || > type == MTK_DISP_GAMMA || > type == MTK_DPI || > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index 486e73e675ad5..b013d56d27773 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -531,11 +531,12 @@ static int mtk_drm_probe(struct platform_device *pdev) > private->comp_node[comp_id] = of_node_get(node); > > /* > - * Currently only the COLOR, GAMMA, OVL, RDMA, DSI, and DPI blocks have > - * separate component platform drivers and initialize their own > + * Currently only the CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI > + * blocks have separate component platform drivers and initialize their own > * DDP component structure. The others are initialized here. > */ > - if (comp_type == MTK_DISP_COLOR || > + if (comp_type == MTK_DISP_CCORR || > + comp_type == MTK_DISP_COLOR || > comp_type == MTK_DISP_GAMMA || > comp_type == MTK_DISP_OVL || > comp_type == MTK_DISP_OVL_2L || > @@ -634,6 +635,7 @@ static struct platform_driver mtk_drm_platform_driver = { > }; > > static struct platform_driver * const mtk_drm_drivers[] = { > + &mtk_disp_ccorr_driver, > &mtk_disp_color_driver, > &mtk_disp_gamma_driver, > &mtk_disp_ovl_driver, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > index 0e54e3d51014a..637f5669e8954 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h > @@ -46,6 +46,7 @@ struct mtk_drm_private { > struct drm_atomic_state *suspend_state; > }; > > +extern struct platform_driver mtk_disp_ccorr_driver; > extern struct platform_driver mtk_disp_color_driver; > extern struct platform_driver mtk_disp_gamma_driver; > extern struct platform_driver mtk_disp_ovl_driver; > -- > 2.30.0.365.g02bc693789-goog > > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v6 5/8] drm/mediatek: Fix ccorr size config 2021-02-02 8:12 ` Hsin-Yi Wang (?) (?) @ 2021-02-02 8:12 ` Hsin-Yi Wang -1 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> Fix setting to follow hardware datasheet. The original error setting affects mt8192 display. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 6ee2431e6b843..6c86673a835c3 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -65,7 +65,7 @@ void mtk_ccorr_config(struct device *dev, unsigned int w, { struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); - mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs, + mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_SIZE); mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_CFG); -- 2.30.0.365.g02bc693789-goog _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 5/8] drm/mediatek: Fix ccorr size config @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> Fix setting to follow hardware datasheet. The original error setting affects mt8192 display. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 6ee2431e6b843..6c86673a835c3 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -65,7 +65,7 @@ void mtk_ccorr_config(struct device *dev, unsigned int w, { struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); - mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs, + mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_SIZE); mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_CFG); -- 2.30.0.365.g02bc693789-goog _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 5/8] drm/mediatek: Fix ccorr size config @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu From: Yongqiang Niu <yongqiang.niu@mediatek.com> Fix setting to follow hardware datasheet. The original error setting affects mt8192 display. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 6ee2431e6b843..6c86673a835c3 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -65,7 +65,7 @@ void mtk_ccorr_config(struct device *dev, unsigned int w, { struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); - mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs, + mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_SIZE); mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_CFG); -- 2.30.0.365.g02bc693789-goog ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 5/8] drm/mediatek: Fix ccorr size config @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> Fix setting to follow hardware datasheet. The original error setting affects mt8192 display. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 6ee2431e6b843..6c86673a835c3 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -65,7 +65,7 @@ void mtk_ccorr_config(struct device *dev, unsigned int w, { struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); - mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs, + mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_SIZE); mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_CFG); -- 2.30.0.365.g02bc693789-goog _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 64+ messages in thread
* Re: [PATCH v6 5/8] drm/mediatek: Fix ccorr size config 2021-02-02 8:12 ` Hsin-Yi Wang (?) (?) @ 2021-02-03 16:13 ` Chun-Kuang Hu -1 siblings, 0 replies; 64+ messages in thread From: Chun-Kuang Hu @ 2021-02-03 16:13 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Mark Rutland, DTML, Philipp Zabel, David Airlie, linux-kernel, DRI Development, Matthias Brugger, moderated list:ARM/Mediatek SoC support, Yongqiang Niu, CK Hu, Daniel Vetter, Linux ARM Hi, Hsin-Yi: Hsin-Yi Wang <hsinyi@chromium.org> 於 2021年2月2日 週二 下午4:13寫道： > > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > Fix setting to follow hardware datasheet. The original error setting > affects mt8192 display. > Applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, Chun-Kuang. > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > Reviewed-by: CK Hu <ck.hu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > index 6ee2431e6b843..6c86673a835c3 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -65,7 +65,7 @@ void mtk_ccorr_config(struct device *dev, unsigned int w, > { > struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs, > + mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs, > DISP_CCORR_SIZE); > mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, > DISP_CCORR_CFG); > -- > 2.30.0.365.g02bc693789-goog > > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 5/8] drm/mediatek: Fix ccorr size config @ 2021-02-03 16:13 ` Chun-Kuang Hu 0 siblings, 0 replies; 64+ messages in thread From: Chun-Kuang Hu @ 2021-02-03 16:13 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Mark Rutland, DTML, David Airlie, linux-kernel, DRI Development, Matthias Brugger, moderated list:ARM/Mediatek SoC support, Yongqiang Niu, Linux ARM Hi, Hsin-Yi: Hsin-Yi Wang <hsinyi@chromium.org> 於 2021年2月2日 週二 下午4:13寫道： > > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > Fix setting to follow hardware datasheet. The original error setting > affects mt8192 display. > Applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, Chun-Kuang. > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > Reviewed-by: CK Hu <ck.hu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > index 6ee2431e6b843..6c86673a835c3 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -65,7 +65,7 @@ void mtk_ccorr_config(struct device *dev, unsigned int w, > { > struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs, > + mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs, > DISP_CCORR_SIZE); > mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, > DISP_CCORR_CFG); > -- > 2.30.0.365.g02bc693789-goog > > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 5/8] drm/mediatek: Fix ccorr size config @ 2021-02-03 16:13 ` Chun-Kuang Hu 0 siblings, 0 replies; 64+ messages in thread From: Chun-Kuang Hu @ 2021-02-03 16:13 UTC (permalink / raw) To: Hsin-Yi Wang Cc: CK Hu, Philipp Zabel, Matthias Brugger, Mark Rutland, DTML, Yongqiang Niu, David Airlie, linux-kernel, DRI Development, moderated list:ARM/Mediatek SoC support, Daniel Vetter, Linux ARM Hi, Hsin-Yi: Hsin-Yi Wang <hsinyi@chromium.org> 於 2021年2月2日 週二 下午4:13寫道： > > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > Fix setting to follow hardware datasheet. The original error setting > affects mt8192 display. > Applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, Chun-Kuang. > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > Reviewed-by: CK Hu <ck.hu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > index 6ee2431e6b843..6c86673a835c3 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -65,7 +65,7 @@ void mtk_ccorr_config(struct device *dev, unsigned int w, > { > struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs, > + mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs, > DISP_CCORR_SIZE); > mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, > DISP_CCORR_CFG); > -- > 2.30.0.365.g02bc693789-goog > > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 5/8] drm/mediatek: Fix ccorr size config @ 2021-02-03 16:13 ` Chun-Kuang Hu 0 siblings, 0 replies; 64+ messages in thread From: Chun-Kuang Hu @ 2021-02-03 16:13 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Mark Rutland, DTML, Philipp Zabel, David Airlie, linux-kernel, DRI Development, Matthias Brugger, moderated list:ARM/Mediatek SoC support, Yongqiang Niu, CK Hu, Daniel Vetter, Linux ARM Hi, Hsin-Yi: Hsin-Yi Wang <hsinyi@chromium.org> 於 2021年2月2日 週二 下午4:13寫道： > > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > Fix setting to follow hardware datasheet. The original error setting > affects mt8192 display. > Applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, Chun-Kuang. > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > Reviewed-by: CK Hu <ck.hu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > index 6ee2431e6b843..6c86673a835c3 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -65,7 +65,7 @@ void mtk_ccorr_config(struct device *dev, unsigned int w, > { > struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev); > > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &ccorr->cmdq_reg, ccorr->regs, > + mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs, > DISP_CCORR_SIZE); > mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, > DISP_CCORR_CFG); > -- > 2.30.0.365.g02bc693789-goog > > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v6 6/8] drm/mediatek: add matrix_bits private data for ccorr 2021-02-02 8:12 ` Hsin-Yi Wang (?) (?) @ 2021-02-02 8:12 ` Hsin-Yi Wang -1 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> Add matrix_bits and coeffs_precision to ccorr private data: - matrix bits of mt8183 is 10 - matrix bits of mt8192 is 11 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> --- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 27 ++++++++++++++--------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 6c86673a835c3..141cb36b9c07b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -30,7 +30,7 @@ #define DISP_CCORR_COEF_4 0x0090 struct mtk_disp_ccorr_data { - u32 reserved; + u32 matrix_bits; }; /** @@ -85,21 +85,22 @@ void mtk_ccorr_stop(struct device *dev) writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); } -/* Converts a DRM S31.32 value to the HW S1.10 format. */ -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) +/* Converts a DRM S31.32 value to the HW S1.n format. */ +static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n) { u16 r; /* Sign bit. */ - r = in & BIT_ULL(63) ? BIT(11) : 0; + r = in & BIT_ULL(63) ? BIT(n + 1) : 0; if ((in & GENMASK_ULL(62, 33)) > 0) { - /* identity value 0x100000000 -> 0x400, */ + /* identity value 0x100000000 -> 0x400(mt8183), */ + /* identity value 0x100000000 -> 0x800(mt8192), */ /* if bigger this, set it to max 0x7ff. */ - r |= GENMASK(10, 0); + r |= GENMASK(n, 0); } else { - /* take the 11 most important bits. */ - r |= (in >> 22) & GENMASK(10, 0); + /* take the n+1 most important bits. */ + r |= (in >> (32 - n)) & GENMASK(n, 0); } return r; @@ -114,6 +115,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) uint16_t coeffs[9] = { 0 }; int i; struct cmdq_pkt *cmdq_pkt = NULL; + u32 matrix_bits = ccorr->data->matrix_bits; if (!blob) return; @@ -122,7 +124,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) input = ctm->matrix; for (i = 0; i < ARRAY_SIZE(coeffs); i++) - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); + coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits); mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); @@ -199,8 +201,13 @@ static int mtk_disp_ccorr_remove(struct platform_device *pdev) return 0; } +static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { + .matrix_bits = 10, +}; + static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { - { .compatible = "mediatek,mt8183-disp-ccorr"}, + { .compatible = "mediatek,mt8183-disp-ccorr", + .data = &mt8183_ccorr_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); -- 2.30.0.365.g02bc693789-goog _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 6/8] drm/mediatek: add matrix_bits private data for ccorr @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> Add matrix_bits and coeffs_precision to ccorr private data: - matrix bits of mt8183 is 10 - matrix bits of mt8192 is 11 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> --- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 27 ++++++++++++++--------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 6c86673a835c3..141cb36b9c07b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -30,7 +30,7 @@ #define DISP_CCORR_COEF_4 0x0090 struct mtk_disp_ccorr_data { - u32 reserved; + u32 matrix_bits; }; /** @@ -85,21 +85,22 @@ void mtk_ccorr_stop(struct device *dev) writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); } -/* Converts a DRM S31.32 value to the HW S1.10 format. */ -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) +/* Converts a DRM S31.32 value to the HW S1.n format. */ +static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n) { u16 r; /* Sign bit. */ - r = in & BIT_ULL(63) ? BIT(11) : 0; + r = in & BIT_ULL(63) ? BIT(n + 1) : 0; if ((in & GENMASK_ULL(62, 33)) > 0) { - /* identity value 0x100000000 -> 0x400, */ + /* identity value 0x100000000 -> 0x400(mt8183), */ + /* identity value 0x100000000 -> 0x800(mt8192), */ /* if bigger this, set it to max 0x7ff. */ - r |= GENMASK(10, 0); + r |= GENMASK(n, 0); } else { - /* take the 11 most important bits. */ - r |= (in >> 22) & GENMASK(10, 0); + /* take the n+1 most important bits. */ + r |= (in >> (32 - n)) & GENMASK(n, 0); } return r; @@ -114,6 +115,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) uint16_t coeffs[9] = { 0 }; int i; struct cmdq_pkt *cmdq_pkt = NULL; + u32 matrix_bits = ccorr->data->matrix_bits; if (!blob) return; @@ -122,7 +124,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) input = ctm->matrix; for (i = 0; i < ARRAY_SIZE(coeffs); i++) - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); + coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits); mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); @@ -199,8 +201,13 @@ static int mtk_disp_ccorr_remove(struct platform_device *pdev) return 0; } +static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { + .matrix_bits = 10, +}; + static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { - { .compatible = "mediatek,mt8183-disp-ccorr"}, + { .compatible = "mediatek,mt8183-disp-ccorr", + .data = &mt8183_ccorr_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); -- 2.30.0.365.g02bc693789-goog _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 6/8] drm/mediatek: add matrix_bits private data for ccorr @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu From: Yongqiang Niu <yongqiang.niu@mediatek.com> Add matrix_bits and coeffs_precision to ccorr private data: - matrix bits of mt8183 is 10 - matrix bits of mt8192 is 11 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> --- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 27 ++++++++++++++--------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 6c86673a835c3..141cb36b9c07b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -30,7 +30,7 @@ #define DISP_CCORR_COEF_4 0x0090 struct mtk_disp_ccorr_data { - u32 reserved; + u32 matrix_bits; }; /** @@ -85,21 +85,22 @@ void mtk_ccorr_stop(struct device *dev) writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); } -/* Converts a DRM S31.32 value to the HW S1.10 format. */ -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) +/* Converts a DRM S31.32 value to the HW S1.n format. */ +static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n) { u16 r; /* Sign bit. */ - r = in & BIT_ULL(63) ? BIT(11) : 0; + r = in & BIT_ULL(63) ? BIT(n + 1) : 0; if ((in & GENMASK_ULL(62, 33)) > 0) { - /* identity value 0x100000000 -> 0x400, */ + /* identity value 0x100000000 -> 0x400(mt8183), */ + /* identity value 0x100000000 -> 0x800(mt8192), */ /* if bigger this, set it to max 0x7ff. */ - r |= GENMASK(10, 0); + r |= GENMASK(n, 0); } else { - /* take the 11 most important bits. */ - r |= (in >> 22) & GENMASK(10, 0); + /* take the n+1 most important bits. */ + r |= (in >> (32 - n)) & GENMASK(n, 0); } return r; @@ -114,6 +115,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) uint16_t coeffs[9] = { 0 }; int i; struct cmdq_pkt *cmdq_pkt = NULL; + u32 matrix_bits = ccorr->data->matrix_bits; if (!blob) return; @@ -122,7 +124,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) input = ctm->matrix; for (i = 0; i < ARRAY_SIZE(coeffs); i++) - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); + coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits); mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); @@ -199,8 +201,13 @@ static int mtk_disp_ccorr_remove(struct platform_device *pdev) return 0; } +static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { + .matrix_bits = 10, +}; + static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { - { .compatible = "mediatek,mt8183-disp-ccorr"}, + { .compatible = "mediatek,mt8183-disp-ccorr", + .data = &mt8183_ccorr_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); -- 2.30.0.365.g02bc693789-goog ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 6/8] drm/mediatek: add matrix_bits private data for ccorr @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> Add matrix_bits and coeffs_precision to ccorr private data: - matrix bits of mt8183 is 10 - matrix bits of mt8192 is 11 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> --- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 27 ++++++++++++++--------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 6c86673a835c3..141cb36b9c07b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -30,7 +30,7 @@ #define DISP_CCORR_COEF_4 0x0090 struct mtk_disp_ccorr_data { - u32 reserved; + u32 matrix_bits; }; /** @@ -85,21 +85,22 @@ void mtk_ccorr_stop(struct device *dev) writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); } -/* Converts a DRM S31.32 value to the HW S1.10 format. */ -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) +/* Converts a DRM S31.32 value to the HW S1.n format. */ +static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n) { u16 r; /* Sign bit. */ - r = in & BIT_ULL(63) ? BIT(11) : 0; + r = in & BIT_ULL(63) ? BIT(n + 1) : 0; if ((in & GENMASK_ULL(62, 33)) > 0) { - /* identity value 0x100000000 -> 0x400, */ + /* identity value 0x100000000 -> 0x400(mt8183), */ + /* identity value 0x100000000 -> 0x800(mt8192), */ /* if bigger this, set it to max 0x7ff. */ - r |= GENMASK(10, 0); + r |= GENMASK(n, 0); } else { - /* take the 11 most important bits. */ - r |= (in >> 22) & GENMASK(10, 0); + /* take the n+1 most important bits. */ + r |= (in >> (32 - n)) & GENMASK(n, 0); } return r; @@ -114,6 +115,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) uint16_t coeffs[9] = { 0 }; int i; struct cmdq_pkt *cmdq_pkt = NULL; + u32 matrix_bits = ccorr->data->matrix_bits; if (!blob) return; @@ -122,7 +124,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) input = ctm->matrix; for (i = 0; i < ARRAY_SIZE(coeffs); i++) - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); + coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits); mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); @@ -199,8 +201,13 @@ static int mtk_disp_ccorr_remove(struct platform_device *pdev) return 0; } +static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { + .matrix_bits = 10, +}; + static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { - { .compatible = "mediatek,mt8183-disp-ccorr"}, + { .compatible = "mediatek,mt8183-disp-ccorr", + .data = &mt8183_ccorr_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); -- 2.30.0.365.g02bc693789-goog _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 64+ messages in thread
* Re: [PATCH v6 6/8] drm/mediatek: add matrix_bits private data for ccorr 2021-02-02 8:12 ` Hsin-Yi Wang (?) (?) @ 2021-02-02 9:11 ` CK Hu -1 siblings, 0 replies; 64+ messages in thread From: CK Hu @ 2021-02-02 9:11 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie, linux-kernel, dri-devel, Yongqiang Niu, linux-mediatek, Daniel Vetter, Matthias Brugger, linux-arm-kernel Hi, Hsin-Yi: On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > Add matrix_bits and coeffs_precision to ccorr private data: > - matrix bits of mt8183 is 10 > - matrix bits of mt8192 is 11 > Reviewed-by: CK Hu <ck.hu@mediatek.com> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > --- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 27 ++++++++++++++--------- > 1 file changed, 17 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > index 6c86673a835c3..141cb36b9c07b 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -30,7 +30,7 @@ > #define DISP_CCORR_COEF_4 0x0090 > > struct mtk_disp_ccorr_data { > - u32 reserved; > + u32 matrix_bits; > }; > > /** > @@ -85,21 +85,22 @@ void mtk_ccorr_stop(struct device *dev) > writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); > } > > -/* Converts a DRM S31.32 value to the HW S1.10 format. */ > -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) > +/* Converts a DRM S31.32 value to the HW S1.n format. */ > +static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n) > { > u16 r; > > /* Sign bit. */ > - r = in & BIT_ULL(63) ? BIT(11) : 0; > + r = in & BIT_ULL(63) ? BIT(n + 1) : 0; > > if ((in & GENMASK_ULL(62, 33)) > 0) { > - /* identity value 0x100000000 -> 0x400, */ > + /* identity value 0x100000000 -> 0x400(mt8183), */ > + /* identity value 0x100000000 -> 0x800(mt8192), */ > /* if bigger this, set it to max 0x7ff. */ > - r |= GENMASK(10, 0); > + r |= GENMASK(n, 0); > } else { > - /* take the 11 most important bits. */ > - r |= (in >> 22) & GENMASK(10, 0); > + /* take the n+1 most important bits. */ > + r |= (in >> (32 - n)) & GENMASK(n, 0); > } > > return r; > @@ -114,6 +115,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > uint16_t coeffs[9] = { 0 }; > int i; > struct cmdq_pkt *cmdq_pkt = NULL; > + u32 matrix_bits = ccorr->data->matrix_bits; > > if (!blob) > return; > @@ -122,7 +124,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > input = ctm->matrix; > > for (i = 0; i < ARRAY_SIZE(coeffs); i++) > - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > + coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits); > > mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); > @@ -199,8 +201,13 @@ static int mtk_disp_ccorr_remove(struct platform_device *pdev) > return 0; > } > > +static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { > + .matrix_bits = 10, > +}; > + > static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { > - { .compatible = "mediatek,mt8183-disp-ccorr"}, > + { .compatible = "mediatek,mt8183-disp-ccorr", > + .data = &mt8183_ccorr_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 6/8] drm/mediatek: add matrix_bits private data for ccorr @ 2021-02-02 9:11 ` CK Hu 0 siblings, 0 replies; 64+ messages in thread From: CK Hu @ 2021-02-02 9:11 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, Yongqiang Niu, linux-mediatek, Matthias Brugger, linux-arm-kernel Hi, Hsin-Yi: On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > Add matrix_bits and coeffs_precision to ccorr private data: > - matrix bits of mt8183 is 10 > - matrix bits of mt8192 is 11 > Reviewed-by: CK Hu <ck.hu@mediatek.com> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > --- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 27 ++++++++++++++--------- > 1 file changed, 17 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > index 6c86673a835c3..141cb36b9c07b 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -30,7 +30,7 @@ > #define DISP_CCORR_COEF_4 0x0090 > > struct mtk_disp_ccorr_data { > - u32 reserved; > + u32 matrix_bits; > }; > > /** > @@ -85,21 +85,22 @@ void mtk_ccorr_stop(struct device *dev) > writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); > } > > -/* Converts a DRM S31.32 value to the HW S1.10 format. */ > -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) > +/* Converts a DRM S31.32 value to the HW S1.n format. */ > +static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n) > { > u16 r; > > /* Sign bit. */ > - r = in & BIT_ULL(63) ? BIT(11) : 0; > + r = in & BIT_ULL(63) ? BIT(n + 1) : 0; > > if ((in & GENMASK_ULL(62, 33)) > 0) { > - /* identity value 0x100000000 -> 0x400, */ > + /* identity value 0x100000000 -> 0x400(mt8183), */ > + /* identity value 0x100000000 -> 0x800(mt8192), */ > /* if bigger this, set it to max 0x7ff. */ > - r |= GENMASK(10, 0); > + r |= GENMASK(n, 0); > } else { > - /* take the 11 most important bits. */ > - r |= (in >> 22) & GENMASK(10, 0); > + /* take the n+1 most important bits. */ > + r |= (in >> (32 - n)) & GENMASK(n, 0); > } > > return r; > @@ -114,6 +115,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > uint16_t coeffs[9] = { 0 }; > int i; > struct cmdq_pkt *cmdq_pkt = NULL; > + u32 matrix_bits = ccorr->data->matrix_bits; > > if (!blob) > return; > @@ -122,7 +124,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > input = ctm->matrix; > > for (i = 0; i < ARRAY_SIZE(coeffs); i++) > - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > + coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits); > > mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); > @@ -199,8 +201,13 @@ static int mtk_disp_ccorr_remove(struct platform_device *pdev) > return 0; > } > > +static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { > + .matrix_bits = 10, > +}; > + > static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { > - { .compatible = "mediatek,mt8183-disp-ccorr"}, > + { .compatible = "mediatek,mt8183-disp-ccorr", > + .data = &mt8183_ccorr_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 6/8] drm/mediatek: add matrix_bits private data for ccorr @ 2021-02-02 9:11 ` CK Hu 0 siblings, 0 replies; 64+ messages in thread From: CK Hu @ 2021-02-02 9:11 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Philipp Zabel, Matthias Brugger, David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu Hi, Hsin-Yi: On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > Add matrix_bits and coeffs_precision to ccorr private data: > - matrix bits of mt8183 is 10 > - matrix bits of mt8192 is 11 > Reviewed-by: CK Hu <ck.hu@mediatek.com> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > --- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 27 ++++++++++++++--------- > 1 file changed, 17 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > index 6c86673a835c3..141cb36b9c07b 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -30,7 +30,7 @@ > #define DISP_CCORR_COEF_4 0x0090 > > struct mtk_disp_ccorr_data { > - u32 reserved; > + u32 matrix_bits; > }; > > /** > @@ -85,21 +85,22 @@ void mtk_ccorr_stop(struct device *dev) > writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); > } > > -/* Converts a DRM S31.32 value to the HW S1.10 format. */ > -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) > +/* Converts a DRM S31.32 value to the HW S1.n format. */ > +static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n) > { > u16 r; > > /* Sign bit. */ > - r = in & BIT_ULL(63) ? BIT(11) : 0; > + r = in & BIT_ULL(63) ? BIT(n + 1) : 0; > > if ((in & GENMASK_ULL(62, 33)) > 0) { > - /* identity value 0x100000000 -> 0x400, */ > + /* identity value 0x100000000 -> 0x400(mt8183), */ > + /* identity value 0x100000000 -> 0x800(mt8192), */ > /* if bigger this, set it to max 0x7ff. */ > - r |= GENMASK(10, 0); > + r |= GENMASK(n, 0); > } else { > - /* take the 11 most important bits. */ > - r |= (in >> 22) & GENMASK(10, 0); > + /* take the n+1 most important bits. */ > + r |= (in >> (32 - n)) & GENMASK(n, 0); > } > > return r; > @@ -114,6 +115,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > uint16_t coeffs[9] = { 0 }; > int i; > struct cmdq_pkt *cmdq_pkt = NULL; > + u32 matrix_bits = ccorr->data->matrix_bits; > > if (!blob) > return; > @@ -122,7 +124,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > input = ctm->matrix; > > for (i = 0; i < ARRAY_SIZE(coeffs); i++) > - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > + coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits); > > mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); > @@ -199,8 +201,13 @@ static int mtk_disp_ccorr_remove(struct platform_device *pdev) > return 0; > } > > +static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { > + .matrix_bits = 10, > +}; > + > static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { > - { .compatible = "mediatek,mt8183-disp-ccorr"}, > + { .compatible = "mediatek,mt8183-disp-ccorr", > + .data = &mt8183_ccorr_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 6/8] drm/mediatek: add matrix_bits private data for ccorr @ 2021-02-02 9:11 ` CK Hu 0 siblings, 0 replies; 64+ messages in thread From: CK Hu @ 2021-02-02 9:11 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie, linux-kernel, dri-devel, Yongqiang Niu, linux-mediatek, Daniel Vetter, Matthias Brugger, linux-arm-kernel Hi, Hsin-Yi: On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > Add matrix_bits and coeffs_precision to ccorr private data: > - matrix bits of mt8183 is 10 > - matrix bits of mt8192 is 11 > Reviewed-by: CK Hu <ck.hu@mediatek.com> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > --- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 27 ++++++++++++++--------- > 1 file changed, 17 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > index 6c86673a835c3..141cb36b9c07b 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -30,7 +30,7 @@ > #define DISP_CCORR_COEF_4 0x0090 > > struct mtk_disp_ccorr_data { > - u32 reserved; > + u32 matrix_bits; > }; > > /** > @@ -85,21 +85,22 @@ void mtk_ccorr_stop(struct device *dev) > writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); > } > > -/* Converts a DRM S31.32 value to the HW S1.10 format. */ > -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) > +/* Converts a DRM S31.32 value to the HW S1.n format. */ > +static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n) > { > u16 r; > > /* Sign bit. */ > - r = in & BIT_ULL(63) ? BIT(11) : 0; > + r = in & BIT_ULL(63) ? BIT(n + 1) : 0; > > if ((in & GENMASK_ULL(62, 33)) > 0) { > - /* identity value 0x100000000 -> 0x400, */ > + /* identity value 0x100000000 -> 0x400(mt8183), */ > + /* identity value 0x100000000 -> 0x800(mt8192), */ > /* if bigger this, set it to max 0x7ff. */ > - r |= GENMASK(10, 0); > + r |= GENMASK(n, 0); > } else { > - /* take the 11 most important bits. */ > - r |= (in >> 22) & GENMASK(10, 0); > + /* take the n+1 most important bits. */ > + r |= (in >> (32 - n)) & GENMASK(n, 0); > } > > return r; > @@ -114,6 +115,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > uint16_t coeffs[9] = { 0 }; > int i; > struct cmdq_pkt *cmdq_pkt = NULL; > + u32 matrix_bits = ccorr->data->matrix_bits; > > if (!blob) > return; > @@ -122,7 +124,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > input = ctm->matrix; > > for (i = 0; i < ARRAY_SIZE(coeffs); i++) > - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > + coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits); > > mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); > @@ -199,8 +201,13 @@ static int mtk_disp_ccorr_remove(struct platform_device *pdev) > return 0; > } > > +static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { > + .matrix_bits = 10, > +}; > + > static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { > - { .compatible = "mediatek,mt8183-disp-ccorr"}, > + { .compatible = "mediatek,mt8183-disp-ccorr", > + .data = &mt8183_ccorr_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 6/8] drm/mediatek: add matrix_bits private data for ccorr 2021-02-02 8:12 ` Hsin-Yi Wang (?) (?) @ 2021-02-03 16:14 ` Chun-Kuang Hu -1 siblings, 0 replies; 64+ messages in thread From: Chun-Kuang Hu @ 2021-02-03 16:14 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Mark Rutland, DTML, Philipp Zabel, David Airlie, linux-kernel, DRI Development, Matthias Brugger, moderated list:ARM/Mediatek SoC support, Yongqiang Niu, CK Hu, Daniel Vetter, Linux ARM Hi, Hsin-Yi: Hsin-Yi Wang <hsinyi@chromium.org> 於 2021年2月2日 週二 下午4:14寫道： > > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > Add matrix_bits and coeffs_precision to ccorr private data: > - matrix bits of mt8183 is 10 > - matrix bits of mt8192 is 11 Applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, Chun-Kuang. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > --- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 27 ++++++++++++++--------- > 1 file changed, 17 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > index 6c86673a835c3..141cb36b9c07b 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -30,7 +30,7 @@ > #define DISP_CCORR_COEF_4 0x0090 > > struct mtk_disp_ccorr_data { > - u32 reserved; > + u32 matrix_bits; > }; > > /** > @@ -85,21 +85,22 @@ void mtk_ccorr_stop(struct device *dev) > writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); > } > > -/* Converts a DRM S31.32 value to the HW S1.10 format. */ > -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) > +/* Converts a DRM S31.32 value to the HW S1.n format. */ > +static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n) > { > u16 r; > > /* Sign bit. */ > - r = in & BIT_ULL(63) ? BIT(11) : 0; > + r = in & BIT_ULL(63) ? BIT(n + 1) : 0; > > if ((in & GENMASK_ULL(62, 33)) > 0) { > - /* identity value 0x100000000 -> 0x400, */ > + /* identity value 0x100000000 -> 0x400(mt8183), */ > + /* identity value 0x100000000 -> 0x800(mt8192), */ > /* if bigger this, set it to max 0x7ff. */ > - r |= GENMASK(10, 0); > + r |= GENMASK(n, 0); > } else { > - /* take the 11 most important bits. */ > - r |= (in >> 22) & GENMASK(10, 0); > + /* take the n+1 most important bits. */ > + r |= (in >> (32 - n)) & GENMASK(n, 0); > } > > return r; > @@ -114,6 +115,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > uint16_t coeffs[9] = { 0 }; > int i; > struct cmdq_pkt *cmdq_pkt = NULL; > + u32 matrix_bits = ccorr->data->matrix_bits; > > if (!blob) > return; > @@ -122,7 +124,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > input = ctm->matrix; > > for (i = 0; i < ARRAY_SIZE(coeffs); i++) > - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > + coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits); > > mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); > @@ -199,8 +201,13 @@ static int mtk_disp_ccorr_remove(struct platform_device *pdev) > return 0; > } > > +static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { > + .matrix_bits = 10, > +}; > + > static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { > - { .compatible = "mediatek,mt8183-disp-ccorr"}, > + { .compatible = "mediatek,mt8183-disp-ccorr", > + .data = &mt8183_ccorr_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); > -- > 2.30.0.365.g02bc693789-goog > > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 6/8] drm/mediatek: add matrix_bits private data for ccorr @ 2021-02-03 16:14 ` Chun-Kuang Hu 0 siblings, 0 replies; 64+ messages in thread From: Chun-Kuang Hu @ 2021-02-03 16:14 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Mark Rutland, DTML, David Airlie, linux-kernel, DRI Development, Matthias Brugger, moderated list:ARM/Mediatek SoC support, Yongqiang Niu, Linux ARM Hi, Hsin-Yi: Hsin-Yi Wang <hsinyi@chromium.org> 於 2021年2月2日 週二 下午4:14寫道： > > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > Add matrix_bits and coeffs_precision to ccorr private data: > - matrix bits of mt8183 is 10 > - matrix bits of mt8192 is 11 Applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, Chun-Kuang. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > --- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 27 ++++++++++++++--------- > 1 file changed, 17 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > index 6c86673a835c3..141cb36b9c07b 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -30,7 +30,7 @@ > #define DISP_CCORR_COEF_4 0x0090 > > struct mtk_disp_ccorr_data { > - u32 reserved; > + u32 matrix_bits; > }; > > /** > @@ -85,21 +85,22 @@ void mtk_ccorr_stop(struct device *dev) > writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); > } > > -/* Converts a DRM S31.32 value to the HW S1.10 format. */ > -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) > +/* Converts a DRM S31.32 value to the HW S1.n format. */ > +static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n) > { > u16 r; > > /* Sign bit. */ > - r = in & BIT_ULL(63) ? BIT(11) : 0; > + r = in & BIT_ULL(63) ? BIT(n + 1) : 0; > > if ((in & GENMASK_ULL(62, 33)) > 0) { > - /* identity value 0x100000000 -> 0x400, */ > + /* identity value 0x100000000 -> 0x400(mt8183), */ > + /* identity value 0x100000000 -> 0x800(mt8192), */ > /* if bigger this, set it to max 0x7ff. */ > - r |= GENMASK(10, 0); > + r |= GENMASK(n, 0); > } else { > - /* take the 11 most important bits. */ > - r |= (in >> 22) & GENMASK(10, 0); > + /* take the n+1 most important bits. */ > + r |= (in >> (32 - n)) & GENMASK(n, 0); > } > > return r; > @@ -114,6 +115,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > uint16_t coeffs[9] = { 0 }; > int i; > struct cmdq_pkt *cmdq_pkt = NULL; > + u32 matrix_bits = ccorr->data->matrix_bits; > > if (!blob) > return; > @@ -122,7 +124,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > input = ctm->matrix; > > for (i = 0; i < ARRAY_SIZE(coeffs); i++) > - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > + coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits); > > mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); > @@ -199,8 +201,13 @@ static int mtk_disp_ccorr_remove(struct platform_device *pdev) > return 0; > } > > +static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { > + .matrix_bits = 10, > +}; > + > static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { > - { .compatible = "mediatek,mt8183-disp-ccorr"}, > + { .compatible = "mediatek,mt8183-disp-ccorr", > + .data = &mt8183_ccorr_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); > -- > 2.30.0.365.g02bc693789-goog > > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 6/8] drm/mediatek: add matrix_bits private data for ccorr @ 2021-02-03 16:14 ` Chun-Kuang Hu 0 siblings, 0 replies; 64+ messages in thread From: Chun-Kuang Hu @ 2021-02-03 16:14 UTC (permalink / raw) To: Hsin-Yi Wang Cc: CK Hu, Philipp Zabel, Matthias Brugger, Mark Rutland, DTML, Yongqiang Niu, David Airlie, linux-kernel, DRI Development, moderated list:ARM/Mediatek SoC support, Daniel Vetter, Linux ARM Hi, Hsin-Yi: Hsin-Yi Wang <hsinyi@chromium.org> 於 2021年2月2日 週二 下午4:14寫道： > > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > Add matrix_bits and coeffs_precision to ccorr private data: > - matrix bits of mt8183 is 10 > - matrix bits of mt8192 is 11 Applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, Chun-Kuang. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > --- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 27 ++++++++++++++--------- > 1 file changed, 17 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > index 6c86673a835c3..141cb36b9c07b 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -30,7 +30,7 @@ > #define DISP_CCORR_COEF_4 0x0090 > > struct mtk_disp_ccorr_data { > - u32 reserved; > + u32 matrix_bits; > }; > > /** > @@ -85,21 +85,22 @@ void mtk_ccorr_stop(struct device *dev) > writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); > } > > -/* Converts a DRM S31.32 value to the HW S1.10 format. */ > -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) > +/* Converts a DRM S31.32 value to the HW S1.n format. */ > +static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n) > { > u16 r; > > /* Sign bit. */ > - r = in & BIT_ULL(63) ? BIT(11) : 0; > + r = in & BIT_ULL(63) ? BIT(n + 1) : 0; > > if ((in & GENMASK_ULL(62, 33)) > 0) { > - /* identity value 0x100000000 -> 0x400, */ > + /* identity value 0x100000000 -> 0x400(mt8183), */ > + /* identity value 0x100000000 -> 0x800(mt8192), */ > /* if bigger this, set it to max 0x7ff. */ > - r |= GENMASK(10, 0); > + r |= GENMASK(n, 0); > } else { > - /* take the 11 most important bits. */ > - r |= (in >> 22) & GENMASK(10, 0); > + /* take the n+1 most important bits. */ > + r |= (in >> (32 - n)) & GENMASK(n, 0); > } > > return r; > @@ -114,6 +115,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > uint16_t coeffs[9] = { 0 }; > int i; > struct cmdq_pkt *cmdq_pkt = NULL; > + u32 matrix_bits = ccorr->data->matrix_bits; > > if (!blob) > return; > @@ -122,7 +124,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > input = ctm->matrix; > > for (i = 0; i < ARRAY_SIZE(coeffs); i++) > - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > + coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits); > > mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); > @@ -199,8 +201,13 @@ static int mtk_disp_ccorr_remove(struct platform_device *pdev) > return 0; > } > > +static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { > + .matrix_bits = 10, > +}; > + > static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { > - { .compatible = "mediatek,mt8183-disp-ccorr"}, > + { .compatible = "mediatek,mt8183-disp-ccorr", > + .data = &mt8183_ccorr_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); > -- > 2.30.0.365.g02bc693789-goog > > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 6/8] drm/mediatek: add matrix_bits private data for ccorr @ 2021-02-03 16:14 ` Chun-Kuang Hu 0 siblings, 0 replies; 64+ messages in thread From: Chun-Kuang Hu @ 2021-02-03 16:14 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Mark Rutland, DTML, Philipp Zabel, David Airlie, linux-kernel, DRI Development, Matthias Brugger, moderated list:ARM/Mediatek SoC support, Yongqiang Niu, CK Hu, Daniel Vetter, Linux ARM Hi, Hsin-Yi: Hsin-Yi Wang <hsinyi@chromium.org> 於 2021年2月2日 週二 下午4:14寫道： > > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > Add matrix_bits and coeffs_precision to ccorr private data: > - matrix bits of mt8183 is 10 > - matrix bits of mt8192 is 11 Applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, Chun-Kuang. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > --- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 27 ++++++++++++++--------- > 1 file changed, 17 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > index 6c86673a835c3..141cb36b9c07b 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -30,7 +30,7 @@ > #define DISP_CCORR_COEF_4 0x0090 > > struct mtk_disp_ccorr_data { > - u32 reserved; > + u32 matrix_bits; > }; > > /** > @@ -85,21 +85,22 @@ void mtk_ccorr_stop(struct device *dev) > writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN); > } > > -/* Converts a DRM S31.32 value to the HW S1.10 format. */ > -static u16 mtk_ctm_s31_32_to_s1_10(u64 in) > +/* Converts a DRM S31.32 value to the HW S1.n format. */ > +static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n) > { > u16 r; > > /* Sign bit. */ > - r = in & BIT_ULL(63) ? BIT(11) : 0; > + r = in & BIT_ULL(63) ? BIT(n + 1) : 0; > > if ((in & GENMASK_ULL(62, 33)) > 0) { > - /* identity value 0x100000000 -> 0x400, */ > + /* identity value 0x100000000 -> 0x400(mt8183), */ > + /* identity value 0x100000000 -> 0x800(mt8192), */ > /* if bigger this, set it to max 0x7ff. */ > - r |= GENMASK(10, 0); > + r |= GENMASK(n, 0); > } else { > - /* take the 11 most important bits. */ > - r |= (in >> 22) & GENMASK(10, 0); > + /* take the n+1 most important bits. */ > + r |= (in >> (32 - n)) & GENMASK(n, 0); > } > > return r; > @@ -114,6 +115,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > uint16_t coeffs[9] = { 0 }; > int i; > struct cmdq_pkt *cmdq_pkt = NULL; > + u32 matrix_bits = ccorr->data->matrix_bits; > > if (!blob) > return; > @@ -122,7 +124,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) > input = ctm->matrix; > > for (i = 0; i < ARRAY_SIZE(coeffs); i++) > - coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); > + coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits); > > mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], > &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); > @@ -199,8 +201,13 @@ static int mtk_disp_ccorr_remove(struct platform_device *pdev) > return 0; > } > > +static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { > + .matrix_bits = 10, > +}; > + > static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { > - { .compatible = "mediatek,mt8183-disp-ccorr"}, > + { .compatible = "mediatek,mt8183-disp-ccorr", > + .data = &mt8183_ccorr_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); > -- > 2.30.0.365.g02bc693789-goog > > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 64+ messages in thread
* [PATCH v6 7/8] soc: mediatek: add mtk mutex support for MT8192 2021-02-02 8:12 ` Hsin-Yi Wang (?) (?) @ 2021-02-02 8:12 ` Hsin-Yi Wang -1 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> Add mtk mutex support for MT8192 SoC. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> --- drivers/soc/mediatek/mtk-mutex.c | 35 ++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 718a41beb6afb..dfd9806d5a001 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -39,6 +39,18 @@ #define MT8167_MUTEX_MOD_DISP_DITHER 15 #define MT8167_MUTEX_MOD_DISP_UFOE 16 +#define MT8192_MUTEX_MOD_DISP_OVL0 0 +#define MT8192_MUTEX_MOD_DISP_OVL0_2L 1 +#define MT8192_MUTEX_MOD_DISP_RDMA0 2 +#define MT8192_MUTEX_MOD_DISP_COLOR0 4 +#define MT8192_MUTEX_MOD_DISP_CCORR0 5 +#define MT8192_MUTEX_MOD_DISP_AAL0 6 +#define MT8192_MUTEX_MOD_DISP_GAMMA0 7 +#define MT8192_MUTEX_MOD_DISP_POSTMASK0 8 +#define MT8192_MUTEX_MOD_DISP_DITHER0 9 +#define MT8192_MUTEX_MOD_DISP_OVL2_2L 16 +#define MT8192_MUTEX_MOD_DISP_RDMA4 17 + #define MT8183_MUTEX_MOD_DISP_RDMA0 0 #define MT8183_MUTEX_MOD_DISP_RDMA1 1 #define MT8183_MUTEX_MOD_DISP_OVL0 9 @@ -214,6 +226,20 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, }; +static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0, + [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0, + [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0, + [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0, + [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L, + [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L, + [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4, +}; + static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, @@ -275,6 +301,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = { .no_clk = true, }; +static const struct mtk_mutex_data mt8192_mutex_driver_data = { + .mutex_mod = mt8192_mutex_mod, + .mutex_sof = mt8183_mutex_sof, + .mutex_mod_reg = MT8183_MUTEX0_MOD0, + .mutex_sof_reg = MT8183_MUTEX0_SOF0, +}; + struct mtk_mutex *mtk_mutex_get(struct device *dev) { struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); @@ -507,6 +540,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { .data = &mt8173_mutex_driver_data}, { .compatible = "mediatek,mt8183-disp-mutex", .data = &mt8183_mutex_driver_data}, + { .compatible = "mediatek,mt8192-disp-mutex", + .data = &mt8192_mutex_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); -- 2.30.0.365.g02bc693789-goog _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 7/8] soc: mediatek: add mtk mutex support for MT8192 @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> Add mtk mutex support for MT8192 SoC. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> --- drivers/soc/mediatek/mtk-mutex.c | 35 ++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 718a41beb6afb..dfd9806d5a001 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -39,6 +39,18 @@ #define MT8167_MUTEX_MOD_DISP_DITHER 15 #define MT8167_MUTEX_MOD_DISP_UFOE 16 +#define MT8192_MUTEX_MOD_DISP_OVL0 0 +#define MT8192_MUTEX_MOD_DISP_OVL0_2L 1 +#define MT8192_MUTEX_MOD_DISP_RDMA0 2 +#define MT8192_MUTEX_MOD_DISP_COLOR0 4 +#define MT8192_MUTEX_MOD_DISP_CCORR0 5 +#define MT8192_MUTEX_MOD_DISP_AAL0 6 +#define MT8192_MUTEX_MOD_DISP_GAMMA0 7 +#define MT8192_MUTEX_MOD_DISP_POSTMASK0 8 +#define MT8192_MUTEX_MOD_DISP_DITHER0 9 +#define MT8192_MUTEX_MOD_DISP_OVL2_2L 16 +#define MT8192_MUTEX_MOD_DISP_RDMA4 17 + #define MT8183_MUTEX_MOD_DISP_RDMA0 0 #define MT8183_MUTEX_MOD_DISP_RDMA1 1 #define MT8183_MUTEX_MOD_DISP_OVL0 9 @@ -214,6 +226,20 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, }; +static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0, + [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0, + [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0, + [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0, + [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L, + [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L, + [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4, +}; + static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, @@ -275,6 +301,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = { .no_clk = true, }; +static const struct mtk_mutex_data mt8192_mutex_driver_data = { + .mutex_mod = mt8192_mutex_mod, + .mutex_sof = mt8183_mutex_sof, + .mutex_mod_reg = MT8183_MUTEX0_MOD0, + .mutex_sof_reg = MT8183_MUTEX0_SOF0, +}; + struct mtk_mutex *mtk_mutex_get(struct device *dev) { struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); @@ -507,6 +540,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { .data = &mt8173_mutex_driver_data}, { .compatible = "mediatek,mt8183-disp-mutex", .data = &mt8183_mutex_driver_data}, + { .compatible = "mediatek,mt8192-disp-mutex", + .data = &mt8192_mutex_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); -- 2.30.0.365.g02bc693789-goog _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 7/8] soc: mediatek: add mtk mutex support for MT8192 @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu From: Yongqiang Niu <yongqiang.niu@mediatek.com> Add mtk mutex support for MT8192 SoC. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> --- drivers/soc/mediatek/mtk-mutex.c | 35 ++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 718a41beb6afb..dfd9806d5a001 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -39,6 +39,18 @@ #define MT8167_MUTEX_MOD_DISP_DITHER 15 #define MT8167_MUTEX_MOD_DISP_UFOE 16 +#define MT8192_MUTEX_MOD_DISP_OVL0 0 +#define MT8192_MUTEX_MOD_DISP_OVL0_2L 1 +#define MT8192_MUTEX_MOD_DISP_RDMA0 2 +#define MT8192_MUTEX_MOD_DISP_COLOR0 4 +#define MT8192_MUTEX_MOD_DISP_CCORR0 5 +#define MT8192_MUTEX_MOD_DISP_AAL0 6 +#define MT8192_MUTEX_MOD_DISP_GAMMA0 7 +#define MT8192_MUTEX_MOD_DISP_POSTMASK0 8 +#define MT8192_MUTEX_MOD_DISP_DITHER0 9 +#define MT8192_MUTEX_MOD_DISP_OVL2_2L 16 +#define MT8192_MUTEX_MOD_DISP_RDMA4 17 + #define MT8183_MUTEX_MOD_DISP_RDMA0 0 #define MT8183_MUTEX_MOD_DISP_RDMA1 1 #define MT8183_MUTEX_MOD_DISP_OVL0 9 @@ -214,6 +226,20 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, }; +static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0, + [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0, + [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0, + [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0, + [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L, + [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L, + [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4, +}; + static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, @@ -275,6 +301,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = { .no_clk = true, }; +static const struct mtk_mutex_data mt8192_mutex_driver_data = { + .mutex_mod = mt8192_mutex_mod, + .mutex_sof = mt8183_mutex_sof, + .mutex_mod_reg = MT8183_MUTEX0_MOD0, + .mutex_sof_reg = MT8183_MUTEX0_SOF0, +}; + struct mtk_mutex *mtk_mutex_get(struct device *dev) { struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); @@ -507,6 +540,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { .data = &mt8173_mutex_driver_data}, { .compatible = "mediatek,mt8183-disp-mutex", .data = &mt8183_mutex_driver_data}, + { .compatible = "mediatek,mt8192-disp-mutex", + .data = &mt8192_mutex_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); -- 2.30.0.365.g02bc693789-goog ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 7/8] soc: mediatek: add mtk mutex support for MT8192 @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> Add mtk mutex support for MT8192 SoC. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> --- drivers/soc/mediatek/mtk-mutex.c | 35 ++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 718a41beb6afb..dfd9806d5a001 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -39,6 +39,18 @@ #define MT8167_MUTEX_MOD_DISP_DITHER 15 #define MT8167_MUTEX_MOD_DISP_UFOE 16 +#define MT8192_MUTEX_MOD_DISP_OVL0 0 +#define MT8192_MUTEX_MOD_DISP_OVL0_2L 1 +#define MT8192_MUTEX_MOD_DISP_RDMA0 2 +#define MT8192_MUTEX_MOD_DISP_COLOR0 4 +#define MT8192_MUTEX_MOD_DISP_CCORR0 5 +#define MT8192_MUTEX_MOD_DISP_AAL0 6 +#define MT8192_MUTEX_MOD_DISP_GAMMA0 7 +#define MT8192_MUTEX_MOD_DISP_POSTMASK0 8 +#define MT8192_MUTEX_MOD_DISP_DITHER0 9 +#define MT8192_MUTEX_MOD_DISP_OVL2_2L 16 +#define MT8192_MUTEX_MOD_DISP_RDMA4 17 + #define MT8183_MUTEX_MOD_DISP_RDMA0 0 #define MT8183_MUTEX_MOD_DISP_RDMA1 1 #define MT8183_MUTEX_MOD_DISP_OVL0 9 @@ -214,6 +226,20 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, }; +static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0, + [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0, + [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0, + [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0, + [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L, + [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L, + [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4, +}; + static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, @@ -275,6 +301,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = { .no_clk = true, }; +static const struct mtk_mutex_data mt8192_mutex_driver_data = { + .mutex_mod = mt8192_mutex_mod, + .mutex_sof = mt8183_mutex_sof, + .mutex_mod_reg = MT8183_MUTEX0_MOD0, + .mutex_sof_reg = MT8183_MUTEX0_SOF0, +}; + struct mtk_mutex *mtk_mutex_get(struct device *dev) { struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); @@ -507,6 +540,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { .data = &mt8173_mutex_driver_data}, { .compatible = "mediatek,mt8183-disp-mutex", .data = &mt8183_mutex_driver_data}, + { .compatible = "mediatek,mt8192-disp-mutex", + .data = &mt8192_mutex_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); -- 2.30.0.365.g02bc693789-goog _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 8/8] drm/mediatek: add support for mediatek SOC MT8192 2021-02-02 8:12 ` Hsin-Yi Wang (?) (?) @ 2021-02-02 8:12 ` Hsin-Yi Wang -1 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> add support for mediatek SOC MT8192 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> --- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 6 ++++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 +++++++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 +++++++++++++++++++++++ 4 files changed, 74 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 141cb36b9c07b..3a53ebc4e1724 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -205,9 +205,15 @@ static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { .matrix_bits = 10, }; +static const struct mtk_disp_ccorr_data mt8192_ccorr_driver_data = { + .matrix_bits = 11, +}; + static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { { .compatible = "mediatek,mt8183-disp-ccorr", .data = &mt8183_ccorr_driver_data}, + { .compatible = "mediatek,mt8192-disp-ccorr", + .data = &mt8192_ccorr_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 961f87f8d4d15..e266baae586c4 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -455,6 +455,22 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { .fmt_rgb565_is_0 = true, }; +static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 4, + .fmt_rgb565_is_0 = true, + .smi_id_en = true, +}; + +static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 2, + .fmt_rgb565_is_0 = true, + .smi_id_en = true, +}; + static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-ovl", .data = &mt2701_ovl_driver_data}, @@ -464,6 +480,10 @@ static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { .data = &mt8183_ovl_driver_data}, { .compatible = "mediatek,mt8183-disp-ovl-2l", .data = &mt8183_ovl_2l_driver_data}, + { .compatible = "mediatek,mt8192-disp-ovl", + .data = &mt8192_ovl_driver_data}, + { .compatible = "mediatek,mt8192-disp-ovl-2l", + .data = &mt8192_ovl_2l_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 728aaadfea8cf..f123fc00a3935 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { .fifo_size = 5 * SZ_1K, }; +static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = { + .fifo_size = 5 * SZ_1K, +}; + static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-rdma", .data = &mt2701_rdma_driver_data}, @@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { .data = &mt8173_rdma_driver_data}, { .compatible = "mediatek,mt8183-disp-rdma", .data = &mt8183_rdma_driver_data}, + { .compatible = "mediatek,mt8192-disp-rdma", + .data = &mt8192_rdma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index b013d56d27773..6df551055630c 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -147,6 +147,25 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, }; +static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_OVL_2L0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_POSTMASK0, + DDP_COMPONENT_DITHER, + DDP_COMPONENT_DSI0, +}; + +static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = { + DDP_COMPONENT_OVL_2L2, + DDP_COMPONENT_RDMA4, + DDP_COMPONENT_DPI0, +}; + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -186,6 +205,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), }; +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { + .main_path = mt8192_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), + .ext_path = mt8192_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), +}; + static int mtk_drm_kms_init(struct drm_device *drm) { struct mtk_drm_private *private = drm->dev_private; @@ -404,22 +430,32 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8183-disp-ovl-2l", .data = (void *)MTK_DISP_OVL_2L }, + { .compatible = "mediatek,mt8192-disp-ovl", + .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt8192-disp-ovl-2l", + .data = (void *)MTK_DISP_OVL_2L }, { .compatible = "mediatek,mt2701-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8183-disp-rdma", .data = (void *)MTK_DISP_RDMA }, + { .compatible = "mediatek,mt8192-disp-rdma", + .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA }, { .compatible = "mediatek,mt8183-disp-ccorr", .data = (void *)MTK_DISP_CCORR }, + { .compatible = "mediatek,mt8192-disp-ccorr", + .data = (void *)MTK_DISP_CCORR }, { .compatible = "mediatek,mt2701-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-aal", .data = (void *)MTK_DISP_AAL}, + { .compatible = "mediatek,mt8192-disp-aal", + .data = (void *)MTK_DISP_AAL}, { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, { .compatible = "mediatek,mt8183-disp-gamma", @@ -448,12 +484,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8183-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt8192-disp-mutex", + .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM }, { .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD }, + { .compatible = "mediatek,mt8192-disp-postmask", + .data = (void *)MTK_DISP_POSTMASK }, { } }; @@ -468,6 +508,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { .data = &mt8173_mmsys_driver_data}, { .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data}, + { .compatible = "mediatek,mt8192-mmsys", + .data = &mt8192_mmsys_driver_data}, { } }; -- 2.30.0.365.g02bc693789-goog _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 8/8] drm/mediatek: add support for mediatek SOC MT8192 @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> add support for mediatek SOC MT8192 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> --- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 6 ++++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 +++++++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 +++++++++++++++++++++++ 4 files changed, 74 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 141cb36b9c07b..3a53ebc4e1724 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -205,9 +205,15 @@ static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { .matrix_bits = 10, }; +static const struct mtk_disp_ccorr_data mt8192_ccorr_driver_data = { + .matrix_bits = 11, +}; + static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { { .compatible = "mediatek,mt8183-disp-ccorr", .data = &mt8183_ccorr_driver_data}, + { .compatible = "mediatek,mt8192-disp-ccorr", + .data = &mt8192_ccorr_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 961f87f8d4d15..e266baae586c4 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -455,6 +455,22 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { .fmt_rgb565_is_0 = true, }; +static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 4, + .fmt_rgb565_is_0 = true, + .smi_id_en = true, +}; + +static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 2, + .fmt_rgb565_is_0 = true, + .smi_id_en = true, +}; + static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-ovl", .data = &mt2701_ovl_driver_data}, @@ -464,6 +480,10 @@ static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { .data = &mt8183_ovl_driver_data}, { .compatible = "mediatek,mt8183-disp-ovl-2l", .data = &mt8183_ovl_2l_driver_data}, + { .compatible = "mediatek,mt8192-disp-ovl", + .data = &mt8192_ovl_driver_data}, + { .compatible = "mediatek,mt8192-disp-ovl-2l", + .data = &mt8192_ovl_2l_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 728aaadfea8cf..f123fc00a3935 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { .fifo_size = 5 * SZ_1K, }; +static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = { + .fifo_size = 5 * SZ_1K, +}; + static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-rdma", .data = &mt2701_rdma_driver_data}, @@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { .data = &mt8173_rdma_driver_data}, { .compatible = "mediatek,mt8183-disp-rdma", .data = &mt8183_rdma_driver_data}, + { .compatible = "mediatek,mt8192-disp-rdma", + .data = &mt8192_rdma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index b013d56d27773..6df551055630c 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -147,6 +147,25 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, }; +static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_OVL_2L0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_POSTMASK0, + DDP_COMPONENT_DITHER, + DDP_COMPONENT_DSI0, +}; + +static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = { + DDP_COMPONENT_OVL_2L2, + DDP_COMPONENT_RDMA4, + DDP_COMPONENT_DPI0, +}; + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -186,6 +205,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), }; +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { + .main_path = mt8192_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), + .ext_path = mt8192_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), +}; + static int mtk_drm_kms_init(struct drm_device *drm) { struct mtk_drm_private *private = drm->dev_private; @@ -404,22 +430,32 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8183-disp-ovl-2l", .data = (void *)MTK_DISP_OVL_2L }, + { .compatible = "mediatek,mt8192-disp-ovl", + .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt8192-disp-ovl-2l", + .data = (void *)MTK_DISP_OVL_2L }, { .compatible = "mediatek,mt2701-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8183-disp-rdma", .data = (void *)MTK_DISP_RDMA }, + { .compatible = "mediatek,mt8192-disp-rdma", + .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA }, { .compatible = "mediatek,mt8183-disp-ccorr", .data = (void *)MTK_DISP_CCORR }, + { .compatible = "mediatek,mt8192-disp-ccorr", + .data = (void *)MTK_DISP_CCORR }, { .compatible = "mediatek,mt2701-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-aal", .data = (void *)MTK_DISP_AAL}, + { .compatible = "mediatek,mt8192-disp-aal", + .data = (void *)MTK_DISP_AAL}, { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, { .compatible = "mediatek,mt8183-disp-gamma", @@ -448,12 +484,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8183-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt8192-disp-mutex", + .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM }, { .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD }, + { .compatible = "mediatek,mt8192-disp-postmask", + .data = (void *)MTK_DISP_POSTMASK }, { } }; @@ -468,6 +508,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { .data = &mt8173_mmsys_driver_data}, { .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data}, + { .compatible = "mediatek,mt8192-mmsys", + .data = &mt8192_mmsys_driver_data}, { } }; -- 2.30.0.365.g02bc693789-goog _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 8/8] drm/mediatek: add support for mediatek SOC MT8192 @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu From: Yongqiang Niu <yongqiang.niu@mediatek.com> add support for mediatek SOC MT8192 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> --- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 6 ++++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 +++++++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 +++++++++++++++++++++++ 4 files changed, 74 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 141cb36b9c07b..3a53ebc4e1724 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -205,9 +205,15 @@ static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { .matrix_bits = 10, }; +static const struct mtk_disp_ccorr_data mt8192_ccorr_driver_data = { + .matrix_bits = 11, +}; + static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { { .compatible = "mediatek,mt8183-disp-ccorr", .data = &mt8183_ccorr_driver_data}, + { .compatible = "mediatek,mt8192-disp-ccorr", + .data = &mt8192_ccorr_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 961f87f8d4d15..e266baae586c4 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -455,6 +455,22 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { .fmt_rgb565_is_0 = true, }; +static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 4, + .fmt_rgb565_is_0 = true, + .smi_id_en = true, +}; + +static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 2, + .fmt_rgb565_is_0 = true, + .smi_id_en = true, +}; + static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-ovl", .data = &mt2701_ovl_driver_data}, @@ -464,6 +480,10 @@ static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { .data = &mt8183_ovl_driver_data}, { .compatible = "mediatek,mt8183-disp-ovl-2l", .data = &mt8183_ovl_2l_driver_data}, + { .compatible = "mediatek,mt8192-disp-ovl", + .data = &mt8192_ovl_driver_data}, + { .compatible = "mediatek,mt8192-disp-ovl-2l", + .data = &mt8192_ovl_2l_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 728aaadfea8cf..f123fc00a3935 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { .fifo_size = 5 * SZ_1K, }; +static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = { + .fifo_size = 5 * SZ_1K, +}; + static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-rdma", .data = &mt2701_rdma_driver_data}, @@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { .data = &mt8173_rdma_driver_data}, { .compatible = "mediatek,mt8183-disp-rdma", .data = &mt8183_rdma_driver_data}, + { .compatible = "mediatek,mt8192-disp-rdma", + .data = &mt8192_rdma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index b013d56d27773..6df551055630c 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -147,6 +147,25 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, }; +static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_OVL_2L0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_POSTMASK0, + DDP_COMPONENT_DITHER, + DDP_COMPONENT_DSI0, +}; + +static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = { + DDP_COMPONENT_OVL_2L2, + DDP_COMPONENT_RDMA4, + DDP_COMPONENT_DPI0, +}; + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -186,6 +205,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), }; +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { + .main_path = mt8192_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), + .ext_path = mt8192_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), +}; + static int mtk_drm_kms_init(struct drm_device *drm) { struct mtk_drm_private *private = drm->dev_private; @@ -404,22 +430,32 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8183-disp-ovl-2l", .data = (void *)MTK_DISP_OVL_2L }, + { .compatible = "mediatek,mt8192-disp-ovl", + .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt8192-disp-ovl-2l", + .data = (void *)MTK_DISP_OVL_2L }, { .compatible = "mediatek,mt2701-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8183-disp-rdma", .data = (void *)MTK_DISP_RDMA }, + { .compatible = "mediatek,mt8192-disp-rdma", + .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA }, { .compatible = "mediatek,mt8183-disp-ccorr", .data = (void *)MTK_DISP_CCORR }, + { .compatible = "mediatek,mt8192-disp-ccorr", + .data = (void *)MTK_DISP_CCORR }, { .compatible = "mediatek,mt2701-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-aal", .data = (void *)MTK_DISP_AAL}, + { .compatible = "mediatek,mt8192-disp-aal", + .data = (void *)MTK_DISP_AAL}, { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, { .compatible = "mediatek,mt8183-disp-gamma", @@ -448,12 +484,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8183-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt8192-disp-mutex", + .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM }, { .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD }, + { .compatible = "mediatek,mt8192-disp-postmask", + .data = (void *)MTK_DISP_POSTMASK }, { } }; @@ -468,6 +508,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { .data = &mt8173_mmsys_driver_data}, { .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data}, + { .compatible = "mediatek,mt8192-mmsys", + .data = &mt8192_mmsys_driver_data}, { } }; -- 2.30.0.365.g02bc693789-goog ^ permalink raw reply related [flat|nested] 64+ messages in thread
* [PATCH v6 8/8] drm/mediatek: add support for mediatek SOC MT8192 @ 2021-02-02 8:12 ` Hsin-Yi Wang 0 siblings, 0 replies; 64+ messages in thread From: Hsin-Yi Wang @ 2021-02-02 8:12 UTC (permalink / raw) To: CK Hu, Philipp Zabel, Matthias Brugger Cc: Mark Rutland, devicetree, Yongqiang Niu, David Airlie, linux-kernel, dri-devel, linux-mediatek, Daniel Vetter, linux-arm-kernel From: Yongqiang Niu <yongqiang.niu@mediatek.com> add support for mediatek SOC MT8192 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> --- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 6 ++++ drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 +++++++++++ drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 +++++++++++++++++++++++ 4 files changed, 74 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c index 141cb36b9c07b..3a53ebc4e1724 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -205,9 +205,15 @@ static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { .matrix_bits = 10, }; +static const struct mtk_disp_ccorr_data mt8192_ccorr_driver_data = { + .matrix_bits = 11, +}; + static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { { .compatible = "mediatek,mt8183-disp-ccorr", .data = &mt8183_ccorr_driver_data}, + { .compatible = "mediatek,mt8192-disp-ccorr", + .data = &mt8192_ccorr_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 961f87f8d4d15..e266baae586c4 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -455,6 +455,22 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { .fmt_rgb565_is_0 = true, }; +static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 4, + .fmt_rgb565_is_0 = true, + .smi_id_en = true, +}; + +static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = { + .addr = DISP_REG_OVL_ADDR_MT8173, + .gmc_bits = 10, + .layer_nr = 2, + .fmt_rgb565_is_0 = true, + .smi_id_en = true, +}; + static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-ovl", .data = &mt2701_ovl_driver_data}, @@ -464,6 +480,10 @@ static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { .data = &mt8183_ovl_driver_data}, { .compatible = "mediatek,mt8183-disp-ovl-2l", .data = &mt8183_ovl_2l_driver_data}, + { .compatible = "mediatek,mt8192-disp-ovl", + .data = &mt8192_ovl_driver_data}, + { .compatible = "mediatek,mt8192-disp-ovl-2l", + .data = &mt8192_ovl_2l_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 728aaadfea8cf..f123fc00a3935 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { .fifo_size = 5 * SZ_1K, }; +static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = { + .fifo_size = 5 * SZ_1K, +}; + static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-rdma", .data = &mt2701_rdma_driver_data}, @@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { .data = &mt8173_rdma_driver_data}, { .compatible = "mediatek,mt8183-disp-rdma", .data = &mt8183_rdma_driver_data}, + { .compatible = "mediatek,mt8192-disp-rdma", + .data = &mt8192_rdma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index b013d56d27773..6df551055630c 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -147,6 +147,25 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, }; +static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_OVL_2L0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_POSTMASK0, + DDP_COMPONENT_DITHER, + DDP_COMPONENT_DSI0, +}; + +static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = { + DDP_COMPONENT_OVL_2L2, + DDP_COMPONENT_RDMA4, + DDP_COMPONENT_DPI0, +}; + static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .main_path = mt2701_mtk_ddp_main, .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), @@ -186,6 +205,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), }; +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { + .main_path = mt8192_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), + .ext_path = mt8192_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), +}; + static int mtk_drm_kms_init(struct drm_device *drm) { struct mtk_drm_private *private = drm->dev_private; @@ -404,22 +430,32 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_OVL }, { .compatible = "mediatek,mt8183-disp-ovl-2l", .data = (void *)MTK_DISP_OVL_2L }, + { .compatible = "mediatek,mt8192-disp-ovl", + .data = (void *)MTK_DISP_OVL }, + { .compatible = "mediatek,mt8192-disp-ovl-2l", + .data = (void *)MTK_DISP_OVL_2L }, { .compatible = "mediatek,mt2701-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8183-disp-rdma", .data = (void *)MTK_DISP_RDMA }, + { .compatible = "mediatek,mt8192-disp-rdma", + .data = (void *)MTK_DISP_RDMA }, { .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA }, { .compatible = "mediatek,mt8183-disp-ccorr", .data = (void *)MTK_DISP_CCORR }, + { .compatible = "mediatek,mt8192-disp-ccorr", + .data = (void *)MTK_DISP_CCORR }, { .compatible = "mediatek,mt2701-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-color", .data = (void *)MTK_DISP_COLOR }, { .compatible = "mediatek,mt8173-disp-aal", .data = (void *)MTK_DISP_AAL}, + { .compatible = "mediatek,mt8192-disp-aal", + .data = (void *)MTK_DISP_AAL}, { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, }, { .compatible = "mediatek,mt8183-disp-gamma", @@ -448,12 +484,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8183-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt8192-disp-mutex", + .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM }, { .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD }, + { .compatible = "mediatek,mt8192-disp-postmask", + .data = (void *)MTK_DISP_POSTMASK }, { } }; @@ -468,6 +508,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { .data = &mt8173_mmsys_driver_data}, { .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data}, + { .compatible = "mediatek,mt8192-mmsys", + .data = &mt8192_mmsys_driver_data}, { } }; -- 2.30.0.365.g02bc693789-goog _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 64+ messages in thread
* Re: [PATCH v6 8/8] drm/mediatek: add support for mediatek SOC MT8192 2021-02-02 8:12 ` Hsin-Yi Wang (?) (?) @ 2021-02-02 9:12 ` CK Hu -1 siblings, 0 replies; 64+ messages in thread From: CK Hu @ 2021-02-02 9:12 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie, linux-kernel, dri-devel, Yongqiang Niu, linux-mediatek, Daniel Vetter, Matthias Brugger, linux-arm-kernel Hi, Hsin-Yi: On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > add support for mediatek SOC MT8192 Reviewed-by: CK Hu <ck.hu@mediatek.com> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > --- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 6 ++++ > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 +++++++++++ > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 +++++++++++++++++++++++ > 4 files changed, 74 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > index 141cb36b9c07b..3a53ebc4e1724 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -205,9 +205,15 @@ static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { > .matrix_bits = 10, > }; > > +static const struct mtk_disp_ccorr_data mt8192_ccorr_driver_data = { > + .matrix_bits = 11, > +}; > + > static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { > { .compatible = "mediatek,mt8183-disp-ccorr", > .data = &mt8183_ccorr_driver_data}, > + { .compatible = "mediatek,mt8192-disp-ccorr", > + .data = &mt8192_ccorr_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > index 961f87f8d4d15..e266baae586c4 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > @@ -455,6 +455,22 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { > .fmt_rgb565_is_0 = true, > }; > > +static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = { > + .addr = DISP_REG_OVL_ADDR_MT8173, > + .gmc_bits = 10, > + .layer_nr = 4, > + .fmt_rgb565_is_0 = true, > + .smi_id_en = true, > +}; > + > +static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = { > + .addr = DISP_REG_OVL_ADDR_MT8173, > + .gmc_bits = 10, > + .layer_nr = 2, > + .fmt_rgb565_is_0 = true, > + .smi_id_en = true, > +}; > + > static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { > { .compatible = "mediatek,mt2701-disp-ovl", > .data = &mt2701_ovl_driver_data}, > @@ -464,6 +480,10 @@ static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { > .data = &mt8183_ovl_driver_data}, > { .compatible = "mediatek,mt8183-disp-ovl-2l", > .data = &mt8183_ovl_2l_driver_data}, > + { .compatible = "mediatek,mt8192-disp-ovl", > + .data = &mt8192_ovl_driver_data}, > + { .compatible = "mediatek,mt8192-disp-ovl-2l", > + .data = &mt8192_ovl_2l_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index 728aaadfea8cf..f123fc00a3935 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { > .fifo_size = 5 * SZ_1K, > }; > > +static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = { > + .fifo_size = 5 * SZ_1K, > +}; > + > static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { > { .compatible = "mediatek,mt2701-disp-rdma", > .data = &mt2701_rdma_driver_data}, > @@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { > .data = &mt8173_rdma_driver_data}, > { .compatible = "mediatek,mt8183-disp-rdma", > .data = &mt8183_rdma_driver_data}, > + { .compatible = "mediatek,mt8192-disp-rdma", > + .data = &mt8192_rdma_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index b013d56d27773..6df551055630c 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -147,6 +147,25 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { > DDP_COMPONENT_DPI0, > }; > > +static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = { > + DDP_COMPONENT_OVL0, > + DDP_COMPONENT_OVL_2L0, > + DDP_COMPONENT_RDMA0, > + DDP_COMPONENT_COLOR0, > + DDP_COMPONENT_CCORR, > + DDP_COMPONENT_AAL0, > + DDP_COMPONENT_GAMMA, > + DDP_COMPONENT_POSTMASK0, > + DDP_COMPONENT_DITHER, > + DDP_COMPONENT_DSI0, > +}; > + > +static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = { > + DDP_COMPONENT_OVL_2L2, > + DDP_COMPONENT_RDMA4, > + DDP_COMPONENT_DPI0, > +}; > + > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > .main_path = mt2701_mtk_ddp_main, > .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), > @@ -186,6 +205,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), > }; > > +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { > + .main_path = mt8192_mtk_ddp_main, > + .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), > + .ext_path = mt8192_mtk_ddp_ext, > + .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), > +}; > + > static int mtk_drm_kms_init(struct drm_device *drm) > { > struct mtk_drm_private *private = drm->dev_private; > @@ -404,22 +430,32 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { > .data = (void *)MTK_DISP_OVL }, > { .compatible = "mediatek,mt8183-disp-ovl-2l", > .data = (void *)MTK_DISP_OVL_2L }, > + { .compatible = "mediatek,mt8192-disp-ovl", > + .data = (void *)MTK_DISP_OVL }, > + { .compatible = "mediatek,mt8192-disp-ovl-2l", > + .data = (void *)MTK_DISP_OVL_2L }, > { .compatible = "mediatek,mt2701-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8173-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8183-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > + { .compatible = "mediatek,mt8192-disp-rdma", > + .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8173-disp-wdma", > .data = (void *)MTK_DISP_WDMA }, > { .compatible = "mediatek,mt8183-disp-ccorr", > .data = (void *)MTK_DISP_CCORR }, > + { .compatible = "mediatek,mt8192-disp-ccorr", > + .data = (void *)MTK_DISP_CCORR }, > { .compatible = "mediatek,mt2701-disp-color", > .data = (void *)MTK_DISP_COLOR }, > { .compatible = "mediatek,mt8173-disp-color", > .data = (void *)MTK_DISP_COLOR }, > { .compatible = "mediatek,mt8173-disp-aal", > .data = (void *)MTK_DISP_AAL}, > + { .compatible = "mediatek,mt8192-disp-aal", > + .data = (void *)MTK_DISP_AAL}, > { .compatible = "mediatek,mt8173-disp-gamma", > .data = (void *)MTK_DISP_GAMMA, }, > { .compatible = "mediatek,mt8183-disp-gamma", > @@ -448,12 +484,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { > .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt8183-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > + { .compatible = "mediatek,mt8192-disp-mutex", > + .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt2701-disp-pwm", > .data = (void *)MTK_DISP_BLS }, > { .compatible = "mediatek,mt8173-disp-pwm", > .data = (void *)MTK_DISP_PWM }, > { .compatible = "mediatek,mt8173-disp-od", > .data = (void *)MTK_DISP_OD }, > + { .compatible = "mediatek,mt8192-disp-postmask", > + .data = (void *)MTK_DISP_POSTMASK }, > { } > }; > > @@ -468,6 +508,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { > .data = &mt8173_mmsys_driver_data}, > { .compatible = "mediatek,mt8183-mmsys", > .data = &mt8183_mmsys_driver_data}, > + { .compatible = "mediatek,mt8192-mmsys", > + .data = &mt8192_mmsys_driver_data}, > { } > }; > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 8/8] drm/mediatek: add support for mediatek SOC MT8192 @ 2021-02-02 9:12 ` CK Hu 0 siblings, 0 replies; 64+ messages in thread From: CK Hu @ 2021-02-02 9:12 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Mark Rutland, devicetree, David Airlie, linux-kernel, dri-devel, Yongqiang Niu, linux-mediatek, Matthias Brugger, linux-arm-kernel Hi, Hsin-Yi: On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > add support for mediatek SOC MT8192 Reviewed-by: CK Hu <ck.hu@mediatek.com> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > --- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 6 ++++ > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 +++++++++++ > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 +++++++++++++++++++++++ > 4 files changed, 74 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > index 141cb36b9c07b..3a53ebc4e1724 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -205,9 +205,15 @@ static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { > .matrix_bits = 10, > }; > > +static const struct mtk_disp_ccorr_data mt8192_ccorr_driver_data = { > + .matrix_bits = 11, > +}; > + > static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { > { .compatible = "mediatek,mt8183-disp-ccorr", > .data = &mt8183_ccorr_driver_data}, > + { .compatible = "mediatek,mt8192-disp-ccorr", > + .data = &mt8192_ccorr_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > index 961f87f8d4d15..e266baae586c4 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > @@ -455,6 +455,22 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { > .fmt_rgb565_is_0 = true, > }; > > +static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = { > + .addr = DISP_REG_OVL_ADDR_MT8173, > + .gmc_bits = 10, > + .layer_nr = 4, > + .fmt_rgb565_is_0 = true, > + .smi_id_en = true, > +}; > + > +static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = { > + .addr = DISP_REG_OVL_ADDR_MT8173, > + .gmc_bits = 10, > + .layer_nr = 2, > + .fmt_rgb565_is_0 = true, > + .smi_id_en = true, > +}; > + > static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { > { .compatible = "mediatek,mt2701-disp-ovl", > .data = &mt2701_ovl_driver_data}, > @@ -464,6 +480,10 @@ static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { > .data = &mt8183_ovl_driver_data}, > { .compatible = "mediatek,mt8183-disp-ovl-2l", > .data = &mt8183_ovl_2l_driver_data}, > + { .compatible = "mediatek,mt8192-disp-ovl", > + .data = &mt8192_ovl_driver_data}, > + { .compatible = "mediatek,mt8192-disp-ovl-2l", > + .data = &mt8192_ovl_2l_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index 728aaadfea8cf..f123fc00a3935 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { > .fifo_size = 5 * SZ_1K, > }; > > +static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = { > + .fifo_size = 5 * SZ_1K, > +}; > + > static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { > { .compatible = "mediatek,mt2701-disp-rdma", > .data = &mt2701_rdma_driver_data}, > @@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { > .data = &mt8173_rdma_driver_data}, > { .compatible = "mediatek,mt8183-disp-rdma", > .data = &mt8183_rdma_driver_data}, > + { .compatible = "mediatek,mt8192-disp-rdma", > + .data = &mt8192_rdma_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index b013d56d27773..6df551055630c 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -147,6 +147,25 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { > DDP_COMPONENT_DPI0, > }; > > +static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = { > + DDP_COMPONENT_OVL0, > + DDP_COMPONENT_OVL_2L0, > + DDP_COMPONENT_RDMA0, > + DDP_COMPONENT_COLOR0, > + DDP_COMPONENT_CCORR, > + DDP_COMPONENT_AAL0, > + DDP_COMPONENT_GAMMA, > + DDP_COMPONENT_POSTMASK0, > + DDP_COMPONENT_DITHER, > + DDP_COMPONENT_DSI0, > +}; > + > +static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = { > + DDP_COMPONENT_OVL_2L2, > + DDP_COMPONENT_RDMA4, > + DDP_COMPONENT_DPI0, > +}; > + > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > .main_path = mt2701_mtk_ddp_main, > .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), > @@ -186,6 +205,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), > }; > > +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { > + .main_path = mt8192_mtk_ddp_main, > + .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), > + .ext_path = mt8192_mtk_ddp_ext, > + .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), > +}; > + > static int mtk_drm_kms_init(struct drm_device *drm) > { > struct mtk_drm_private *private = drm->dev_private; > @@ -404,22 +430,32 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { > .data = (void *)MTK_DISP_OVL }, > { .compatible = "mediatek,mt8183-disp-ovl-2l", > .data = (void *)MTK_DISP_OVL_2L }, > + { .compatible = "mediatek,mt8192-disp-ovl", > + .data = (void *)MTK_DISP_OVL }, > + { .compatible = "mediatek,mt8192-disp-ovl-2l", > + .data = (void *)MTK_DISP_OVL_2L }, > { .compatible = "mediatek,mt2701-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8173-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8183-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > + { .compatible = "mediatek,mt8192-disp-rdma", > + .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8173-disp-wdma", > .data = (void *)MTK_DISP_WDMA }, > { .compatible = "mediatek,mt8183-disp-ccorr", > .data = (void *)MTK_DISP_CCORR }, > + { .compatible = "mediatek,mt8192-disp-ccorr", > + .data = (void *)MTK_DISP_CCORR }, > { .compatible = "mediatek,mt2701-disp-color", > .data = (void *)MTK_DISP_COLOR }, > { .compatible = "mediatek,mt8173-disp-color", > .data = (void *)MTK_DISP_COLOR }, > { .compatible = "mediatek,mt8173-disp-aal", > .data = (void *)MTK_DISP_AAL}, > + { .compatible = "mediatek,mt8192-disp-aal", > + .data = (void *)MTK_DISP_AAL}, > { .compatible = "mediatek,mt8173-disp-gamma", > .data = (void *)MTK_DISP_GAMMA, }, > { .compatible = "mediatek,mt8183-disp-gamma", > @@ -448,12 +484,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { > .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt8183-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > + { .compatible = "mediatek,mt8192-disp-mutex", > + .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt2701-disp-pwm", > .data = (void *)MTK_DISP_BLS }, > { .compatible = "mediatek,mt8173-disp-pwm", > .data = (void *)MTK_DISP_PWM }, > { .compatible = "mediatek,mt8173-disp-od", > .data = (void *)MTK_DISP_OD }, > + { .compatible = "mediatek,mt8192-disp-postmask", > + .data = (void *)MTK_DISP_POSTMASK }, > { } > }; > > @@ -468,6 +508,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { > .data = &mt8173_mmsys_driver_data}, > { .compatible = "mediatek,mt8183-mmsys", > .data = &mt8183_mmsys_driver_data}, > + { .compatible = "mediatek,mt8192-mmsys", > + .data = &mt8192_mmsys_driver_data}, > { } > }; > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 8/8] drm/mediatek: add support for mediatek SOC MT8192 @ 2021-02-02 9:12 ` CK Hu 0 siblings, 0 replies; 64+ messages in thread From: CK Hu @ 2021-02-02 9:12 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Philipp Zabel, Matthias Brugger, David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu Hi, Hsin-Yi: On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > add support for mediatek SOC MT8192 Reviewed-by: CK Hu <ck.hu@mediatek.com> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > --- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 6 ++++ > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 +++++++++++ > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 +++++++++++++++++++++++ > 4 files changed, 74 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > index 141cb36b9c07b..3a53ebc4e1724 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -205,9 +205,15 @@ static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { > .matrix_bits = 10, > }; > > +static const struct mtk_disp_ccorr_data mt8192_ccorr_driver_data = { > + .matrix_bits = 11, > +}; > + > static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { > { .compatible = "mediatek,mt8183-disp-ccorr", > .data = &mt8183_ccorr_driver_data}, > + { .compatible = "mediatek,mt8192-disp-ccorr", > + .data = &mt8192_ccorr_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > index 961f87f8d4d15..e266baae586c4 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > @@ -455,6 +455,22 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { > .fmt_rgb565_is_0 = true, > }; > > +static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = { > + .addr = DISP_REG_OVL_ADDR_MT8173, > + .gmc_bits = 10, > + .layer_nr = 4, > + .fmt_rgb565_is_0 = true, > + .smi_id_en = true, > +}; > + > +static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = { > + .addr = DISP_REG_OVL_ADDR_MT8173, > + .gmc_bits = 10, > + .layer_nr = 2, > + .fmt_rgb565_is_0 = true, > + .smi_id_en = true, > +}; > + > static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { > { .compatible = "mediatek,mt2701-disp-ovl", > .data = &mt2701_ovl_driver_data}, > @@ -464,6 +480,10 @@ static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { > .data = &mt8183_ovl_driver_data}, > { .compatible = "mediatek,mt8183-disp-ovl-2l", > .data = &mt8183_ovl_2l_driver_data}, > + { .compatible = "mediatek,mt8192-disp-ovl", > + .data = &mt8192_ovl_driver_data}, > + { .compatible = "mediatek,mt8192-disp-ovl-2l", > + .data = &mt8192_ovl_2l_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index 728aaadfea8cf..f123fc00a3935 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { > .fifo_size = 5 * SZ_1K, > }; > > +static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = { > + .fifo_size = 5 * SZ_1K, > +}; > + > static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { > { .compatible = "mediatek,mt2701-disp-rdma", > .data = &mt2701_rdma_driver_data}, > @@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { > .data = &mt8173_rdma_driver_data}, > { .compatible = "mediatek,mt8183-disp-rdma", > .data = &mt8183_rdma_driver_data}, > + { .compatible = "mediatek,mt8192-disp-rdma", > + .data = &mt8192_rdma_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index b013d56d27773..6df551055630c 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -147,6 +147,25 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { > DDP_COMPONENT_DPI0, > }; > > +static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = { > + DDP_COMPONENT_OVL0, > + DDP_COMPONENT_OVL_2L0, > + DDP_COMPONENT_RDMA0, > + DDP_COMPONENT_COLOR0, > + DDP_COMPONENT_CCORR, > + DDP_COMPONENT_AAL0, > + DDP_COMPONENT_GAMMA, > + DDP_COMPONENT_POSTMASK0, > + DDP_COMPONENT_DITHER, > + DDP_COMPONENT_DSI0, > +}; > + > +static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = { > + DDP_COMPONENT_OVL_2L2, > + DDP_COMPONENT_RDMA4, > + DDP_COMPONENT_DPI0, > +}; > + > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > .main_path = mt2701_mtk_ddp_main, > .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), > @@ -186,6 +205,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), > }; > > +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { > + .main_path = mt8192_mtk_ddp_main, > + .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), > + .ext_path = mt8192_mtk_ddp_ext, > + .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), > +}; > + > static int mtk_drm_kms_init(struct drm_device *drm) > { > struct mtk_drm_private *private = drm->dev_private; > @@ -404,22 +430,32 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { > .data = (void *)MTK_DISP_OVL }, > { .compatible = "mediatek,mt8183-disp-ovl-2l", > .data = (void *)MTK_DISP_OVL_2L }, > + { .compatible = "mediatek,mt8192-disp-ovl", > + .data = (void *)MTK_DISP_OVL }, > + { .compatible = "mediatek,mt8192-disp-ovl-2l", > + .data = (void *)MTK_DISP_OVL_2L }, > { .compatible = "mediatek,mt2701-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8173-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8183-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > + { .compatible = "mediatek,mt8192-disp-rdma", > + .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8173-disp-wdma", > .data = (void *)MTK_DISP_WDMA }, > { .compatible = "mediatek,mt8183-disp-ccorr", > .data = (void *)MTK_DISP_CCORR }, > + { .compatible = "mediatek,mt8192-disp-ccorr", > + .data = (void *)MTK_DISP_CCORR }, > { .compatible = "mediatek,mt2701-disp-color", > .data = (void *)MTK_DISP_COLOR }, > { .compatible = "mediatek,mt8173-disp-color", > .data = (void *)MTK_DISP_COLOR }, > { .compatible = "mediatek,mt8173-disp-aal", > .data = (void *)MTK_DISP_AAL}, > + { .compatible = "mediatek,mt8192-disp-aal", > + .data = (void *)MTK_DISP_AAL}, > { .compatible = "mediatek,mt8173-disp-gamma", > .data = (void *)MTK_DISP_GAMMA, }, > { .compatible = "mediatek,mt8183-disp-gamma", > @@ -448,12 +484,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { > .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt8183-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > + { .compatible = "mediatek,mt8192-disp-mutex", > + .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt2701-disp-pwm", > .data = (void *)MTK_DISP_BLS }, > { .compatible = "mediatek,mt8173-disp-pwm", > .data = (void *)MTK_DISP_PWM }, > { .compatible = "mediatek,mt8173-disp-od", > .data = (void *)MTK_DISP_OD }, > + { .compatible = "mediatek,mt8192-disp-postmask", > + .data = (void *)MTK_DISP_POSTMASK }, > { } > }; > > @@ -468,6 +508,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { > .data = &mt8173_mmsys_driver_data}, > { .compatible = "mediatek,mt8183-mmsys", > .data = &mt8183_mmsys_driver_data}, > + { .compatible = "mediatek,mt8192-mmsys", > + .data = &mt8192_mmsys_driver_data}, > { } > }; > ^ permalink raw reply [flat|nested] 64+ messages in thread
* Re: [PATCH v6 8/8] drm/mediatek: add support for mediatek SOC MT8192 @ 2021-02-02 9:12 ` CK Hu 0 siblings, 0 replies; 64+ messages in thread From: CK Hu @ 2021-02-02 9:12 UTC (permalink / raw) To: Hsin-Yi Wang Cc: Mark Rutland, devicetree, Philipp Zabel, David Airlie, linux-kernel, dri-devel, Yongqiang Niu, linux-mediatek, Daniel Vetter, Matthias Brugger, linux-arm-kernel Hi, Hsin-Yi: On Tue, 2021-02-02 at 16:12 +0800, Hsin-Yi Wang wrote: > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > add support for mediatek SOC MT8192 Reviewed-by: CK Hu <ck.hu@mediatek.com> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> > --- > drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 6 ++++ > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 20 +++++++++++ > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++ > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 +++++++++++++++++++++++ > 4 files changed, 74 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > index 141cb36b9c07b..3a53ebc4e1724 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c > @@ -205,9 +205,15 @@ static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = { > .matrix_bits = 10, > }; > > +static const struct mtk_disp_ccorr_data mt8192_ccorr_driver_data = { > + .matrix_bits = 11, > +}; > + > static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = { > { .compatible = "mediatek,mt8183-disp-ccorr", > .data = &mt8183_ccorr_driver_data}, > + { .compatible = "mediatek,mt8192-disp-ccorr", > + .data = &mt8192_ccorr_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > index 961f87f8d4d15..e266baae586c4 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > @@ -455,6 +455,22 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { > .fmt_rgb565_is_0 = true, > }; > > +static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = { > + .addr = DISP_REG_OVL_ADDR_MT8173, > + .gmc_bits = 10, > + .layer_nr = 4, > + .fmt_rgb565_is_0 = true, > + .smi_id_en = true, > +}; > + > +static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = { > + .addr = DISP_REG_OVL_ADDR_MT8173, > + .gmc_bits = 10, > + .layer_nr = 2, > + .fmt_rgb565_is_0 = true, > + .smi_id_en = true, > +}; > + > static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { > { .compatible = "mediatek,mt2701-disp-ovl", > .data = &mt2701_ovl_driver_data}, > @@ -464,6 +480,10 @@ static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = { > .data = &mt8183_ovl_driver_data}, > { .compatible = "mediatek,mt8183-disp-ovl-2l", > .data = &mt8183_ovl_2l_driver_data}, > + { .compatible = "mediatek,mt8192-disp-ovl", > + .data = &mt8192_ovl_driver_data}, > + { .compatible = "mediatek,mt8192-disp-ovl-2l", > + .data = &mt8192_ovl_2l_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index 728aaadfea8cf..f123fc00a3935 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = { > .fifo_size = 5 * SZ_1K, > }; > > +static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = { > + .fifo_size = 5 * SZ_1K, > +}; > + > static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { > { .compatible = "mediatek,mt2701-disp-rdma", > .data = &mt2701_rdma_driver_data}, > @@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = { > .data = &mt8173_rdma_driver_data}, > { .compatible = "mediatek,mt8183-disp-rdma", > .data = &mt8183_rdma_driver_data}, > + { .compatible = "mediatek,mt8192-disp-rdma", > + .data = &mt8192_rdma_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match); > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index b013d56d27773..6df551055630c 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -147,6 +147,25 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = { > DDP_COMPONENT_DPI0, > }; > > +static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = { > + DDP_COMPONENT_OVL0, > + DDP_COMPONENT_OVL_2L0, > + DDP_COMPONENT_RDMA0, > + DDP_COMPONENT_COLOR0, > + DDP_COMPONENT_CCORR, > + DDP_COMPONENT_AAL0, > + DDP_COMPONENT_GAMMA, > + DDP_COMPONENT_POSTMASK0, > + DDP_COMPONENT_DITHER, > + DDP_COMPONENT_DSI0, > +}; > + > +static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = { > + DDP_COMPONENT_OVL_2L2, > + DDP_COMPONENT_RDMA4, > + DDP_COMPONENT_DPI0, > +}; > + > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > .main_path = mt2701_mtk_ddp_main, > .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), > @@ -186,6 +205,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext), > }; > > +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { > + .main_path = mt8192_mtk_ddp_main, > + .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main), > + .ext_path = mt8192_mtk_ddp_ext, > + .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext), > +}; > + > static int mtk_drm_kms_init(struct drm_device *drm) > { > struct mtk_drm_private *private = drm->dev_private; > @@ -404,22 +430,32 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { > .data = (void *)MTK_DISP_OVL }, > { .compatible = "mediatek,mt8183-disp-ovl-2l", > .data = (void *)MTK_DISP_OVL_2L }, > + { .compatible = "mediatek,mt8192-disp-ovl", > + .data = (void *)MTK_DISP_OVL }, > + { .compatible = "mediatek,mt8192-disp-ovl-2l", > + .data = (void *)MTK_DISP_OVL_2L }, > { .compatible = "mediatek,mt2701-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8173-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8183-disp-rdma", > .data = (void *)MTK_DISP_RDMA }, > + { .compatible = "mediatek,mt8192-disp-rdma", > + .data = (void *)MTK_DISP_RDMA }, > { .compatible = "mediatek,mt8173-disp-wdma", > .data = (void *)MTK_DISP_WDMA }, > { .compatible = "mediatek,mt8183-disp-ccorr", > .data = (void *)MTK_DISP_CCORR }, > + { .compatible = "mediatek,mt8192-disp-ccorr", > + .data = (void *)MTK_DISP_CCORR }, > { .compatible = "mediatek,mt2701-disp-color", > .data = (void *)MTK_DISP_COLOR }, > { .compatible = "mediatek,mt8173-disp-color", > .data = (void *)MTK_DISP_COLOR }, > { .compatible = "mediatek,mt8173-disp-aal", > .data = (void *)MTK_DISP_AAL}, > + { .compatible = "mediatek,mt8192-disp-aal", > + .data = (void *)MTK_DISP_AAL}, > { .compatible = "mediatek,mt8173-disp-gamma", > .data = (void *)MTK_DISP_GAMMA, }, > { .compatible = "mediatek,mt8183-disp-gamma", > @@ -448,12 +484,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { > .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt8183-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > + { .compatible = "mediatek,mt8192-disp-mutex", > + .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt2701-disp-pwm", > .data = (void *)MTK_DISP_BLS }, > { .compatible = "mediatek,mt8173-disp-pwm", > .data = (void *)MTK_DISP_PWM }, > { .compatible = "mediatek,mt8173-disp-od", > .data = (void *)MTK_DISP_OD }, > + { .compatible = "mediatek,mt8192-disp-postmask", > + .data = (void *)MTK_DISP_POSTMASK }, > { } > }; > > @@ -468,6 +508,8 @@ static const struct of_device_id mtk_drm_of_ids[] = { > .data = &mt8173_mmsys_driver_data}, > { .compatible = "mediatek,mt8183-mmsys", > .data = &mt8183_mmsys_driver_data}, > + { .compatible = "mediatek,mt8192-mmsys", > + .data = &mt8192_mmsys_driver_data}, > { } > }; > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 64+ messages in thread
end of thread, other threads:[~2021-02-09 16:37 UTC | newest] Thread overview: 64+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2021-02-02 8:12 [PATCH v6 0/8] drm/mediatek: add support for mediatek SOC MT8192 Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 8:12 ` [PATCH v6 1/8] drm/mediatek: add component OVL_2L2 Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 8:12 ` [PATCH v6 2/8] drm/mediatek: add component POSTMASK Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 9:09 ` CK Hu 2021-02-02 9:09 ` CK Hu 2021-02-02 9:09 ` CK Hu 2021-02-02 9:09 ` CK Hu 2021-02-09 15:32 ` Guenter Roeck 2021-02-09 15:32 ` Guenter Roeck 2021-02-09 15:32 ` Guenter Roeck 2021-02-09 15:32 ` Guenter Roeck 2021-02-02 8:12 ` [PATCH v6 3/8] drm/mediatek: add component RDMA4 Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 8:12 ` [PATCH v6 4/8] drm/mediatek: separate ccorr module Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-03 16:13 ` Chun-Kuang Hu 2021-02-03 16:13 ` Chun-Kuang Hu 2021-02-03 16:13 ` Chun-Kuang Hu 2021-02-03 16:13 ` Chun-Kuang Hu 2021-02-02 8:12 ` [PATCH v6 5/8] drm/mediatek: Fix ccorr size config Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-03 16:13 ` Chun-Kuang Hu 2021-02-03 16:13 ` Chun-Kuang Hu 2021-02-03 16:13 ` Chun-Kuang Hu 2021-02-03 16:13 ` Chun-Kuang Hu 2021-02-02 8:12 ` [PATCH v6 6/8] drm/mediatek: add matrix_bits private data for ccorr Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 9:11 ` CK Hu 2021-02-02 9:11 ` CK Hu 2021-02-02 9:11 ` CK Hu 2021-02-02 9:11 ` CK Hu 2021-02-03 16:14 ` Chun-Kuang Hu 2021-02-03 16:14 ` Chun-Kuang Hu 2021-02-03 16:14 ` Chun-Kuang Hu 2021-02-03 16:14 ` Chun-Kuang Hu 2021-02-02 8:12 ` [PATCH v6 7/8] soc: mediatek: add mtk mutex support for MT8192 Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 8:12 ` [PATCH v6 8/8] drm/mediatek: add support for mediatek SOC MT8192 Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 8:12 ` Hsin-Yi Wang 2021-02-02 9:12 ` CK Hu 2021-02-02 9:12 ` CK Hu 2021-02-02 9:12 ` CK Hu 2021-02-02 9:12 ` CK Hu
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