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From: guoren@kernel.org
To: guoren@kernel.org, anup@brainfault.org, atish.patra@wdc.com,
	maz@kernel.org, tglx@linutronix.de, palmer@dabbelt.com,
	heiko@sntech.de, robh@kernel.org
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	Guo Ren <guoren@linux.alibaba.com>,
	Palmer Dabbelt <palmerdabbelt@google.com>
Subject: [PATCH V4 2/3] dt-bindings: update riscv plic compatible string
Date: Sat, 16 Oct 2021 11:21:59 +0800	[thread overview]
Message-ID: <20211016032200.2869998-3-guoren@kernel.org> (raw)
In-Reply-To: <20211016032200.2869998-1-guoren@kernel.org>

From: Guo Ren <guoren@linux.alibaba.com>

Add the compatible string "thead,c900-plic" to the riscv plic
bindings to support allwinner d1 SOC which contains c906 core.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Palmer Dabbelt <palmerdabbelt@google.com>
Cc: Anup Patel <anup@brainfault.org>
Cc: Atish Patra <atish.patra@wdc.com>

---

Changes since V4:
 - Update description in errata style
 - Update enum suggested by Anup, Heiko, Samuel

Changes since V3:
 - Rename "c9xx" to "c900"
 - Add thead,c900-plic in the description section
---
 .../interrupt-controller/sifive,plic-1.0.0.yaml       | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 08d5a57ce00f..272f29540135 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -35,6 +35,12 @@ description:
   contains a specific memory layout, which is documented in chapter 8 of the
   SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
 
+  The C9xx PLIC does not comply with the interrupt claim/completion process defined
+  by the RISC-V PLIC specification because C9xx PLIC will mask an IRQ when it is
+  claimed by PLIC driver (i.e. readl(claim) and the IRQ will be unmasked upon
+  completion by PLIC driver (i.e. writel(claim). This behaviour breaks the handling
+  of IRQS_ONESHOT by the generic handle_fasteoi_irq() used in the PLIC driver.
+
 maintainers:
   - Sagar Kadam <sagar.kadam@sifive.com>
   - Paul Walmsley  <paul.walmsley@sifive.com>
@@ -46,7 +52,10 @@ properties:
       - enum:
           - sifive,fu540-c000-plic
           - canaan,k210-plic
-      - const: sifive,plic-1.0.0
+      - enmu:
+          - sifive,plic-1.0.0
+          - thead,c900-plic
+          - allwinner,sun20i-d1-plic
 
   reg:
     maxItems: 1
-- 
2.25.1


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WARNING: multiple messages have this Message-ID (diff)
From: guoren@kernel.org
To: guoren@kernel.org, anup@brainfault.org, atish.patra@wdc.com,
	maz@kernel.org, tglx@linutronix.de, palmer@dabbelt.com,
	heiko@sntech.de, robh@kernel.org
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	Guo Ren <guoren@linux.alibaba.com>,
	Palmer Dabbelt <palmerdabbelt@google.com>
Subject: [PATCH V4 2/3] dt-bindings: update riscv plic compatible string
Date: Sat, 16 Oct 2021 11:21:59 +0800	[thread overview]
Message-ID: <20211016032200.2869998-3-guoren@kernel.org> (raw)
In-Reply-To: <20211016032200.2869998-1-guoren@kernel.org>

From: Guo Ren <guoren@linux.alibaba.com>

Add the compatible string "thead,c900-plic" to the riscv plic
bindings to support allwinner d1 SOC which contains c906 core.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Palmer Dabbelt <palmerdabbelt@google.com>
Cc: Anup Patel <anup@brainfault.org>
Cc: Atish Patra <atish.patra@wdc.com>

---

Changes since V4:
 - Update description in errata style
 - Update enum suggested by Anup, Heiko, Samuel

Changes since V3:
 - Rename "c9xx" to "c900"
 - Add thead,c900-plic in the description section
---
 .../interrupt-controller/sifive,plic-1.0.0.yaml       | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 08d5a57ce00f..272f29540135 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -35,6 +35,12 @@ description:
   contains a specific memory layout, which is documented in chapter 8 of the
   SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
 
+  The C9xx PLIC does not comply with the interrupt claim/completion process defined
+  by the RISC-V PLIC specification because C9xx PLIC will mask an IRQ when it is
+  claimed by PLIC driver (i.e. readl(claim) and the IRQ will be unmasked upon
+  completion by PLIC driver (i.e. writel(claim). This behaviour breaks the handling
+  of IRQS_ONESHOT by the generic handle_fasteoi_irq() used in the PLIC driver.
+
 maintainers:
   - Sagar Kadam <sagar.kadam@sifive.com>
   - Paul Walmsley  <paul.walmsley@sifive.com>
@@ -46,7 +52,10 @@ properties:
       - enum:
           - sifive,fu540-c000-plic
           - canaan,k210-plic
-      - const: sifive,plic-1.0.0
+      - enmu:
+          - sifive,plic-1.0.0
+          - thead,c900-plic
+          - allwinner,sun20i-d1-plic
 
   reg:
     maxItems: 1
-- 
2.25.1


  parent reply	other threads:[~2021-10-16  3:22 UTC|newest]

Thread overview: 68+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-16  3:21 [PATCH V4 0/3] irqchip: riscv: Add thead,c900-plic support guoren
2021-10-16  3:21 ` guoren
2021-10-16  3:21 ` [PATCH V4 1/3] irqchip/sifive-plic: " guoren
2021-10-16  3:21   ` guoren
2021-10-18  5:17   ` Samuel Holland
2021-10-18  5:17     ` Samuel Holland
2021-10-18  5:40     ` Anup Patel
2021-10-18  5:40       ` Anup Patel
2021-10-18  7:05     ` Guo Ren
2021-10-18  7:05       ` Guo Ren
2021-10-18  7:21     ` Marc Zyngier
2021-10-18  7:21       ` Marc Zyngier
2021-10-19  9:33       ` Guo Ren
2021-10-19  9:33         ` Guo Ren
2021-10-19 10:18         ` Marc Zyngier
2021-10-19 10:18           ` Marc Zyngier
2021-10-19 13:27           ` Guo Ren
2021-10-19 13:27             ` Guo Ren
2021-10-20 13:34             ` Marc Zyngier
2021-10-20 13:34               ` Marc Zyngier
2021-10-20 14:19               ` Guo Ren
2021-10-20 14:19                 ` Guo Ren
2021-10-20 14:59                 ` Darius Rad
2021-10-20 14:59                   ` Darius Rad
2021-10-20 16:18                   ` Anup Patel
2021-10-20 16:18                     ` Anup Patel
2021-10-20 18:01                     ` Darius Rad
2021-10-20 18:01                       ` Darius Rad
2021-10-21  8:47                       ` Anup Patel
2021-10-21  8:47                         ` Anup Patel
2021-10-20 14:33               ` Anup Patel
2021-10-20 14:33                 ` Anup Patel
2021-10-20 15:08                 ` Marc Zyngier
2021-10-20 15:08                   ` Marc Zyngier
2021-10-20 16:08                   ` Anup Patel
2021-10-20 16:08                     ` Anup Patel
2021-10-20 16:48                     ` Marc Zyngier
2021-10-20 16:48                       ` Marc Zyngier
2021-10-21  8:52                       ` Anup Patel
2021-10-21  8:52                         ` Anup Patel
2021-10-21  1:46                     ` Guo Ren
2021-10-21  1:46                       ` Guo Ren
2021-10-21  2:00                   ` Guo Ren
2021-10-21  2:00                     ` Guo Ren
2021-10-21  8:33                     ` Marc Zyngier
2021-10-21  8:33                       ` Marc Zyngier
2021-10-21  9:43                       ` Guo Ren
2021-10-21  9:43                         ` Guo Ren
2021-10-16  3:21 ` guoren [this message]
2021-10-16  3:21   ` [PATCH V4 2/3] dt-bindings: update riscv plic compatible string guoren
2021-10-16  7:07   ` Andreas Schwab
2021-10-16  7:07     ` Andreas Schwab
2021-10-16  9:16     ` Guo Ren
2021-10-16  9:16       ` Guo Ren
2021-10-16 10:34   ` Heiko Stuebner
2021-10-16 10:34     ` Heiko Stuebner
2021-10-16 12:56     ` Guo Ren
2021-10-16 12:56       ` Guo Ren
2021-10-16 16:31       ` Heiko Stuebner
2021-10-16 16:31         ` Heiko Stuebner
2021-10-20 12:15         ` Guo Ren
2021-10-20 12:15           ` Guo Ren
2021-10-18 12:02   ` Rob Herring
2021-10-18 12:02     ` Rob Herring
2021-10-19  0:55     ` Guo Ren
2021-10-19  0:55       ` Guo Ren
2021-10-16  3:22 ` [PATCH V4 3/3] dt-bindings: vendor-prefixes: add T-Head Semiconductor guoren
2021-10-16  3:22   ` guoren

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