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From: Andreas Schwab <schwab@linux-m68k.org>
To: guoren@kernel.org
Cc: anup@brainfault.org,  atish.patra@wdc.com,  maz@kernel.org,
	tglx@linutronix.de,  palmer@dabbelt.com,  heiko@sntech.de,
	robh@kernel.org,  linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	 Guo Ren <guoren@linux.alibaba.com>,
	Palmer Dabbelt <palmerdabbelt@google.com>
Subject: Re: [PATCH V4 2/3] dt-bindings: update riscv plic compatible string
Date: Sat, 16 Oct 2021 09:07:22 +0200	[thread overview]
Message-ID: <87mtn9mor9.fsf@linux-m68k.org> (raw)
In-Reply-To: <20211016032200.2869998-3-guoren@kernel.org> (guoren@kernel.org's message of "Sat, 16 Oct 2021 11:21:59 +0800")

On Okt 16 2021, guoren@kernel.org wrote:

> +  The C9xx PLIC does not comply with the interrupt claim/completion process defined
> +  by the RISC-V PLIC specification because C9xx PLIC will mask an IRQ when it is
> +  claimed by PLIC driver (i.e. readl(claim) and the IRQ will be unmasked upon
> +  completion by PLIC driver (i.e. writel(claim). This behaviour breaks the handling

Missing close paren in both parenthetical remarks above.

Andreas.

-- 
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
"And now for something completely different."

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WARNING: multiple messages have this Message-ID (diff)
From: Andreas Schwab <schwab@linux-m68k.org>
To: guoren@kernel.org
Cc: anup@brainfault.org, atish.patra@wdc.com, maz@kernel.org,
	tglx@linutronix.de, palmer@dabbelt.com, heiko@sntech.de,
	robh@kernel.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	Guo Ren <guoren@linux.alibaba.com>,
	Palmer Dabbelt <palmerdabbelt@google.com>
Subject: Re: [PATCH V4 2/3] dt-bindings: update riscv plic compatible string
Date: Sat, 16 Oct 2021 09:07:22 +0200	[thread overview]
Message-ID: <87mtn9mor9.fsf@linux-m68k.org> (raw)
In-Reply-To: <20211016032200.2869998-3-guoren@kernel.org> (guoren@kernel.org's message of "Sat, 16 Oct 2021 11:21:59 +0800")

On Okt 16 2021, guoren@kernel.org wrote:

> +  The C9xx PLIC does not comply with the interrupt claim/completion process defined
> +  by the RISC-V PLIC specification because C9xx PLIC will mask an IRQ when it is
> +  claimed by PLIC driver (i.e. readl(claim) and the IRQ will be unmasked upon
> +  completion by PLIC driver (i.e. writel(claim). This behaviour breaks the handling

Missing close paren in both parenthetical remarks above.

Andreas.

-- 
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
"And now for something completely different."

  reply	other threads:[~2021-10-16  7:07 UTC|newest]

Thread overview: 68+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-16  3:21 [PATCH V4 0/3] irqchip: riscv: Add thead,c900-plic support guoren
2021-10-16  3:21 ` guoren
2021-10-16  3:21 ` [PATCH V4 1/3] irqchip/sifive-plic: " guoren
2021-10-16  3:21   ` guoren
2021-10-18  5:17   ` Samuel Holland
2021-10-18  5:17     ` Samuel Holland
2021-10-18  5:40     ` Anup Patel
2021-10-18  5:40       ` Anup Patel
2021-10-18  7:05     ` Guo Ren
2021-10-18  7:05       ` Guo Ren
2021-10-18  7:21     ` Marc Zyngier
2021-10-18  7:21       ` Marc Zyngier
2021-10-19  9:33       ` Guo Ren
2021-10-19  9:33         ` Guo Ren
2021-10-19 10:18         ` Marc Zyngier
2021-10-19 10:18           ` Marc Zyngier
2021-10-19 13:27           ` Guo Ren
2021-10-19 13:27             ` Guo Ren
2021-10-20 13:34             ` Marc Zyngier
2021-10-20 13:34               ` Marc Zyngier
2021-10-20 14:19               ` Guo Ren
2021-10-20 14:19                 ` Guo Ren
2021-10-20 14:59                 ` Darius Rad
2021-10-20 14:59                   ` Darius Rad
2021-10-20 16:18                   ` Anup Patel
2021-10-20 16:18                     ` Anup Patel
2021-10-20 18:01                     ` Darius Rad
2021-10-20 18:01                       ` Darius Rad
2021-10-21  8:47                       ` Anup Patel
2021-10-21  8:47                         ` Anup Patel
2021-10-20 14:33               ` Anup Patel
2021-10-20 14:33                 ` Anup Patel
2021-10-20 15:08                 ` Marc Zyngier
2021-10-20 15:08                   ` Marc Zyngier
2021-10-20 16:08                   ` Anup Patel
2021-10-20 16:08                     ` Anup Patel
2021-10-20 16:48                     ` Marc Zyngier
2021-10-20 16:48                       ` Marc Zyngier
2021-10-21  8:52                       ` Anup Patel
2021-10-21  8:52                         ` Anup Patel
2021-10-21  1:46                     ` Guo Ren
2021-10-21  1:46                       ` Guo Ren
2021-10-21  2:00                   ` Guo Ren
2021-10-21  2:00                     ` Guo Ren
2021-10-21  8:33                     ` Marc Zyngier
2021-10-21  8:33                       ` Marc Zyngier
2021-10-21  9:43                       ` Guo Ren
2021-10-21  9:43                         ` Guo Ren
2021-10-16  3:21 ` [PATCH V4 2/3] dt-bindings: update riscv plic compatible string guoren
2021-10-16  3:21   ` guoren
2021-10-16  7:07   ` Andreas Schwab [this message]
2021-10-16  7:07     ` Andreas Schwab
2021-10-16  9:16     ` Guo Ren
2021-10-16  9:16       ` Guo Ren
2021-10-16 10:34   ` Heiko Stuebner
2021-10-16 10:34     ` Heiko Stuebner
2021-10-16 12:56     ` Guo Ren
2021-10-16 12:56       ` Guo Ren
2021-10-16 16:31       ` Heiko Stuebner
2021-10-16 16:31         ` Heiko Stuebner
2021-10-20 12:15         ` Guo Ren
2021-10-20 12:15           ` Guo Ren
2021-10-18 12:02   ` Rob Herring
2021-10-18 12:02     ` Rob Herring
2021-10-19  0:55     ` Guo Ren
2021-10-19  0:55       ` Guo Ren
2021-10-16  3:22 ` [PATCH V4 3/3] dt-bindings: vendor-prefixes: add T-Head Semiconductor guoren
2021-10-16  3:22   ` guoren

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