From: "Marek Behún" <kabel@kernel.org>
To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Sasha Levin <sashal@kernel.org>
Cc: pali@kernel.org, stable@vger.kernel.org,
"Marek Behún" <marek.behun@nic.cz>,
"Remi Pommarel" <repk@triplefau.lt>,
"Tomasz Maciej Nowak" <tmn505@gmail.com>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Gregory CLEMENT" <gregory.clement@bootlin.com>,
"Marek Behún" <kabel@kernel.org>
Subject: [PATCH 5.4 22/22] arm64: dts: marvell: armada-37xx: Set pcie_reset_pin to gpio function
Date: Thu, 25 Nov 2021 01:26:16 +0100 [thread overview]
Message-ID: <20211125002616.31363-23-kabel@kernel.org> (raw)
In-Reply-To: <20211125002616.31363-1-kabel@kernel.org>
From: Marek Behún <marek.behun@nic.cz>
commit 715878016984b2617f6c1f177c50039e12e7bd5b upstream.
We found out that we are unable to control the PERST# signal via the
default pin dedicated to be PERST# pin (GPIO2[3] pin) on A3700 SOC when
this pin is in EP_PCIE1_Resetn mode. There is a register in the PCIe
register space called PERSTN_GPIO_EN (D0088004[3]), but changing the
value of this register does not change the pin output when measuring
with voltmeter.
We do not know if this is a bug in the SOC, or if it works only when
PCIe controller is in a certain state.
Commit f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready
before training link") says that when this pin changes pinctrl mode
from EP_PCIE1_Resetn to GPIO, the PERST# signal is asserted for a brief
moment.
So currently the situation is that on A3700 boards the PERST# signal is
asserted in U-Boot (because the code in U-Boot issues reset via this pin
via GPIO mode), and then in Linux by the obscure and undocumented
mechanism described by the above mentioned commit.
We want to issue PERST# signal in a known way, therefore this patch
changes the pcie_reset_pin function from "pcie" to "gpio" and adds the
reset-gpios property to the PCIe node in device tree files of
EspressoBin and Armada 3720 Dev Board (Turris Mox device tree already
has this property and uDPU does not have a PCIe port).
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Remi Pommarel <repk@triplefau.lt>
Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Marek Behún <kabel@kernel.org>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 3 +++
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 1 +
arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 4 ----
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index f2cc00594d64..3e5789f37206 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -128,6 +128,9 @@
/* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */
&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
+ reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
index 6226e7e80980..a75bb2ea3506 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
@@ -59,6 +59,7 @@
phys = <&comphy1 0>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
+ reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
};
/* J6 */
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
index de0eabff2935..16e73597bb78 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
@@ -127,10 +127,6 @@
};
};
-&pcie_reset_pins {
- function = "gpio";
-};
-
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index c28611c1c251..3d15e4ab3f53 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -318,7 +318,7 @@
pcie_reset_pins: pcie-reset-pins {
groups = "pcie1";
- function = "pcie";
+ function = "gpio";
};
pcie_clkreq_pins: pcie-clkreq-pins {
--
2.32.0
next prev parent reply other threads:[~2021-11-25 0:32 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-25 0:25 [PATCH 5.4 00/22] Armada 3720 PCIe fixes for 5.4 Marek Behún
2021-11-25 0:25 ` [PATCH 5.4 01/22] PCI: aardvark: Wait for endpoint to be ready before training link Marek Behún
2021-11-25 0:25 ` [PATCH 5.4 02/22] PCI: aardvark: Fix big endian support Marek Behún
2021-11-25 0:25 ` [PATCH 5.4 03/22] PCI: aardvark: Train link immediately after enabling training Marek Behún
2021-11-25 0:25 ` [PATCH 5.4 04/22] PCI: aardvark: Improve link training Marek Behún
2021-11-25 0:25 ` [PATCH 5.4 05/22] PCI: aardvark: Issue PERST via GPIO Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 06/22] PCI: aardvark: Replace custom macros by standard linux/pci_regs.h macros Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 07/22] PCI: aardvark: Don't touch PCIe registers if no card connected Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 08/22] PCI: aardvark: Fix compilation on s390 Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 09/22] PCI: aardvark: Move PCIe reset card code to advk_pcie_train_link() Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 10/22] PCI: aardvark: Update comment about disabling link training Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 11/22] PCI: pci-bridge-emul: Fix array overruns, improve safety Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 12/22] PCI: aardvark: Configure PCIe resources from 'ranges' DT property Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 13/22] PCI: aardvark: Fix PCIe Max Payload Size setting Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 14/22] PCI: aardvark: Deduplicate code in advk_pcie_rd_conf() Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 15/22] PCI: aardvark: Implement re-issuing config requests on CRS response Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 16/22] PCI: aardvark: Simplify initialization of rootcap on virtual bridge Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 17/22] PCI: aardvark: Fix link training Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 18/22] PCI: aardvark: Fix support for bus mastering and PCI_COMMAND on emulated bridge Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 19/22] PCI: aardvark: Set PCI Bridge Class Code to PCI Bridge Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 20/22] PCI: aardvark: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridge Marek Behún
2021-11-25 0:26 ` [PATCH 5.4 21/22] pinctrl: armada-37xx: Correct PWM pins definitions Marek Behún
2021-11-25 0:26 ` Marek Behún [this message]
2021-11-28 13:00 ` [PATCH 5.4 00/22] Armada 3720 PCIe fixes for 5.4 Greg Kroah-Hartman
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211125002616.31363-23-kabel@kernel.org \
--to=kabel@kernel.org \
--cc=gregkh@linuxfoundation.org \
--cc=gregory.clement@bootlin.com \
--cc=marek.behun@nic.cz \
--cc=pali@kernel.org \
--cc=repk@triplefau.lt \
--cc=sashal@kernel.org \
--cc=stable@vger.kernel.org \
--cc=thomas.petazzoni@bootlin.com \
--cc=tmn505@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.