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From: Reiji Watanabe <reijiw@google.com>
To: Marc Zyngier <maz@kernel.org>, kvmarm@lists.cs.columbia.edu
Cc: kvm@vger.kernel.org, Will Deacon <will@kernel.org>,
	Peter Shier <pshier@google.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH v4 17/26] KVM: arm64: Use vcpu->arch cptr_el2 to track value of cptr_el2 for VHE
Date: Wed,  5 Jan 2022 20:26:59 -0800	[thread overview]
Message-ID: <20220106042708.2869332-18-reijiw@google.com> (raw)
In-Reply-To: <20220106042708.2869332-1-reijiw@google.com>

Track the baseline guest value for cptr_el2 in struct kvm_vcpu_arch
for VHE.  Use this value when setting cptr_el2 for the guest.

Currently this value is unchanged, but the following patches will set
trapping bits based on features supported for the guest.

No functional change intended.

Signed-off-by: Reiji Watanabe <reijiw@google.com>
---
 arch/arm64/include/asm/kvm_arm.h | 16 ++++++++++++++++
 arch/arm64/kvm/arm.c             |  5 ++++-
 arch/arm64/kvm/hyp/vhe/switch.c  | 14 ++------------
 3 files changed, 22 insertions(+), 13 deletions(-)

diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index 01d47c5886dc..8ab6ea038721 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -288,6 +288,22 @@
 				 GENMASK(19, 14) |	\
 				 BIT(11))
 
+/*
+ * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to
+ * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2,
+ * except for some missing controls, such as TAM.
+ * In this case, CPTR_EL2.TAM has the same position with or without
+ * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM
+ * shift value for trapping the AMU accesses.
+ */
+#define CPTR_EL2_VHE_GUEST_DEFAULT	(CPACR_EL1_TTA | CPTR_EL2_TAM)
+
+/*
+ * Bits that are copied from vcpu->arch.cptr_el2 to set cptr_el2 for
+ * guest with VHE.
+ */
+#define CPTR_EL2_VHE_GUEST_TRACKED_MASK	(CPACR_EL1_TTA | CPTR_EL2_TAM)
+
 /* Hyp Debug Configuration Register bits */
 #define MDCR_EL2_E2TB_MASK	(UL(0x3))
 #define MDCR_EL2_E2TB_SHIFT	(UL(24))
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index 876f2777acf2..3700144f6271 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -1136,7 +1136,10 @@ static int kvm_arch_vcpu_ioctl_vcpu_init(struct kvm_vcpu *vcpu,
 	}
 
 	vcpu_reset_hcr(vcpu);
-	vcpu->arch.cptr_el2 = CPTR_EL2_DEFAULT;
+	if (has_vhe())
+		vcpu->arch.cptr_el2 = CPTR_EL2_VHE_GUEST_DEFAULT;
+	else
+		vcpu->arch.cptr_el2 = CPTR_EL2_DEFAULT;
 
 	/*
 	 * Handle the "start in power-off" case.
diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switch.c
index fbb26b93c347..572b2669ae84 100644
--- a/arch/arm64/kvm/hyp/vhe/switch.c
+++ b/arch/arm64/kvm/hyp/vhe/switch.c
@@ -38,20 +38,10 @@ static void __activate_traps(struct kvm_vcpu *vcpu)
 	___activate_traps(vcpu);
 
 	val = read_sysreg(cpacr_el1);
-	val |= CPACR_EL1_TTA;
+	val &= ~CPTR_EL2_VHE_GUEST_TRACKED_MASK;
+	val |= (vcpu->arch.cptr_el2 & CPTR_EL2_VHE_GUEST_TRACKED_MASK);
 	val &= ~CPACR_EL1_ZEN;
 
-	/*
-	 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to
-	 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2,
-	 * except for some missing controls, such as TAM.
-	 * In this case, CPTR_EL2.TAM has the same position with or without
-	 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM
-	 * shift value for trapping the AMU accesses.
-	 */
-
-	val |= CPTR_EL2_TAM;
-
 	if (update_fp_enabled(vcpu)) {
 		if (vcpu_has_sve(vcpu))
 			val |= CPACR_EL1_ZEN;
-- 
2.34.1.448.ga2b2bfdf31-goog

_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

WARNING: multiple messages have this Message-ID (diff)
From: Reiji Watanabe <reijiw@google.com>
To: Marc Zyngier <maz@kernel.org>, kvmarm@lists.cs.columbia.edu
Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	 James Morse <james.morse@arm.com>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Will Deacon <will@kernel.org>, Andrew Jones <drjones@redhat.com>,
	 Peng Liang <liangpeng10@huawei.com>,
	Peter Shier <pshier@google.com>,
	 Ricardo Koller <ricarkol@google.com>,
	Oliver Upton <oupton@google.com>,
	 Jing Zhang <jingzhangos@google.com>,
	Raghavendra Rao Anata <rananta@google.com>,
	Reiji Watanabe <reijiw@google.com>
Subject: [RFC PATCH v4 17/26] KVM: arm64: Use vcpu->arch cptr_el2 to track value of cptr_el2 for VHE
Date: Wed,  5 Jan 2022 20:26:59 -0800	[thread overview]
Message-ID: <20220106042708.2869332-18-reijiw@google.com> (raw)
In-Reply-To: <20220106042708.2869332-1-reijiw@google.com>

Track the baseline guest value for cptr_el2 in struct kvm_vcpu_arch
for VHE.  Use this value when setting cptr_el2 for the guest.

Currently this value is unchanged, but the following patches will set
trapping bits based on features supported for the guest.

No functional change intended.

Signed-off-by: Reiji Watanabe <reijiw@google.com>
---
 arch/arm64/include/asm/kvm_arm.h | 16 ++++++++++++++++
 arch/arm64/kvm/arm.c             |  5 ++++-
 arch/arm64/kvm/hyp/vhe/switch.c  | 14 ++------------
 3 files changed, 22 insertions(+), 13 deletions(-)

diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index 01d47c5886dc..8ab6ea038721 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -288,6 +288,22 @@
 				 GENMASK(19, 14) |	\
 				 BIT(11))
 
+/*
+ * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to
+ * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2,
+ * except for some missing controls, such as TAM.
+ * In this case, CPTR_EL2.TAM has the same position with or without
+ * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM
+ * shift value for trapping the AMU accesses.
+ */
+#define CPTR_EL2_VHE_GUEST_DEFAULT	(CPACR_EL1_TTA | CPTR_EL2_TAM)
+
+/*
+ * Bits that are copied from vcpu->arch.cptr_el2 to set cptr_el2 for
+ * guest with VHE.
+ */
+#define CPTR_EL2_VHE_GUEST_TRACKED_MASK	(CPACR_EL1_TTA | CPTR_EL2_TAM)
+
 /* Hyp Debug Configuration Register bits */
 #define MDCR_EL2_E2TB_MASK	(UL(0x3))
 #define MDCR_EL2_E2TB_SHIFT	(UL(24))
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index 876f2777acf2..3700144f6271 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -1136,7 +1136,10 @@ static int kvm_arch_vcpu_ioctl_vcpu_init(struct kvm_vcpu *vcpu,
 	}
 
 	vcpu_reset_hcr(vcpu);
-	vcpu->arch.cptr_el2 = CPTR_EL2_DEFAULT;
+	if (has_vhe())
+		vcpu->arch.cptr_el2 = CPTR_EL2_VHE_GUEST_DEFAULT;
+	else
+		vcpu->arch.cptr_el2 = CPTR_EL2_DEFAULT;
 
 	/*
 	 * Handle the "start in power-off" case.
diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switch.c
index fbb26b93c347..572b2669ae84 100644
--- a/arch/arm64/kvm/hyp/vhe/switch.c
+++ b/arch/arm64/kvm/hyp/vhe/switch.c
@@ -38,20 +38,10 @@ static void __activate_traps(struct kvm_vcpu *vcpu)
 	___activate_traps(vcpu);
 
 	val = read_sysreg(cpacr_el1);
-	val |= CPACR_EL1_TTA;
+	val &= ~CPTR_EL2_VHE_GUEST_TRACKED_MASK;
+	val |= (vcpu->arch.cptr_el2 & CPTR_EL2_VHE_GUEST_TRACKED_MASK);
 	val &= ~CPACR_EL1_ZEN;
 
-	/*
-	 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to
-	 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2,
-	 * except for some missing controls, such as TAM.
-	 * In this case, CPTR_EL2.TAM has the same position with or without
-	 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM
-	 * shift value for trapping the AMU accesses.
-	 */
-
-	val |= CPTR_EL2_TAM;
-
 	if (update_fp_enabled(vcpu)) {
 		if (vcpu_has_sve(vcpu))
 			val |= CPACR_EL1_ZEN;
-- 
2.34.1.448.ga2b2bfdf31-goog


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Reiji Watanabe <reijiw@google.com>
To: Marc Zyngier <maz@kernel.org>, kvmarm@lists.cs.columbia.edu
Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	James Morse <james.morse@arm.com>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Will Deacon <will@kernel.org>, Andrew Jones <drjones@redhat.com>,
	Peng Liang <liangpeng10@huawei.com>,
	Peter Shier <pshier@google.com>,
	Ricardo Koller <ricarkol@google.com>,
	Oliver Upton <oupton@google.com>,
	Jing Zhang <jingzhangos@google.com>,
	Raghavendra Rao Anata <rananta@google.com>,
	Reiji Watanabe <reijiw@google.com>
Subject: [RFC PATCH v4 17/26] KVM: arm64: Use vcpu->arch cptr_el2 to track value of cptr_el2 for VHE
Date: Wed,  5 Jan 2022 20:26:59 -0800	[thread overview]
Message-ID: <20220106042708.2869332-18-reijiw@google.com> (raw)
In-Reply-To: <20220106042708.2869332-1-reijiw@google.com>

Track the baseline guest value for cptr_el2 in struct kvm_vcpu_arch
for VHE.  Use this value when setting cptr_el2 for the guest.

Currently this value is unchanged, but the following patches will set
trapping bits based on features supported for the guest.

No functional change intended.

Signed-off-by: Reiji Watanabe <reijiw@google.com>
---
 arch/arm64/include/asm/kvm_arm.h | 16 ++++++++++++++++
 arch/arm64/kvm/arm.c             |  5 ++++-
 arch/arm64/kvm/hyp/vhe/switch.c  | 14 ++------------
 3 files changed, 22 insertions(+), 13 deletions(-)

diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index 01d47c5886dc..8ab6ea038721 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -288,6 +288,22 @@
 				 GENMASK(19, 14) |	\
 				 BIT(11))
 
+/*
+ * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to
+ * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2,
+ * except for some missing controls, such as TAM.
+ * In this case, CPTR_EL2.TAM has the same position with or without
+ * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM
+ * shift value for trapping the AMU accesses.
+ */
+#define CPTR_EL2_VHE_GUEST_DEFAULT	(CPACR_EL1_TTA | CPTR_EL2_TAM)
+
+/*
+ * Bits that are copied from vcpu->arch.cptr_el2 to set cptr_el2 for
+ * guest with VHE.
+ */
+#define CPTR_EL2_VHE_GUEST_TRACKED_MASK	(CPACR_EL1_TTA | CPTR_EL2_TAM)
+
 /* Hyp Debug Configuration Register bits */
 #define MDCR_EL2_E2TB_MASK	(UL(0x3))
 #define MDCR_EL2_E2TB_SHIFT	(UL(24))
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index 876f2777acf2..3700144f6271 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -1136,7 +1136,10 @@ static int kvm_arch_vcpu_ioctl_vcpu_init(struct kvm_vcpu *vcpu,
 	}
 
 	vcpu_reset_hcr(vcpu);
-	vcpu->arch.cptr_el2 = CPTR_EL2_DEFAULT;
+	if (has_vhe())
+		vcpu->arch.cptr_el2 = CPTR_EL2_VHE_GUEST_DEFAULT;
+	else
+		vcpu->arch.cptr_el2 = CPTR_EL2_DEFAULT;
 
 	/*
 	 * Handle the "start in power-off" case.
diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switch.c
index fbb26b93c347..572b2669ae84 100644
--- a/arch/arm64/kvm/hyp/vhe/switch.c
+++ b/arch/arm64/kvm/hyp/vhe/switch.c
@@ -38,20 +38,10 @@ static void __activate_traps(struct kvm_vcpu *vcpu)
 	___activate_traps(vcpu);
 
 	val = read_sysreg(cpacr_el1);
-	val |= CPACR_EL1_TTA;
+	val &= ~CPTR_EL2_VHE_GUEST_TRACKED_MASK;
+	val |= (vcpu->arch.cptr_el2 & CPTR_EL2_VHE_GUEST_TRACKED_MASK);
 	val &= ~CPACR_EL1_ZEN;
 
-	/*
-	 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to
-	 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2,
-	 * except for some missing controls, such as TAM.
-	 * In this case, CPTR_EL2.TAM has the same position with or without
-	 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM
-	 * shift value for trapping the AMU accesses.
-	 */
-
-	val |= CPTR_EL2_TAM;
-
 	if (update_fp_enabled(vcpu)) {
 		if (vcpu_has_sve(vcpu))
 			val |= CPACR_EL1_ZEN;
-- 
2.34.1.448.ga2b2bfdf31-goog


  parent reply	other threads:[~2022-01-06  4:29 UTC|newest]

Thread overview: 201+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-06  4:26 [RFC PATCH v4 00/26] KVM: arm64: Make CPU ID registers writable by userspace Reiji Watanabe
2022-01-06  4:26 ` Reiji Watanabe
2022-01-06  4:26 ` Reiji Watanabe
2022-01-06  4:26 ` [RFC PATCH v4 01/26] KVM: arm64: Introduce a validation function for an ID register Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-07  7:12   ` Reiji Watanabe
2022-01-07  7:12     ` Reiji Watanabe
2022-01-07  7:12     ` Reiji Watanabe
2022-01-24 16:20   ` Fuad Tabba
2022-01-24 16:20     ` Fuad Tabba
2022-01-24 16:20     ` Fuad Tabba
2022-01-26  6:04     ` Reiji Watanabe
2022-01-26  6:04       ` Reiji Watanabe
2022-01-26  6:04       ` Reiji Watanabe
2022-02-01 14:13       ` Fuad Tabba
2022-02-01 14:13         ` Fuad Tabba
2022-02-01 14:13         ` Fuad Tabba
2022-02-02  6:46         ` Reiji Watanabe
2022-02-02  6:46           ` Reiji Watanabe
2022-02-02  6:46           ` Reiji Watanabe
2022-01-26  4:30   ` Ricardo Koller
2022-01-26  4:30     ` Ricardo Koller
2022-01-26  4:30     ` Ricardo Koller
2022-01-28  6:01     ` Reiji Watanabe
2022-01-28  6:01       ` Reiji Watanabe
2022-01-28  6:01       ` Reiji Watanabe
2022-01-06  4:26 ` [RFC PATCH v4 02/26] KVM: arm64: Save ID registers' sanitized value per guest Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-24 16:21   ` Fuad Tabba
2022-01-24 16:21     ` Fuad Tabba
2022-01-24 16:21     ` Fuad Tabba
2022-02-09  2:26     ` Reiji Watanabe
2022-02-09  2:26       ` Reiji Watanabe
2022-02-09  2:26       ` Reiji Watanabe
2022-01-26  5:22   ` Ricardo Koller
2022-01-26  5:22     ` Ricardo Koller
2022-01-26  5:22     ` Ricardo Koller
2022-01-28  6:24     ` Reiji Watanabe
2022-01-28  6:24       ` Reiji Watanabe
2022-01-28  6:24       ` Reiji Watanabe
2022-01-28 19:27       ` Ricardo Koller
2022-01-28 19:27         ` Ricardo Koller
2022-01-28 19:27         ` Ricardo Koller
2022-01-29  5:52         ` Reiji Watanabe
2022-01-29  5:52           ` Reiji Watanabe
2022-01-29  5:52           ` Reiji Watanabe
2022-01-31  3:40           ` Ricardo Koller
2022-01-31  3:40             ` Ricardo Koller
2022-01-31  3:40             ` Ricardo Koller
2022-02-01  6:00             ` Reiji Watanabe
2022-02-01  6:00               ` Reiji Watanabe
2022-02-01  6:00               ` Reiji Watanabe
2022-02-01 18:38               ` Ricardo Koller
2022-02-01 18:38                 ` Ricardo Koller
2022-02-01 18:38                 ` Ricardo Koller
2022-02-03  6:31                 ` Reiji Watanabe
2022-02-03  6:31                   ` Reiji Watanabe
2022-02-03  6:31                   ` Reiji Watanabe
2022-02-04 14:41                   ` Ricardo Koller
2022-02-04 14:41                     ` Ricardo Koller
2022-02-04 14:41                     ` Ricardo Koller
2022-01-06  4:26 ` [RFC PATCH v4 03/26] KVM: arm64: Introduce struct id_reg_info Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-24 16:28   ` Fuad Tabba
2022-01-24 16:28     ` Fuad Tabba
2022-01-24 16:28     ` Fuad Tabba
2022-01-26  6:46     ` Reiji Watanabe
2022-01-26  6:46       ` Reiji Watanabe
2022-01-26  6:46       ` Reiji Watanabe
2022-02-01 14:13       ` Fuad Tabba
2022-02-01 14:13         ` Fuad Tabba
2022-02-01 14:13         ` Fuad Tabba
2022-01-06  4:26 ` [RFC PATCH v4 04/26] KVM: arm64: Make ID_AA64PFR0_EL1 writable Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-24 16:51   ` Fuad Tabba
2022-01-24 16:51     ` Fuad Tabba
2022-01-24 16:51     ` Fuad Tabba
2022-01-27  4:01     ` Reiji Watanabe
2022-01-27  4:01       ` Reiji Watanabe
2022-01-27  4:01       ` Reiji Watanabe
2022-02-01 14:14       ` Fuad Tabba
2022-02-01 14:14         ` Fuad Tabba
2022-02-01 14:14         ` Fuad Tabba
2022-02-10  5:33         ` Reiji Watanabe
2022-02-10  5:33           ` Reiji Watanabe
2022-02-10  5:33           ` Reiji Watanabe
2022-01-06  4:26 ` [RFC PATCH v4 05/26] KVM: arm64: Make ID_AA64PFR1_EL1 writable Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26 ` [RFC PATCH v4 06/26] KVM: arm64: Make ID_AA64ISAR0_EL1 writable Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26 ` [RFC PATCH v4 07/26] KVM: arm64: Make ID_AA64ISAR1_EL1 writable Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26 ` [RFC PATCH v4 08/26] KVM: arm64: Make ID_AA64MMFR0_EL1 writable Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26 ` [RFC PATCH v4 09/26] KVM: arm64: Hide IMPLEMENTATION DEFINED PMU support for the guest Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26 ` [RFC PATCH v4 10/26] KVM: arm64: Make ID_AA64DFR0_EL1 writable Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26 ` [RFC PATCH v4 11/26] KVM: arm64: Make ID_DFR0_EL1 writable Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26 ` [RFC PATCH v4 12/26] KVM: arm64: Make MVFR1_EL1 writable Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26 ` [RFC PATCH v4 13/26] KVM: arm64: Make ID registers without id_reg_info writable Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26 ` [RFC PATCH v4 14/26] KVM: arm64: Add consistency checking for frac fields of ID registers Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-24 17:00   ` Fuad Tabba
2022-01-24 17:00     ` Fuad Tabba
2022-01-24 17:00     ` Fuad Tabba
2022-01-27  5:03     ` Reiji Watanabe
2022-01-27  5:03       ` Reiji Watanabe
2022-01-27  5:03       ` Reiji Watanabe
2022-01-06  4:26 ` [RFC PATCH v4 15/26] KVM: arm64: Introduce KVM_CAP_ARM_ID_REG_CONFIGURABLE capability Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26 ` [RFC PATCH v4 16/26] KVM: arm64: Add kunit test for ID register validation Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:26 ` Reiji Watanabe [this message]
2022-01-06  4:26   ` [RFC PATCH v4 17/26] KVM: arm64: Use vcpu->arch cptr_el2 to track value of cptr_el2 for VHE Reiji Watanabe
2022-01-06  4:26   ` Reiji Watanabe
2022-01-06  4:27 ` [RFC PATCH v4 18/26] KVM: arm64: Use vcpu->arch.mdcr_el2 to track value of mdcr_el2 Reiji Watanabe
2022-01-06  4:27   ` Reiji Watanabe
2022-01-06  4:27   ` Reiji Watanabe
2022-01-06  4:27 ` [RFC PATCH v4 19/26] KVM: arm64: Introduce framework to trap disabled features Reiji Watanabe
2022-01-06  4:27   ` Reiji Watanabe
2022-01-06  4:27   ` Reiji Watanabe
2022-01-06  4:27 ` [RFC PATCH v4 20/26] KVM: arm64: Trap disabled features of ID_AA64PFR0_EL1 Reiji Watanabe
2022-01-06  4:27   ` Reiji Watanabe
2022-01-06  4:27   ` Reiji Watanabe
2022-01-24 17:16   ` Fuad Tabba
2022-01-24 17:16     ` Fuad Tabba
2022-01-24 17:16     ` Fuad Tabba
2022-01-27  7:19     ` Reiji Watanabe
2022-01-27  7:19       ` Reiji Watanabe
2022-01-27  7:19       ` Reiji Watanabe
2022-02-01 14:14       ` Fuad Tabba
2022-02-01 14:14         ` Fuad Tabba
2022-02-01 14:14         ` Fuad Tabba
2022-02-10  4:15         ` Reiji Watanabe
2022-02-10  4:15           ` Reiji Watanabe
2022-02-10  4:15           ` Reiji Watanabe
2022-01-06  4:27 ` [RFC PATCH v4 21/26] KVM: arm64: Trap disabled features of ID_AA64PFR1_EL1 Reiji Watanabe
2022-01-06  4:27   ` Reiji Watanabe
2022-01-06  4:27   ` Reiji Watanabe
2022-01-06  4:27 ` [RFC PATCH v4 22/26] KVM: arm64: Trap disabled features of ID_AA64DFR0_EL1 Reiji Watanabe
2022-01-06  4:27   ` Reiji Watanabe
2022-01-06  4:27   ` Reiji Watanabe
2022-01-24 17:19   ` Fuad Tabba
2022-01-24 17:19     ` Fuad Tabba
2022-01-24 17:19     ` Fuad Tabba
2022-01-28  5:40     ` Reiji Watanabe
2022-01-28  5:40       ` Reiji Watanabe
2022-01-28  5:40       ` Reiji Watanabe
2022-01-06  4:27 ` [RFC PATCH v4 23/26] KVM: arm64: Trap disabled features of ID_AA64MMFR1_EL1 Reiji Watanabe
2022-01-06  4:27   ` Reiji Watanabe
2022-01-06  4:27   ` Reiji Watanabe
2022-01-24 17:37   ` Fuad Tabba
2022-01-24 17:37     ` Fuad Tabba
2022-01-24 17:37     ` Fuad Tabba
2022-01-28  5:43     ` Reiji Watanabe
2022-01-28  5:43       ` Reiji Watanabe
2022-01-28  5:43       ` Reiji Watanabe
2022-02-09  4:51       ` Reiji Watanabe
2022-02-09  4:51         ` Reiji Watanabe
2022-02-09  4:51         ` Reiji Watanabe
2022-01-06  4:27 ` [RFC PATCH v4 24/26] KVM: arm64: Trap disabled features of ID_AA64ISAR1_EL1 Reiji Watanabe
2022-01-06  4:27   ` Reiji Watanabe
2022-01-06  4:27   ` Reiji Watanabe
2022-01-06  4:27 ` [RFC PATCH v4 25/26] KVM: arm64: Add kunit test for trap initialization Reiji Watanabe
2022-01-06  4:27   ` Reiji Watanabe
2022-01-06  4:27   ` Reiji Watanabe
2022-01-06  4:27 ` [RFC PATCH v4 26/26] KVM: arm64: selftests: Introduce id_reg_test Reiji Watanabe
2022-01-06  4:27   ` Reiji Watanabe
2022-01-06  4:27   ` Reiji Watanabe
2022-01-18  4:24 ` [RFC PATCH v4 00/26] KVM: arm64: Make CPU ID registers writable by userspace Reiji Watanabe
2022-01-18  4:24   ` Reiji Watanabe
2022-01-18  4:24   ` Reiji Watanabe
2022-01-24 16:18 ` Fuad Tabba
2022-01-24 16:18   ` Fuad Tabba
2022-01-24 16:18   ` Fuad Tabba
2022-01-25  6:31   ` Reiji Watanabe
2022-01-25  6:31     ` Reiji Watanabe
2022-01-25  6:31     ` Reiji Watanabe
2022-02-01 14:12     ` Fuad Tabba
2022-02-01 14:12       ` Fuad Tabba
2022-02-01 14:12       ` Fuad Tabba

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