From: Guillaume Ranquet <granquet@baylibre.com>
To: Rob Herring <robh+dt@kernel.org>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
Jitao shi <jitao.shi@mediatek.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Vinod Koul <vkoul@kernel.org>, CK Hu <ck.hu@mediatek.com>,
Daniel Vetter <daniel@ffwll.ch>, David Airlie <airlied@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Kishon Vijay Abraham I <kishon@ti.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
linux-arm-kernel@lists.infradead.org, stuart.lee@mediatek.com,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org,
Guillaume Ranquet <granquet@baylibre.com>,
mac.shen@mediatek.com, linux-phy@lists.infradead.org
Subject: [PATCH v3 03/12] drm/mediatek: hdmi: use a regmap instead of iomem
Date: Fri, 04 Nov 2022 15:09:49 +0100 [thread overview]
Message-ID: <20220919-v3-3-a803f2660127@baylibre.com> (raw)
In-Reply-To: <20220919-v3-0-a803f2660127@baylibre.com>
To prepare support for newer chips that need to share their address
range with a dedicated ddc driver, use a regmap.
Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 43 +++++++++++--------------------------
1 file changed, 13 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 4c80b6896dc3..9b02b30a193a 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -171,7 +171,7 @@ struct mtk_hdmi {
u32 ibias_up;
struct regmap *sys_regmap;
unsigned int sys_offset;
- void __iomem *regs;
+ struct regmap *regs;
enum hdmi_colorspace csp;
struct hdmi_audio_param aud_param;
bool audio_enable;
@@ -187,44 +187,29 @@ static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
return container_of(b, struct mtk_hdmi, bridge);
}
-static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
+static int mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset, u32 *val)
{
- return readl(hdmi->regs + offset);
+ return regmap_read(hdmi->regs, offset, val);
}
static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
{
- writel(val, hdmi->regs + offset);
+ regmap_write(hdmi->regs, offset, val);
}
static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
{
- void __iomem *reg = hdmi->regs + offset;
- u32 tmp;
-
- tmp = readl(reg);
- tmp &= ~bits;
- writel(tmp, reg);
+ regmap_clear_bits(hdmi->regs, offset, bits);
}
static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
{
- void __iomem *reg = hdmi->regs + offset;
- u32 tmp;
-
- tmp = readl(reg);
- tmp |= bits;
- writel(tmp, reg);
+ regmap_set_bits(hdmi->regs, offset, bits);
}
static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
{
- void __iomem *reg = hdmi->regs + offset;
- u32 tmp;
-
- tmp = readl(reg);
- tmp = (tmp & ~mask) | (val & mask);
- writel(tmp, reg);
+ regmap_update_bits(hdmi->regs, offset, mask, val);
}
static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
@@ -473,7 +458,7 @@ static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_CFG0);
+ mtk_hdmi_read(hdmi, GRL_CFG0, &val);
val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
switch (i2s_fmt) {
@@ -565,7 +550,7 @@ static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_CFG1);
+ mtk_hdmi_read(hdmi, GRL_CFG1, &val);
if (input_type == HDMI_AUD_INPUT_I2S &&
(val & CFG1_SPDIF) == CFG1_SPDIF) {
val &= ~CFG1_SPDIF;
@@ -596,7 +581,7 @@ static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
+ mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val);
if (val & MIX_CTRL_SRC_EN) {
val &= ~MIX_CTRL_SRC_EN;
mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
@@ -610,7 +595,7 @@ static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
+ mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val);
val &= ~MIX_CTRL_SRC_EN;
mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
@@ -621,7 +606,7 @@ static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_CFG5);
+ mtk_hdmi_read(hdmi, GRL_CFG5, &val);
val &= CFG5_CD_RATIO_MASK;
switch (mclk) {
@@ -1427,7 +1412,6 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
struct device_node *cec_np, *remote, *i2c_np;
struct platform_device *cec_pdev;
struct regmap *regmap;
- struct resource *mem;
int ret;
ret = mtk_hdmi_get_all_clk(hdmi, np);
@@ -1473,8 +1457,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
}
hdmi->sys_regmap = regmap;
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- hdmi->regs = devm_ioremap_resource(dev, mem);
+ hdmi->regs = device_node_to_regmap(dev->of_node);
if (IS_ERR(hdmi->regs)) {
ret = PTR_ERR(hdmi->regs);
goto put_device;
--
b4 0.11.0-dev
WARNING: multiple messages have this Message-ID (diff)
From: Guillaume Ranquet <granquet@baylibre.com>
To: Rob Herring <robh+dt@kernel.org>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
Jitao shi <jitao.shi@mediatek.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Vinod Koul <vkoul@kernel.org>, CK Hu <ck.hu@mediatek.com>,
Daniel Vetter <daniel@ffwll.ch>, David Airlie <airlied@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Kishon Vijay Abraham I <kishon@ti.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
linux-arm-kernel@lists.infradead.org, stuart.lee@mediatek.com,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org,
Guillaume Ranquet <granquet@baylibre.com>,
mac.shen@mediatek.com, linux-phy@lists.infradead.org
Subject: [PATCH v3 03/12] drm/mediatek: hdmi: use a regmap instead of iomem
Date: Fri, 04 Nov 2022 15:09:49 +0100 [thread overview]
Message-ID: <20220919-v3-3-a803f2660127@baylibre.com> (raw)
In-Reply-To: <20220919-v3-0-a803f2660127@baylibre.com>
To prepare support for newer chips that need to share their address
range with a dedicated ddc driver, use a regmap.
Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 43 +++++++++++--------------------------
1 file changed, 13 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 4c80b6896dc3..9b02b30a193a 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -171,7 +171,7 @@ struct mtk_hdmi {
u32 ibias_up;
struct regmap *sys_regmap;
unsigned int sys_offset;
- void __iomem *regs;
+ struct regmap *regs;
enum hdmi_colorspace csp;
struct hdmi_audio_param aud_param;
bool audio_enable;
@@ -187,44 +187,29 @@ static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
return container_of(b, struct mtk_hdmi, bridge);
}
-static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
+static int mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset, u32 *val)
{
- return readl(hdmi->regs + offset);
+ return regmap_read(hdmi->regs, offset, val);
}
static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
{
- writel(val, hdmi->regs + offset);
+ regmap_write(hdmi->regs, offset, val);
}
static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
{
- void __iomem *reg = hdmi->regs + offset;
- u32 tmp;
-
- tmp = readl(reg);
- tmp &= ~bits;
- writel(tmp, reg);
+ regmap_clear_bits(hdmi->regs, offset, bits);
}
static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
{
- void __iomem *reg = hdmi->regs + offset;
- u32 tmp;
-
- tmp = readl(reg);
- tmp |= bits;
- writel(tmp, reg);
+ regmap_set_bits(hdmi->regs, offset, bits);
}
static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
{
- void __iomem *reg = hdmi->regs + offset;
- u32 tmp;
-
- tmp = readl(reg);
- tmp = (tmp & ~mask) | (val & mask);
- writel(tmp, reg);
+ regmap_update_bits(hdmi->regs, offset, mask, val);
}
static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
@@ -473,7 +458,7 @@ static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_CFG0);
+ mtk_hdmi_read(hdmi, GRL_CFG0, &val);
val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
switch (i2s_fmt) {
@@ -565,7 +550,7 @@ static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_CFG1);
+ mtk_hdmi_read(hdmi, GRL_CFG1, &val);
if (input_type == HDMI_AUD_INPUT_I2S &&
(val & CFG1_SPDIF) == CFG1_SPDIF) {
val &= ~CFG1_SPDIF;
@@ -596,7 +581,7 @@ static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
+ mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val);
if (val & MIX_CTRL_SRC_EN) {
val &= ~MIX_CTRL_SRC_EN;
mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
@@ -610,7 +595,7 @@ static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
+ mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val);
val &= ~MIX_CTRL_SRC_EN;
mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
@@ -621,7 +606,7 @@ static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_CFG5);
+ mtk_hdmi_read(hdmi, GRL_CFG5, &val);
val &= CFG5_CD_RATIO_MASK;
switch (mclk) {
@@ -1427,7 +1412,6 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
struct device_node *cec_np, *remote, *i2c_np;
struct platform_device *cec_pdev;
struct regmap *regmap;
- struct resource *mem;
int ret;
ret = mtk_hdmi_get_all_clk(hdmi, np);
@@ -1473,8 +1457,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
}
hdmi->sys_regmap = regmap;
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- hdmi->regs = devm_ioremap_resource(dev, mem);
+ hdmi->regs = device_node_to_regmap(dev->of_node);
if (IS_ERR(hdmi->regs)) {
ret = PTR_ERR(hdmi->regs);
goto put_device;
--
b4 0.11.0-dev
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
WARNING: multiple messages have this Message-ID (diff)
From: Guillaume Ranquet <granquet@baylibre.com>
To: Rob Herring <robh+dt@kernel.org>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
Jitao shi <jitao.shi@mediatek.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Vinod Koul <vkoul@kernel.org>, CK Hu <ck.hu@mediatek.com>,
Daniel Vetter <daniel@ffwll.ch>, David Airlie <airlied@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Kishon Vijay Abraham I <kishon@ti.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
linux-arm-kernel@lists.infradead.org, stuart.lee@mediatek.com,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org,
Guillaume Ranquet <granquet@baylibre.com>,
mac.shen@mediatek.com, linux-phy@lists.infradead.org
Subject: [PATCH v3 03/12] drm/mediatek: hdmi: use a regmap instead of iomem
Date: Fri, 04 Nov 2022 15:09:49 +0100 [thread overview]
Message-ID: <20220919-v3-3-a803f2660127@baylibre.com> (raw)
In-Reply-To: <20220919-v3-0-a803f2660127@baylibre.com>
To prepare support for newer chips that need to share their address
range with a dedicated ddc driver, use a regmap.
Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 43 +++++++++++--------------------------
1 file changed, 13 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 4c80b6896dc3..9b02b30a193a 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -171,7 +171,7 @@ struct mtk_hdmi {
u32 ibias_up;
struct regmap *sys_regmap;
unsigned int sys_offset;
- void __iomem *regs;
+ struct regmap *regs;
enum hdmi_colorspace csp;
struct hdmi_audio_param aud_param;
bool audio_enable;
@@ -187,44 +187,29 @@ static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
return container_of(b, struct mtk_hdmi, bridge);
}
-static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
+static int mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset, u32 *val)
{
- return readl(hdmi->regs + offset);
+ return regmap_read(hdmi->regs, offset, val);
}
static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
{
- writel(val, hdmi->regs + offset);
+ regmap_write(hdmi->regs, offset, val);
}
static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
{
- void __iomem *reg = hdmi->regs + offset;
- u32 tmp;
-
- tmp = readl(reg);
- tmp &= ~bits;
- writel(tmp, reg);
+ regmap_clear_bits(hdmi->regs, offset, bits);
}
static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
{
- void __iomem *reg = hdmi->regs + offset;
- u32 tmp;
-
- tmp = readl(reg);
- tmp |= bits;
- writel(tmp, reg);
+ regmap_set_bits(hdmi->regs, offset, bits);
}
static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
{
- void __iomem *reg = hdmi->regs + offset;
- u32 tmp;
-
- tmp = readl(reg);
- tmp = (tmp & ~mask) | (val & mask);
- writel(tmp, reg);
+ regmap_update_bits(hdmi->regs, offset, mask, val);
}
static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
@@ -473,7 +458,7 @@ static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_CFG0);
+ mtk_hdmi_read(hdmi, GRL_CFG0, &val);
val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
switch (i2s_fmt) {
@@ -565,7 +550,7 @@ static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_CFG1);
+ mtk_hdmi_read(hdmi, GRL_CFG1, &val);
if (input_type == HDMI_AUD_INPUT_I2S &&
(val & CFG1_SPDIF) == CFG1_SPDIF) {
val &= ~CFG1_SPDIF;
@@ -596,7 +581,7 @@ static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
+ mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val);
if (val & MIX_CTRL_SRC_EN) {
val &= ~MIX_CTRL_SRC_EN;
mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
@@ -610,7 +595,7 @@ static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
+ mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val);
val &= ~MIX_CTRL_SRC_EN;
mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
@@ -621,7 +606,7 @@ static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_CFG5);
+ mtk_hdmi_read(hdmi, GRL_CFG5, &val);
val &= CFG5_CD_RATIO_MASK;
switch (mclk) {
@@ -1427,7 +1412,6 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
struct device_node *cec_np, *remote, *i2c_np;
struct platform_device *cec_pdev;
struct regmap *regmap;
- struct resource *mem;
int ret;
ret = mtk_hdmi_get_all_clk(hdmi, np);
@@ -1473,8 +1457,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
}
hdmi->sys_regmap = regmap;
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- hdmi->regs = devm_ioremap_resource(dev, mem);
+ hdmi->regs = device_node_to_regmap(dev->of_node);
if (IS_ERR(hdmi->regs)) {
ret = PTR_ERR(hdmi->regs);
goto put_device;
--
b4 0.11.0-dev
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Guillaume Ranquet <granquet@baylibre.com>
To: Rob Herring <robh+dt@kernel.org>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
Jitao shi <jitao.shi@mediatek.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Vinod Koul <vkoul@kernel.org>, CK Hu <ck.hu@mediatek.com>,
Daniel Vetter <daniel@ffwll.ch>, David Airlie <airlied@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Kishon Vijay Abraham I <kishon@ti.com>
Cc: devicetree@vger.kernel.org,
Guillaume Ranquet <granquet@baylibre.com>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
mac.shen@mediatek.com, stuart.lee@mediatek.com,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
linux-mediatek@lists.infradead.org,
linux-phy@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>
Subject: [PATCH v3 03/12] drm/mediatek: hdmi: use a regmap instead of iomem
Date: Fri, 04 Nov 2022 15:09:49 +0100 [thread overview]
Message-ID: <20220919-v3-3-a803f2660127@baylibre.com> (raw)
In-Reply-To: <20220919-v3-0-a803f2660127@baylibre.com>
To prepare support for newer chips that need to share their address
range with a dedicated ddc driver, use a regmap.
Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
---
drivers/gpu/drm/mediatek/mtk_hdmi.c | 43 +++++++++++--------------------------
1 file changed, 13 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 4c80b6896dc3..9b02b30a193a 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -171,7 +171,7 @@ struct mtk_hdmi {
u32 ibias_up;
struct regmap *sys_regmap;
unsigned int sys_offset;
- void __iomem *regs;
+ struct regmap *regs;
enum hdmi_colorspace csp;
struct hdmi_audio_param aud_param;
bool audio_enable;
@@ -187,44 +187,29 @@ static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
return container_of(b, struct mtk_hdmi, bridge);
}
-static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
+static int mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset, u32 *val)
{
- return readl(hdmi->regs + offset);
+ return regmap_read(hdmi->regs, offset, val);
}
static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
{
- writel(val, hdmi->regs + offset);
+ regmap_write(hdmi->regs, offset, val);
}
static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
{
- void __iomem *reg = hdmi->regs + offset;
- u32 tmp;
-
- tmp = readl(reg);
- tmp &= ~bits;
- writel(tmp, reg);
+ regmap_clear_bits(hdmi->regs, offset, bits);
}
static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
{
- void __iomem *reg = hdmi->regs + offset;
- u32 tmp;
-
- tmp = readl(reg);
- tmp |= bits;
- writel(tmp, reg);
+ regmap_set_bits(hdmi->regs, offset, bits);
}
static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
{
- void __iomem *reg = hdmi->regs + offset;
- u32 tmp;
-
- tmp = readl(reg);
- tmp = (tmp & ~mask) | (val & mask);
- writel(tmp, reg);
+ regmap_update_bits(hdmi->regs, offset, mask, val);
}
static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
@@ -473,7 +458,7 @@ static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_CFG0);
+ mtk_hdmi_read(hdmi, GRL_CFG0, &val);
val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
switch (i2s_fmt) {
@@ -565,7 +550,7 @@ static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_CFG1);
+ mtk_hdmi_read(hdmi, GRL_CFG1, &val);
if (input_type == HDMI_AUD_INPUT_I2S &&
(val & CFG1_SPDIF) == CFG1_SPDIF) {
val &= ~CFG1_SPDIF;
@@ -596,7 +581,7 @@ static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
+ mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val);
if (val & MIX_CTRL_SRC_EN) {
val &= ~MIX_CTRL_SRC_EN;
mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
@@ -610,7 +595,7 @@ static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
+ mtk_hdmi_read(hdmi, GRL_MIX_CTRL, &val);
val &= ~MIX_CTRL_SRC_EN;
mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
@@ -621,7 +606,7 @@ static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
{
u32 val;
- val = mtk_hdmi_read(hdmi, GRL_CFG5);
+ mtk_hdmi_read(hdmi, GRL_CFG5, &val);
val &= CFG5_CD_RATIO_MASK;
switch (mclk) {
@@ -1427,7 +1412,6 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
struct device_node *cec_np, *remote, *i2c_np;
struct platform_device *cec_pdev;
struct regmap *regmap;
- struct resource *mem;
int ret;
ret = mtk_hdmi_get_all_clk(hdmi, np);
@@ -1473,8 +1457,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
}
hdmi->sys_regmap = regmap;
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- hdmi->regs = devm_ioremap_resource(dev, mem);
+ hdmi->regs = device_node_to_regmap(dev->of_node);
if (IS_ERR(hdmi->regs)) {
ret = PTR_ERR(hdmi->regs);
goto put_device;
--
b4 0.11.0-dev
next prev parent reply other threads:[~2022-11-04 15:16 UTC|newest]
Thread overview: 128+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-04 14:09 [PATCH v3 00/12] Add MT8195 HDMI support Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` [PATCH v3 01/12] dt-bindings: phy: mediatek: hdmi-phy: Add mt8195 compatible Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-07 11:20 ` AngeloGioacchino Del Regno
2022-11-07 11:20 ` AngeloGioacchino Del Regno
2022-11-07 11:20 ` AngeloGioacchino Del Regno
2022-11-07 11:20 ` AngeloGioacchino Del Regno
2022-11-07 14:41 ` Guillaume Ranquet
2022-11-07 14:41 ` Guillaume Ranquet
2022-11-07 14:41 ` Guillaume Ranquet
2022-11-07 14:41 ` Guillaume Ranquet
2022-11-04 14:09 ` [PATCH v3 02/12] dt-bindings: display: mediatek: add MT8195 hdmi bindings Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-07 10:02 ` Krzysztof Kozlowski
2022-11-07 10:02 ` Krzysztof Kozlowski
2022-11-07 10:02 ` Krzysztof Kozlowski
2022-11-07 10:02 ` Krzysztof Kozlowski
2022-11-07 14:42 ` Guillaume Ranquet
2022-11-07 14:42 ` Guillaume Ranquet
2022-11-07 14:42 ` Guillaume Ranquet
2022-11-07 14:42 ` Guillaume Ranquet
2022-12-26 5:18 ` CK Hu (胡俊光)
2022-12-26 5:18 ` CK Hu (胡俊光)
2022-12-26 5:18 ` CK Hu (胡俊光)
2022-12-26 5:18 ` CK Hu (胡俊光)
2023-01-02 13:38 ` Guillaume Ranquet
2023-01-02 13:38 ` Guillaume Ranquet
2023-01-02 13:38 ` Guillaume Ranquet
2023-01-02 13:38 ` Guillaume Ranquet
2023-01-02 14:14 ` AngeloGioacchino Del Regno
2023-01-02 14:14 ` AngeloGioacchino Del Regno
2023-01-02 14:14 ` AngeloGioacchino Del Regno
2023-01-02 14:14 ` AngeloGioacchino Del Regno
2023-01-02 15:19 ` Guillaume Ranquet
2023-01-02 15:19 ` Guillaume Ranquet
2023-01-02 15:19 ` Guillaume Ranquet
2023-01-02 15:19 ` Guillaume Ranquet
2023-01-03 10:11 ` AngeloGioacchino Del Regno
2023-01-03 10:11 ` AngeloGioacchino Del Regno
2023-01-03 10:11 ` AngeloGioacchino Del Regno
2023-01-03 10:11 ` AngeloGioacchino Del Regno
2022-11-04 14:09 ` Guillaume Ranquet [this message]
2022-11-04 14:09 ` [PATCH v3 03/12] drm/mediatek: hdmi: use a regmap instead of iomem Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-07 11:20 ` AngeloGioacchino Del Regno
2022-11-07 11:20 ` AngeloGioacchino Del Regno
2022-11-07 11:20 ` AngeloGioacchino Del Regno
2022-11-07 11:20 ` AngeloGioacchino Del Regno
2022-11-07 14:43 ` Guillaume Ranquet
2022-11-07 14:43 ` Guillaume Ranquet
2022-11-07 14:43 ` Guillaume Ranquet
2022-11-07 14:43 ` Guillaume Ranquet
2022-11-04 14:09 ` [PATCH v3 04/12] drm/mediatek: extract common functions from the mtk hdmi driver Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-07 11:09 ` AngeloGioacchino Del Regno
2022-11-07 11:09 ` AngeloGioacchino Del Regno
2022-11-07 11:09 ` AngeloGioacchino Del Regno
2022-11-07 11:09 ` AngeloGioacchino Del Regno
2022-11-04 14:09 ` [PATCH v3 05/12] drm/mediatek: hdmi: make the cec dev optional Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` [PATCH v3 06/12] drm/mediatek: hdmi: add frame_colorimetry flag Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-07 11:09 ` AngeloGioacchino Del Regno
2022-11-07 11:09 ` AngeloGioacchino Del Regno
2022-11-07 11:09 ` AngeloGioacchino Del Regno
2022-11-07 11:09 ` AngeloGioacchino Del Regno
2022-11-07 14:57 ` Guillaume Ranquet
2022-11-07 14:57 ` Guillaume Ranquet
2022-11-07 14:57 ` Guillaume Ranquet
2022-11-07 14:57 ` Guillaume Ranquet
2022-11-04 14:09 ` [PATCH v3 07/12] drm/mediatek: hdmi: add v2 support Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-12-26 3:12 ` CK Hu (胡俊光)
2022-12-26 3:12 ` CK Hu (胡俊光)
2022-12-26 3:12 ` CK Hu (胡俊光)
2022-12-26 3:12 ` CK Hu (胡俊光)
2022-11-04 14:09 ` [PATCH v3 08/12] drm/mediatek: hdmi: v2: add audio support Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-07 11:09 ` AngeloGioacchino Del Regno
2022-11-07 11:09 ` AngeloGioacchino Del Regno
2022-11-07 11:09 ` AngeloGioacchino Del Regno
2022-11-07 11:09 ` AngeloGioacchino Del Regno
2022-11-04 14:09 ` [PATCH v3 09/12] phy: phy-mtk-hdmi: Add generic phy configure callback Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` [PATCH v3 10/12] phy: mediatek: add support for phy-mtk-hdmi-mt8195 Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-10 7:22 ` Vinod Koul
2022-11-10 7:22 ` Vinod Koul
2022-11-10 7:22 ` Vinod Koul
2022-11-10 7:22 ` Vinod Koul
2022-11-04 14:09 ` [PATCH v3 11/12] dt-bindings: display: mediatek: dpi: Add compatible for MediaTek MT8195 Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` [PATCH v3 12/12] drm/mediatek: dpi: Add mt8195 hdmi to DPI driver Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-04 14:09 ` Guillaume Ranquet
2022-11-07 11:20 ` AngeloGioacchino Del Regno
2022-11-07 11:20 ` AngeloGioacchino Del Regno
2022-11-07 11:20 ` AngeloGioacchino Del Regno
2022-11-07 11:20 ` AngeloGioacchino Del Regno
2022-11-07 15:06 ` Guillaume Ranquet
2022-11-07 15:06 ` Guillaume Ranquet
2022-11-07 15:06 ` Guillaume Ranquet
2022-11-07 15:06 ` Guillaume Ranquet
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