All of lore.kernel.org
 help / color / mirror / Atom feed
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: "Arnd Bergmann" <arnd@arndb.de>
Cc: "Valentin Korenblit" <vkorenblit@sequans.com>,
	"kernel test robot" <lkp@intel.com>,
	llvm@lists.linux.dev, kbuild-all@lists.01.org,
	linux-kernel@vger.kernel.org
Subject: Re: [mtd:nand/next 11/31] drivers/mtd/nand/raw/cadence-nand-controller.c:1893:4: error: implicit declaration of function 'ioread64_rep' is invalid in C99
Date: Thu, 22 Sep 2022 13:00:28 +0200	[thread overview]
Message-ID: <20220922130028.67657957@xps-13> (raw)
In-Reply-To: <01210adb-ff77-4ec5-8d10-ab56ae986d58@www.fastmail.com>

Hi Arnd,

arnd@arndb.de wrote on Thu, 22 Sep 2022 12:52:36 +0200:

> On Thu, Sep 22, 2022, at 11:36 AM, Miquel Raynal wrote:
> > vkorenblit@sequans.com wrote on Thu, 22 Sep 2022 10:18:46 +0200:  
> >> 
> >> Correct, this was my initial idea. However, this driver should work
> >> with every architecture or do we limit the scope to arm/arm64/x86_64?  
> >
> > The driver should work on ARM and aarch64, I'm not aware of other
> > architectures with this IP.
> >
> > The driver should compile when COMPILE_TEST=y.  
> 
> It should also be written in a way that makes it plausible to
> use elsewhere. Since this is just a licensed IP core, there is
> a good chance that someone reused it on mips or riscv, or
> anything else.

Fair enough.

> >> >> I believe what Valentin wanted to achieve in the first place, was to
> >> >> use 64-bit accesses when relevant (otherwise it does not work).    
> >> > The width is read from a device specific register at
> >> > runtime, it is not related to the architecture you are
> >> > running on, presumably this is hardwired during the
> >> > design of an SoC, based on the capabilities of the DMA
> >> > engine:  
> >
> > Well, yes, but in the mean time 64-bit DMA width will never be
> > used on 32-bit platforms.  
> 
> Why? Most architectures (including x86 and arm) allow you to
> run a 32-bit kernel on a 64-bit SoC. While this is almost always
> a bad idea to actually do, a driver should be written to
> work correctly in this setup.

Oh right, I forgot about that.

> >> > This usually means the largest access that is valid for
> >> > reading from the FIFO, but usually smaller accesses work
> >> > as well, just slower.    
> >
> > Mmh, ok, that's interesting, thanks for the pointer.
> >
> > But in the mean time I am only half satisfied, because we plan to do
> > twice more accesses than needed _just_ because of a the COMPILE_TEST
> > constraint.  
> 
> In my example, I had an #ifdef so it would only fall back
> to 32-bit accesses on the 64-bit register when running an
> actual 32-bit kernel, but leaving the 64-bit case efficient.

All right, thanks for all your valuable feedback Arnd!

Cheers,
Miquèl

WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: kbuild-all@lists.01.org
Subject: Re: [mtd:nand/next 11/31] drivers/mtd/nand/raw/cadence-nand-controller.c:1893:4: error: implicit declaration of function 'ioread64_rep' is invalid in C99
Date: Thu, 22 Sep 2022 13:00:28 +0200	[thread overview]
Message-ID: <20220922130028.67657957@xps-13> (raw)
In-Reply-To: <01210adb-ff77-4ec5-8d10-ab56ae986d58@www.fastmail.com>

[-- Attachment #1: Type: text/plain, Size: 2220 bytes --]

Hi Arnd,

arnd(a)arndb.de wrote on Thu, 22 Sep 2022 12:52:36 +0200:

> On Thu, Sep 22, 2022, at 11:36 AM, Miquel Raynal wrote:
> > vkorenblit(a)sequans.com wrote on Thu, 22 Sep 2022 10:18:46 +0200:  
> >> 
> >> Correct, this was my initial idea. However, this driver should work
> >> with every architecture or do we limit the scope to arm/arm64/x86_64?  
> >
> > The driver should work on ARM and aarch64, I'm not aware of other
> > architectures with this IP.
> >
> > The driver should compile when COMPILE_TEST=y.  
> 
> It should also be written in a way that makes it plausible to
> use elsewhere. Since this is just a licensed IP core, there is
> a good chance that someone reused it on mips or riscv, or
> anything else.

Fair enough.

> >> >> I believe what Valentin wanted to achieve in the first place, was to
> >> >> use 64-bit accesses when relevant (otherwise it does not work).    
> >> > The width is read from a device specific register at
> >> > runtime, it is not related to the architecture you are
> >> > running on, presumably this is hardwired during the
> >> > design of an SoC, based on the capabilities of the DMA
> >> > engine:  
> >
> > Well, yes, but in the mean time 64-bit DMA width will never be
> > used on 32-bit platforms.  
> 
> Why? Most architectures (including x86 and arm) allow you to
> run a 32-bit kernel on a 64-bit SoC. While this is almost always
> a bad idea to actually do, a driver should be written to
> work correctly in this setup.

Oh right, I forgot about that.

> >> > This usually means the largest access that is valid for
> >> > reading from the FIFO, but usually smaller accesses work
> >> > as well, just slower.    
> >
> > Mmh, ok, that's interesting, thanks for the pointer.
> >
> > But in the mean time I am only half satisfied, because we plan to do
> > twice more accesses than needed _just_ because of a the COMPILE_TEST
> > constraint.  
> 
> In my example, I had an #ifdef so it would only fall back
> to 32-bit accesses on the 64-bit register when running an
> actual 32-bit kernel, but leaving the 64-bit case efficient.

All right, thanks for all your valuable feedback Arnd!

Cheers,
Miquèl

  reply	other threads:[~2022-09-22 11:00 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-20 22:31 [mtd:nand/next 11/31] drivers/mtd/nand/raw/cadence-nand-controller.c:1893:4: error: implicit declaration of function 'ioread64_rep' is invalid in C99 kernel test robot
2022-09-21  8:40 ` Miquel Raynal
2022-09-21  8:40   ` Miquel Raynal
2022-09-21  8:45   ` Valentin Korenblit
2022-09-21  8:45     ` Valentin Korenblit
2022-09-21 12:27     ` Valentin Korenblit
2022-09-21 14:47       ` Miquel Raynal
2022-09-21 14:47         ` Miquel Raynal
2022-09-21 15:49         ` Arnd Bergmann
2022-09-21 15:49           ` Arnd Bergmann
2022-09-21 16:38           ` Miquel Raynal
2022-09-21 16:38             ` Miquel Raynal
2022-09-21 20:01             ` Arnd Bergmann
2022-09-21 20:01               ` Arnd Bergmann
2022-09-22  8:18               ` Valentin Korenblit
2022-09-22  9:36                 ` Miquel Raynal
2022-09-22  9:36                   ` Miquel Raynal
2022-09-22 10:52                   ` Arnd Bergmann
2022-09-22 10:52                     ` Arnd Bergmann
2022-09-22 11:00                     ` Miquel Raynal [this message]
2022-09-22 11:00                       ` Miquel Raynal
2022-09-27 14:56                     ` Valentin Korenblit
2022-09-27 20:02                       ` Arnd Bergmann
2022-09-27 20:02                         ` Arnd Bergmann
2022-09-28  8:41                         ` Valentin Korenblit
2022-09-28  8:41                           ` Valentin Korenblit
2022-09-28  8:56                           ` Arnd Bergmann
2022-09-28  8:56                             ` Arnd Bergmann
2022-09-28 10:04                             ` Valentin Korenblit
2022-09-28 10:04                               ` Valentin Korenblit
2022-09-22  9:38               ` Miquel Raynal
2022-09-22  9:38                 ` Miquel Raynal

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220922130028.67657957@xps-13 \
    --to=miquel.raynal@bootlin.com \
    --cc=arnd@arndb.de \
    --cc=kbuild-all@lists.01.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=lkp@intel.com \
    --cc=llvm@lists.linux.dev \
    --cc=vkorenblit@sequans.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.