Re: [mtd:nand/next 11/31] drivers/mtd/nand/raw/cadence-nand-controller.c:1893:4: error: implicit declaration of function 'ioread64_rep' is invalid in C99

[Valentin Korenblit <vkorenblit@sequans.com>]

On 9/27/22 22:02, Arnd Bergmann wrote:
> On Tue, Sep 27, 2022, at 4:56 PM, Valentin Korenblit wrote:
>>>> But in the mean time I am only half satisfied, because we plan to do
>>>> twice more accesses than needed _just_ because of a the COMPILE_TEST
>>>> constraint.
>>> In my example, I had an #ifdef so it would only fall back
>>> to 32-bit accesses on the 64-bit register when running an
>>> actual 32-bit kernel, but leaving the 64-bit case efficient. Sorry for my late reply. I've just tested this and unfortunately
>> the two sequential 32-bit accesses (with OFF0==0 and OFF1==4 seem
>> to trigger sdma_err. I need to check some waveforms to verify if it
>> happens right after the first access.
> What happens if you do pairs of read from offset 0, effectively
> doing a readsl() instead of readql(), obviously with twice the number
> of accesses.
>
> It's also possible you have to read from the second word first,
> like
>
>    u32 *buf;
>    do {
>       buf[1] = __raw_readl(reg + 4);
>       buf[0] = __raw_readl(reg);
>       buf += 2;
>    }  while (buf < end);
>
>     Arnd

Same result with pairs of readl at OFF0 and when reading at OFF1 first too,
I still see sdma_err. I've just opened a case to Cadence to see if there
is any workaround for this or if it is just not possible.

I'll be back as soon as I have some news.

Valentin

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