From: "Marek Behún" <kabel@kernel.org>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: "Bjorn Helgaas" <helgaas@kernel.org>,
"Gregory CLEMENT" <gregory.clement@bootlin.com>,
pali@kernel.org, "Krzysztof Wilczyński" <kw@linux.com>,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
"Marek Behún" <kabel@kernel.org>
Subject: [PATCH v2 07/10] PCI: aardvark: Replace custom PCIE_CORE_ERR_CAPCTL_* macros by linux/pci_regs.h macros
Date: Tue, 27 Sep 2022 16:19:23 +0200 [thread overview]
Message-ID: <20220927141926.8895-8-kabel@kernel.org> (raw)
In-Reply-To: <20220927141926.8895-1-kabel@kernel.org>
From: Pali Rohár <pali@kernel.org>
Kernel already has these macros defined under different names.
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
---
drivers/pci/controller/pci-aardvark.c | 14 ++++----------
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index e30a33a4ecc6..4855ac733484 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -37,11 +37,7 @@
#define PCIE_CORE_DEV_REV_REG 0x8
#define PCIE_CORE_PCIEXP_CAP 0xc0
#define PCIE_CORE_PCIERR_CAP 0x100
-#define PCIE_CORE_ERR_CAPCTL_REG 0x118
-#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
-#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
-#define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7)
-#define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8)
+
/* PIO registers base address and register offsets */
#define PIO_BASE_ADDR 0x4000
#define PIO_CTRL (PIO_BASE_ADDR + 0x0)
@@ -589,11 +585,9 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
/* Set Advanced Error Capabilities and Control PF0 register */
- reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
- PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
- PCIE_CORE_ERR_CAPCTL_ECRC_CHCK |
- PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV;
- advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
+ reg = PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_GENE |
+ PCI_ERR_CAP_ECRC_CHKC | PCI_ERR_CAP_ECRC_CHKE;
+ advk_writel(pcie, reg, PCIE_CORE_PCIERR_CAP + PCI_ERR_CAP);
/* Set PCIe Device Control register */
reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
--
2.35.1
WARNING: multiple messages have this Message-ID (diff)
From: "Marek Behún" <kabel@kernel.org>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: "Bjorn Helgaas" <helgaas@kernel.org>,
"Gregory CLEMENT" <gregory.clement@bootlin.com>,
pali@kernel.org, "Krzysztof Wilczyński" <kw@linux.com>,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
"Marek Behún" <kabel@kernel.org>
Subject: [PATCH v2 07/10] PCI: aardvark: Replace custom PCIE_CORE_ERR_CAPCTL_* macros by linux/pci_regs.h macros
Date: Tue, 27 Sep 2022 16:19:23 +0200 [thread overview]
Message-ID: <20220927141926.8895-8-kabel@kernel.org> (raw)
In-Reply-To: <20220927141926.8895-1-kabel@kernel.org>
From: Pali Rohár <pali@kernel.org>
Kernel already has these macros defined under different names.
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <kabel@kernel.org>
---
drivers/pci/controller/pci-aardvark.c | 14 ++++----------
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index e30a33a4ecc6..4855ac733484 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -37,11 +37,7 @@
#define PCIE_CORE_DEV_REV_REG 0x8
#define PCIE_CORE_PCIEXP_CAP 0xc0
#define PCIE_CORE_PCIERR_CAP 0x100
-#define PCIE_CORE_ERR_CAPCTL_REG 0x118
-#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
-#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
-#define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7)
-#define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8)
+
/* PIO registers base address and register offsets */
#define PIO_BASE_ADDR 0x4000
#define PIO_CTRL (PIO_BASE_ADDR + 0x0)
@@ -589,11 +585,9 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
/* Set Advanced Error Capabilities and Control PF0 register */
- reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
- PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
- PCIE_CORE_ERR_CAPCTL_ECRC_CHCK |
- PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV;
- advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
+ reg = PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_GENE |
+ PCI_ERR_CAP_ECRC_CHKC | PCI_ERR_CAP_ECRC_CHKE;
+ advk_writel(pcie, reg, PCIE_CORE_PCIERR_CAP + PCI_ERR_CAP);
/* Set PCIe Device Control register */
reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
--
2.35.1
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next prev parent reply other threads:[~2022-09-27 14:20 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-27 14:19 [PATCH v2 00/10] PCI: aardvark controller changes BATCH 6 Marek Behún
2022-09-27 14:19 ` Marek Behún
2022-09-27 14:19 ` [PATCH v2 01/10] PCI: pciehp: Enable Command Completed Interrupt only if supported Marek Behún
2022-09-27 14:19 ` Marek Behún
2022-12-07 14:29 ` Bjorn Helgaas
2022-12-07 14:29 ` Bjorn Helgaas
2022-09-27 14:19 ` [PATCH v2 02/10] PCI: aardvark: Add support for DLLSC and hotplug interrupt Marek Behún
2022-09-27 14:19 ` Marek Behún
2022-09-27 14:19 ` [PATCH v2 03/10] PCI: aardvark: Send Set_Slot_Power_Limit message Marek Behún
2022-09-27 14:19 ` Marek Behún
2022-09-27 14:19 ` [PATCH v2 04/10] arm64: dts: armada-3720-turris-mox: Define slot-power-limit-milliwatt for PCIe Marek Behún
2022-09-27 14:19 ` Marek Behún
2022-11-27 23:36 ` Gregory CLEMENT
2022-11-27 23:36 ` Gregory CLEMENT
2022-09-27 14:19 ` [PATCH v2 05/10] PCI: aardvark: Add clock support Marek Behún
2022-09-27 14:19 ` Marek Behún
2022-09-27 14:19 ` [PATCH v2 06/10] PCI: aardvark: Add suspend to RAM support Marek Behún
2022-09-27 14:19 ` Marek Behún
2022-09-27 14:19 ` Marek Behún [this message]
2022-09-27 14:19 ` [PATCH v2 07/10] PCI: aardvark: Replace custom PCIE_CORE_ERR_CAPCTL_* macros by linux/pci_regs.h macros Marek Behún
2022-09-27 14:19 ` [PATCH v2 08/10] PCI: aardvark: Don't write read-only bits explicitly in PCI_ERR_CAP register Marek Behún
2022-09-27 14:19 ` Marek Behún
2022-09-27 14:19 ` [PATCH v2 09/10] PCI: aardvark: Explicitly disable Marvell strict ordering Marek Behún
2022-09-27 14:19 ` Marek Behún
2022-09-27 14:19 ` [PATCH v2 10/10] PCI: aardvark: Cleanup some register macros Marek Behún
2022-09-27 14:19 ` Marek Behún
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