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From: "Marek Behún" <kabel@kernel.org>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: "Bjorn Helgaas" <helgaas@kernel.org>,
	"Gregory CLEMENT" <gregory.clement@bootlin.com>,
	pali@kernel.org, "Krzysztof Wilczyński" <kw@linux.com>,
	linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	"Marek Behún" <kabel@kernel.org>
Subject: [PATCH v2 08/10] PCI: aardvark: Don't write read-only bits explicitly in PCI_ERR_CAP register
Date: Tue, 27 Sep 2022 16:19:24 +0200	[thread overview]
Message-ID: <20220927141926.8895-9-kabel@kernel.org> (raw)
In-Reply-To: <20220927141926.8895-1-kabel@kernel.org>

The bits PCI_ERR_CAP_ECRC_GENC and PCI_ERR_CAP_ECRC_CHKC are read only,
reporting the capability of ECRC. Don't write them explicitly, instead
read the register (where they are set), and add the bits that enable
these features.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/pci/controller/pci-aardvark.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 4855ac733484..e816ab726f66 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -584,9 +584,9 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
 	reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 	advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
 
-	/* Set Advanced Error Capabilities and Control PF0 register */
-	reg = PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_GENE |
-	      PCI_ERR_CAP_ECRC_CHKC | PCI_ERR_CAP_ECRC_CHKE;
+	/* Enable generation and checking of ECRC on Root Bridge */
+	reg = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + PCI_ERR_CAP);
+	reg |= PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE;
 	advk_writel(pcie, reg, PCIE_CORE_PCIERR_CAP + PCI_ERR_CAP);
 
 	/* Set PCIe Device Control register */
-- 
2.35.1


WARNING: multiple messages have this Message-ID (diff)
From: "Marek Behún" <kabel@kernel.org>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: "Bjorn Helgaas" <helgaas@kernel.org>,
	"Gregory CLEMENT" <gregory.clement@bootlin.com>,
	pali@kernel.org, "Krzysztof Wilczyński" <kw@linux.com>,
	linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	"Marek Behún" <kabel@kernel.org>
Subject: [PATCH v2 08/10] PCI: aardvark: Don't write read-only bits explicitly in PCI_ERR_CAP register
Date: Tue, 27 Sep 2022 16:19:24 +0200	[thread overview]
Message-ID: <20220927141926.8895-9-kabel@kernel.org> (raw)
In-Reply-To: <20220927141926.8895-1-kabel@kernel.org>

The bits PCI_ERR_CAP_ECRC_GENC and PCI_ERR_CAP_ECRC_CHKC are read only,
reporting the capability of ECRC. Don't write them explicitly, instead
read the register (where they are set), and add the bits that enable
these features.

Signed-off-by: Marek Behún <kabel@kernel.org>
---
 drivers/pci/controller/pci-aardvark.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 4855ac733484..e816ab726f66 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -584,9 +584,9 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
 	reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 	advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
 
-	/* Set Advanced Error Capabilities and Control PF0 register */
-	reg = PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_GENE |
-	      PCI_ERR_CAP_ECRC_CHKC | PCI_ERR_CAP_ECRC_CHKE;
+	/* Enable generation and checking of ECRC on Root Bridge */
+	reg = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + PCI_ERR_CAP);
+	reg |= PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE;
 	advk_writel(pcie, reg, PCIE_CORE_PCIERR_CAP + PCI_ERR_CAP);
 
 	/* Set PCIe Device Control register */
-- 
2.35.1


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  parent reply	other threads:[~2022-09-27 14:20 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-27 14:19 [PATCH v2 00/10] PCI: aardvark controller changes BATCH 6 Marek Behún
2022-09-27 14:19 ` Marek Behún
2022-09-27 14:19 ` [PATCH v2 01/10] PCI: pciehp: Enable Command Completed Interrupt only if supported Marek Behún
2022-09-27 14:19   ` Marek Behún
2022-12-07 14:29   ` Bjorn Helgaas
2022-12-07 14:29     ` Bjorn Helgaas
2022-09-27 14:19 ` [PATCH v2 02/10] PCI: aardvark: Add support for DLLSC and hotplug interrupt Marek Behún
2022-09-27 14:19   ` Marek Behún
2022-09-27 14:19 ` [PATCH v2 03/10] PCI: aardvark: Send Set_Slot_Power_Limit message Marek Behún
2022-09-27 14:19   ` Marek Behún
2022-09-27 14:19 ` [PATCH v2 04/10] arm64: dts: armada-3720-turris-mox: Define slot-power-limit-milliwatt for PCIe Marek Behún
2022-09-27 14:19   ` Marek Behún
2022-11-27 23:36   ` Gregory CLEMENT
2022-11-27 23:36     ` Gregory CLEMENT
2022-09-27 14:19 ` [PATCH v2 05/10] PCI: aardvark: Add clock support Marek Behún
2022-09-27 14:19   ` Marek Behún
2022-09-27 14:19 ` [PATCH v2 06/10] PCI: aardvark: Add suspend to RAM support Marek Behún
2022-09-27 14:19   ` Marek Behún
2022-09-27 14:19 ` [PATCH v2 07/10] PCI: aardvark: Replace custom PCIE_CORE_ERR_CAPCTL_* macros by linux/pci_regs.h macros Marek Behún
2022-09-27 14:19   ` Marek Behún
2022-09-27 14:19 ` Marek Behún [this message]
2022-09-27 14:19   ` [PATCH v2 08/10] PCI: aardvark: Don't write read-only bits explicitly in PCI_ERR_CAP register Marek Behún
2022-09-27 14:19 ` [PATCH v2 09/10] PCI: aardvark: Explicitly disable Marvell strict ordering Marek Behún
2022-09-27 14:19   ` Marek Behún
2022-09-27 14:19 ` [PATCH v2 10/10] PCI: aardvark: Cleanup some register macros Marek Behún
2022-09-27 14:19   ` Marek Behún

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