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From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 6/8] riscv: fpu: switch has_fpu() to riscv_has_extension_likely()
Date: Thu,  6 Oct 2022 15:08:16 +0800	[thread overview]
Message-ID: <20221006070818.3616-7-jszhang@kernel.org> (raw)
In-Reply-To: <20221006070818.3616-1-jszhang@kernel.org>

Switch has_fpu() from statich branch to the new helper
riscv_has_extension_likely().

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 arch/riscv/include/asm/switch_to.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h
index 11463489fec6..60f8ca01d36e 100644
--- a/arch/riscv/include/asm/switch_to.h
+++ b/arch/riscv/include/asm/switch_to.h
@@ -59,7 +59,8 @@ static inline void __switch_to_aux(struct task_struct *prev,
 
 static __always_inline bool has_fpu(void)
 {
-	return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_FPU]);
+	return riscv_has_extension_likely(RISCV_ISA_EXT_f) ||
+		riscv_has_extension_likely(RISCV_ISA_EXT_d);
 }
 #else
 static __always_inline bool has_fpu(void) { return false; }
-- 
2.37.2


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WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 6/8] riscv: fpu: switch has_fpu() to riscv_has_extension_likely()
Date: Thu,  6 Oct 2022 15:08:16 +0800	[thread overview]
Message-ID: <20221006070818.3616-7-jszhang@kernel.org> (raw)
In-Reply-To: <20221006070818.3616-1-jszhang@kernel.org>

Switch has_fpu() from statich branch to the new helper
riscv_has_extension_likely().

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 arch/riscv/include/asm/switch_to.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h
index 11463489fec6..60f8ca01d36e 100644
--- a/arch/riscv/include/asm/switch_to.h
+++ b/arch/riscv/include/asm/switch_to.h
@@ -59,7 +59,8 @@ static inline void __switch_to_aux(struct task_struct *prev,
 
 static __always_inline bool has_fpu(void)
 {
-	return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_FPU]);
+	return riscv_has_extension_likely(RISCV_ISA_EXT_f) ||
+		riscv_has_extension_likely(RISCV_ISA_EXT_d);
 }
 #else
 static __always_inline bool has_fpu(void) { return false; }
-- 
2.37.2


  parent reply	other threads:[~2022-10-06  7:18 UTC|newest]

Thread overview: 70+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-06  7:08 [PATCH 0/8] riscv: improve boot time isa extensions handling Jisheng Zhang
2022-10-06  7:08 ` Jisheng Zhang
2022-10-06  7:08 ` [PATCH 1/8] riscv: move riscv_noncoherent_supported() out of ZICBOM probe Jisheng Zhang
2022-10-06  7:08   ` Jisheng Zhang
2022-10-06 13:10   ` Andrew Jones
2022-10-06 13:10     ` Andrew Jones
2022-10-06 17:44     ` Andrew Jones
2022-10-06 17:44       ` Andrew Jones
2022-10-07  9:18   ` Heiko Stübner
2022-10-07  9:18     ` Heiko Stübner
2022-10-08 13:06   ` Conor Dooley
2022-10-08 13:06     ` Conor Dooley
2022-10-08 13:59     ` Jisheng Zhang
2022-10-08 13:59       ` Jisheng Zhang
2022-10-13  5:37       ` Conor Dooley
2022-10-13  5:37         ` Conor Dooley
2022-10-06  7:08 ` [PATCH 2/8] riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier Jisheng Zhang
2022-10-06  7:08   ` Jisheng Zhang
2022-10-06 13:12   ` Andrew Jones
2022-10-06 13:12     ` Andrew Jones
2022-10-07  9:38   ` Heiko Stübner
2022-10-07  9:38     ` Heiko Stübner
2022-10-06  7:08 ` [PATCH 3/8] riscv: hwcap: make ISA extension ids can be used in asm Jisheng Zhang
2022-10-06  7:08   ` Jisheng Zhang
2022-10-06 13:15   ` Andrew Jones
2022-10-06 13:15     ` Andrew Jones
2022-10-07  9:22   ` Heiko Stübner
2022-10-07  9:22     ` Heiko Stübner
2022-10-06  7:08 ` [PATCH 4/8] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions Jisheng Zhang
2022-10-06  7:08   ` Jisheng Zhang
2022-10-06 13:31   ` Andrew Jones
2022-10-06 13:31     ` Andrew Jones
2022-10-07 11:54   ` Heiko Stübner
2022-10-07 11:54     ` Heiko Stübner
2022-10-13 13:28     ` Heiko Stuebner
2022-10-13 13:28       ` Heiko Stuebner
2022-10-06  7:08 ` [PATCH 5/8] riscv: introduce riscv_has_extension_[un]likely() Jisheng Zhang
2022-10-06  7:08   ` Jisheng Zhang
2022-10-06 13:36   ` Andrew Jones
2022-10-06 13:36     ` Andrew Jones
2022-10-06  7:08 ` Jisheng Zhang [this message]
2022-10-06  7:08   ` [PATCH 6/8] riscv: fpu: switch has_fpu() to riscv_has_extension_likely() Jisheng Zhang
2022-10-06 13:36   ` Andrew Jones
2022-10-06 13:36     ` Andrew Jones
2022-10-07 15:11   ` Heiko Stübner
2022-10-07 15:11     ` Heiko Stübner
2022-10-06  7:08 ` [PATCH 7/8] riscv: cpu_relax: switch " Jisheng Zhang
2022-10-06  7:08   ` Jisheng Zhang
2022-10-06 13:28   ` kernel test robot
2022-10-06 13:28     ` kernel test robot
2022-10-06 13:37   ` Andrew Jones
2022-10-06 13:37     ` Andrew Jones
2022-10-07 15:12   ` Heiko Stübner
2022-10-07 15:12     ` Heiko Stübner
2022-10-07 18:14   ` kernel test robot
2022-10-07 18:14     ` kernel test robot
2022-10-06  7:08 ` [PATCH 8/8] riscv: remove riscv_isa_ext_keys[] array and related usage Jisheng Zhang
2022-10-06  7:08   ` Jisheng Zhang
2022-10-06 13:38   ` Andrew Jones
2022-10-06 13:38     ` Andrew Jones
2022-10-07 15:12   ` Heiko Stübner
2022-10-07 15:12     ` Heiko Stübner
2022-10-13 16:20 ` [PATCH 0/8] riscv: improve boot time isa extensions handling Andrew Jones
2022-10-13 16:20   ` Andrew Jones
2022-10-29  9:56 ` Andrew Jones
2022-10-29  9:56   ` Andrew Jones
2022-10-29 11:38   ` Jisheng Zhang
2022-10-29 11:38     ` Jisheng Zhang
2022-10-30 16:03   ` Jisheng Zhang
2022-10-30 16:03     ` Jisheng Zhang

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