From: Jisheng Zhang <jszhang@kernel.org>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/8] riscv: improve boot time isa extensions handling
Date: Mon, 31 Oct 2022 00:03:20 +0800 [thread overview]
Message-ID: <Y16gSDwCWmp3vxaw@xhacker> (raw)
In-Reply-To: <20221029095609.e4ymkbnk2hl3kxzc@kamzik>
On Sat, Oct 29, 2022 at 11:56:09AM +0200, Andrew Jones wrote:
> On Thu, Oct 06, 2022 at 03:08:10PM +0800, Jisheng Zhang wrote:
> > Generally, riscv ISA extensions are fixed for any specific hardware
> > platform, that's to say, the hart features won't change any more
> > after booting, this chacteristic make it straightforward to use
> > static branch to check one specific ISA extension is supported or not
> > to optimize performance.
> >
> > However, some ISA extensions such as SVPBMT and ZICBOM are handled
> > via. the alternative sequences.
> >
> > Basically, for ease of maintenance, we prefer to use static branches
> > in C code, but recently, Samuel found that the static branch usage in
> > cpu_relax() breaks building with CONFIG_CC_OPTIMIZE_FOR_SIZE[1]. As
> > Samuel pointed out, "Having a static branch in cpu_relax() is
> > problematic because that function is widely inlined, including in some
> > quite complex functions like in the VDSO. A quick measurement shows
> > this static branch is responsible by itself for around 40% of the jump
> > table."
> >
> > Samuel's findings pointed out one of a few downsides of static branches
> > usage in C code to handle ISA extensions detected at boot time:
> > static branch's metadata in the __jump_table section, which is not
> > discarded after ISA extensions are finalized, wastes some space.
> >
> > I want to try to solve the issue for all possible dynamic handling of
> > ISA extensions at boot time. Inspired by Mark[2], this patch introduces
> > riscv_has_extension_*() helpers, which work like static branches but
> > are patched using alternatives, thus the metadata can be freed after
> > patching.
> >
> > [1]https://lore.kernel.org/linux-riscv/20220922060958.44203-1-samuel@sholland.org/
> > [2]https://lore.kernel.org/linux-arm-kernel/20220912162210.3626215-8-mark.rutland@arm.com/
> >
> >
> > Jisheng Zhang (8):
> > riscv: move riscv_noncoherent_supported() out of ZICBOM probe
> > riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier
> > riscv: hwcap: make ISA extension ids can be used in asm
> > riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA
> > extensions
> > riscv: introduce riscv_has_extension_[un]likely()
> > riscv: fpu: switch has_fpu() to riscv_has_extension_likely()
> > riscv: cpu_relax: switch to riscv_has_extension_likely()
> > riscv: remove riscv_isa_ext_keys[] array and related usage
> >
> > arch/riscv/include/asm/errata_list.h | 9 +--
> > arch/riscv/include/asm/hwcap.h | 94 ++++++++++++++-----------
> > arch/riscv/include/asm/switch_to.h | 3 +-
> > arch/riscv/include/asm/vdso/processor.h | 2 +-
> > arch/riscv/kernel/cpufeature.c | 78 +++-----------------
> > arch/riscv/kernel/setup.c | 4 ++
> > 6 files changed, 71 insertions(+), 119 deletions(-)
> >
> > --
> > 2.37.2
> >
>
> Hi Jisheng,
>
> I just tried building this with LLVM=1 and fails to compile with messages
> like
>
> ld.lld: error: relocation R_RISCV_64 cannot be used against symbol '.Ltmp1'; recompile with -fPIC
> >>> defined in arch/riscv/kernel/vdso/vgettimeofday.o
> >>> referenced by vgettimeofday.c
> >>> arch/riscv/kernel/vdso/vgettimeofday.o:(.alternative+0x0)
>
> It does compile and boot with CC=clang and binutils 2.39, where my clang
> version is 14.0.5 (Fedora 14.0.5-1.fc36).
Hi Andrew,
Below is a quick fix.
PS: I think I need add two or more patches to apply alternatives in the
vDSO. But currently only Zihintpause is affected.
Will send out a new version.
diff --git a/arch/riscv/kernel/vdso/Makefile b/arch/riscv/kernel/vdso/Makefile
index f2e065671e4d..522b78477bab 100644
--- a/arch/riscv/kernel/vdso/Makefile
+++ b/arch/riscv/kernel/vdso/Makefile
@@ -44,7 +44,7 @@ $(obj)/vdso.o: $(obj)/vdso.so
# link rule for the .so file, .lds has to be first
$(obj)/vdso.so.dbg: $(obj)/vdso.lds $(obj-vdso) FORCE
$(call if_changed,vdsold)
-LDFLAGS_vdso.so.dbg = -shared -S -soname=linux-vdso.so.1 \
+LDFLAGS_vdso.so.dbg = -shared -z notext -S -soname=linux-vdso.so.1 \
>
> Thanks,
> drew
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/8] riscv: improve boot time isa extensions handling
Date: Mon, 31 Oct 2022 00:03:20 +0800 [thread overview]
Message-ID: <Y16gSDwCWmp3vxaw@xhacker> (raw)
In-Reply-To: <20221029095609.e4ymkbnk2hl3kxzc@kamzik>
On Sat, Oct 29, 2022 at 11:56:09AM +0200, Andrew Jones wrote:
> On Thu, Oct 06, 2022 at 03:08:10PM +0800, Jisheng Zhang wrote:
> > Generally, riscv ISA extensions are fixed for any specific hardware
> > platform, that's to say, the hart features won't change any more
> > after booting, this chacteristic make it straightforward to use
> > static branch to check one specific ISA extension is supported or not
> > to optimize performance.
> >
> > However, some ISA extensions such as SVPBMT and ZICBOM are handled
> > via. the alternative sequences.
> >
> > Basically, for ease of maintenance, we prefer to use static branches
> > in C code, but recently, Samuel found that the static branch usage in
> > cpu_relax() breaks building with CONFIG_CC_OPTIMIZE_FOR_SIZE[1]. As
> > Samuel pointed out, "Having a static branch in cpu_relax() is
> > problematic because that function is widely inlined, including in some
> > quite complex functions like in the VDSO. A quick measurement shows
> > this static branch is responsible by itself for around 40% of the jump
> > table."
> >
> > Samuel's findings pointed out one of a few downsides of static branches
> > usage in C code to handle ISA extensions detected at boot time:
> > static branch's metadata in the __jump_table section, which is not
> > discarded after ISA extensions are finalized, wastes some space.
> >
> > I want to try to solve the issue for all possible dynamic handling of
> > ISA extensions at boot time. Inspired by Mark[2], this patch introduces
> > riscv_has_extension_*() helpers, which work like static branches but
> > are patched using alternatives, thus the metadata can be freed after
> > patching.
> >
> > [1]https://lore.kernel.org/linux-riscv/20220922060958.44203-1-samuel@sholland.org/
> > [2]https://lore.kernel.org/linux-arm-kernel/20220912162210.3626215-8-mark.rutland@arm.com/
> >
> >
> > Jisheng Zhang (8):
> > riscv: move riscv_noncoherent_supported() out of ZICBOM probe
> > riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier
> > riscv: hwcap: make ISA extension ids can be used in asm
> > riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA
> > extensions
> > riscv: introduce riscv_has_extension_[un]likely()
> > riscv: fpu: switch has_fpu() to riscv_has_extension_likely()
> > riscv: cpu_relax: switch to riscv_has_extension_likely()
> > riscv: remove riscv_isa_ext_keys[] array and related usage
> >
> > arch/riscv/include/asm/errata_list.h | 9 +--
> > arch/riscv/include/asm/hwcap.h | 94 ++++++++++++++-----------
> > arch/riscv/include/asm/switch_to.h | 3 +-
> > arch/riscv/include/asm/vdso/processor.h | 2 +-
> > arch/riscv/kernel/cpufeature.c | 78 +++-----------------
> > arch/riscv/kernel/setup.c | 4 ++
> > 6 files changed, 71 insertions(+), 119 deletions(-)
> >
> > --
> > 2.37.2
> >
>
> Hi Jisheng,
>
> I just tried building this with LLVM=1 and fails to compile with messages
> like
>
> ld.lld: error: relocation R_RISCV_64 cannot be used against symbol '.Ltmp1'; recompile with -fPIC
> >>> defined in arch/riscv/kernel/vdso/vgettimeofday.o
> >>> referenced by vgettimeofday.c
> >>> arch/riscv/kernel/vdso/vgettimeofday.o:(.alternative+0x0)
>
> It does compile and boot with CC=clang and binutils 2.39, where my clang
> version is 14.0.5 (Fedora 14.0.5-1.fc36).
Hi Andrew,
Below is a quick fix.
PS: I think I need add two or more patches to apply alternatives in the
vDSO. But currently only Zihintpause is affected.
Will send out a new version.
diff --git a/arch/riscv/kernel/vdso/Makefile b/arch/riscv/kernel/vdso/Makefile
index f2e065671e4d..522b78477bab 100644
--- a/arch/riscv/kernel/vdso/Makefile
+++ b/arch/riscv/kernel/vdso/Makefile
@@ -44,7 +44,7 @@ $(obj)/vdso.o: $(obj)/vdso.so
# link rule for the .so file, .lds has to be first
$(obj)/vdso.so.dbg: $(obj)/vdso.lds $(obj-vdso) FORCE
$(call if_changed,vdsold)
-LDFLAGS_vdso.so.dbg = -shared -S -soname=linux-vdso.so.1 \
+LDFLAGS_vdso.so.dbg = -shared -z notext -S -soname=linux-vdso.so.1 \
>
> Thanks,
> drew
next prev parent reply other threads:[~2022-10-30 16:13 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-06 7:08 [PATCH 0/8] riscv: improve boot time isa extensions handling Jisheng Zhang
2022-10-06 7:08 ` Jisheng Zhang
2022-10-06 7:08 ` [PATCH 1/8] riscv: move riscv_noncoherent_supported() out of ZICBOM probe Jisheng Zhang
2022-10-06 7:08 ` Jisheng Zhang
2022-10-06 13:10 ` Andrew Jones
2022-10-06 13:10 ` Andrew Jones
2022-10-06 17:44 ` Andrew Jones
2022-10-06 17:44 ` Andrew Jones
2022-10-07 9:18 ` Heiko Stübner
2022-10-07 9:18 ` Heiko Stübner
2022-10-08 13:06 ` Conor Dooley
2022-10-08 13:06 ` Conor Dooley
2022-10-08 13:59 ` Jisheng Zhang
2022-10-08 13:59 ` Jisheng Zhang
2022-10-13 5:37 ` Conor Dooley
2022-10-13 5:37 ` Conor Dooley
2022-10-06 7:08 ` [PATCH 2/8] riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier Jisheng Zhang
2022-10-06 7:08 ` Jisheng Zhang
2022-10-06 13:12 ` Andrew Jones
2022-10-06 13:12 ` Andrew Jones
2022-10-07 9:38 ` Heiko Stübner
2022-10-07 9:38 ` Heiko Stübner
2022-10-06 7:08 ` [PATCH 3/8] riscv: hwcap: make ISA extension ids can be used in asm Jisheng Zhang
2022-10-06 7:08 ` Jisheng Zhang
2022-10-06 13:15 ` Andrew Jones
2022-10-06 13:15 ` Andrew Jones
2022-10-07 9:22 ` Heiko Stübner
2022-10-07 9:22 ` Heiko Stübner
2022-10-06 7:08 ` [PATCH 4/8] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions Jisheng Zhang
2022-10-06 7:08 ` Jisheng Zhang
2022-10-06 13:31 ` Andrew Jones
2022-10-06 13:31 ` Andrew Jones
2022-10-07 11:54 ` Heiko Stübner
2022-10-07 11:54 ` Heiko Stübner
2022-10-13 13:28 ` Heiko Stuebner
2022-10-13 13:28 ` Heiko Stuebner
2022-10-06 7:08 ` [PATCH 5/8] riscv: introduce riscv_has_extension_[un]likely() Jisheng Zhang
2022-10-06 7:08 ` Jisheng Zhang
2022-10-06 13:36 ` Andrew Jones
2022-10-06 13:36 ` Andrew Jones
2022-10-06 7:08 ` [PATCH 6/8] riscv: fpu: switch has_fpu() to riscv_has_extension_likely() Jisheng Zhang
2022-10-06 7:08 ` Jisheng Zhang
2022-10-06 13:36 ` Andrew Jones
2022-10-06 13:36 ` Andrew Jones
2022-10-07 15:11 ` Heiko Stübner
2022-10-07 15:11 ` Heiko Stübner
2022-10-06 7:08 ` [PATCH 7/8] riscv: cpu_relax: switch " Jisheng Zhang
2022-10-06 7:08 ` Jisheng Zhang
2022-10-06 13:28 ` kernel test robot
2022-10-06 13:28 ` kernel test robot
2022-10-06 13:37 ` Andrew Jones
2022-10-06 13:37 ` Andrew Jones
2022-10-07 15:12 ` Heiko Stübner
2022-10-07 15:12 ` Heiko Stübner
2022-10-07 18:14 ` kernel test robot
2022-10-07 18:14 ` kernel test robot
2022-10-06 7:08 ` [PATCH 8/8] riscv: remove riscv_isa_ext_keys[] array and related usage Jisheng Zhang
2022-10-06 7:08 ` Jisheng Zhang
2022-10-06 13:38 ` Andrew Jones
2022-10-06 13:38 ` Andrew Jones
2022-10-07 15:12 ` Heiko Stübner
2022-10-07 15:12 ` Heiko Stübner
2022-10-13 16:20 ` [PATCH 0/8] riscv: improve boot time isa extensions handling Andrew Jones
2022-10-13 16:20 ` Andrew Jones
2022-10-29 9:56 ` Andrew Jones
2022-10-29 9:56 ` Andrew Jones
2022-10-29 11:38 ` Jisheng Zhang
2022-10-29 11:38 ` Jisheng Zhang
2022-10-30 16:03 ` Jisheng Zhang [this message]
2022-10-30 16:03 ` Jisheng Zhang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Y16gSDwCWmp3vxaw@xhacker \
--to=jszhang@kernel.org \
--cc=ajones@ventanamicro.com \
--cc=aou@eecs.berkeley.edu \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.