From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 10/28] target/arm: Add is_secure parameter to v7m_read_half_insn
Date: Mon, 10 Oct 2022 15:27:12 +0100 [thread overview]
Message-ID: <20221010142730.502083-11-peter.maydell@linaro.org> (raw)
In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
Remove the use of regime_is_secure from v7m_read_half_insn, using
the new parameter instead.
As it happens, both callers pass true, propagated from the argument
to arm_v7m_mmu_idx_for_secstate which created the mmu_idx argument,
but that is a detail of v7m_handle_execute_nsc we need not expose
to the callee.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/m_helper.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index 5ee4ee15b36..203ba411f64 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -1981,7 +1981,7 @@ static bool do_v7m_function_return(ARMCPU *cpu)
return true;
}
-static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
+static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool secure,
uint32_t addr, uint16_t *insn)
{
/*
@@ -2003,8 +2003,7 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
ARMMMUFaultInfo fi = {};
MemTxResult txres;
- v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx,
- regime_is_secure(env, mmu_idx), &sattrs);
+ v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, secure, &sattrs);
if (!sattrs.nsc || sattrs.ns) {
/*
* This must be the second half of the insn, and it straddles a
@@ -2109,7 +2108,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
/* We want to do the MPU lookup as secure; work out what mmu_idx that is */
mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true);
- if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15], &insn)) {
+ if (!v7m_read_half_insn(cpu, mmu_idx, true, env->regs[15], &insn)) {
return false;
}
@@ -2125,7 +2124,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
goto gen_invep;
}
- if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15] + 2, &insn)) {
+ if (!v7m_read_half_insn(cpu, mmu_idx, true, env->regs[15] + 2, &insn)) {
return false;
}
--
2.25.1
next prev parent reply other threads:[~2022-10-10 14:41 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-10 14:27 [PULL 00/28] target-arm queue Peter Maydell
2022-10-10 14:27 ` [PULL 01/28] target/arm/kvm: Retry KVM_CREATE_VM call if it fails EINTR Peter Maydell
2022-10-10 14:27 ` [PULL 02/28] target/arm: allow setting SCR_EL3.EnTP2 when FEAT_SME is implemented Peter Maydell
2022-10-10 14:27 ` [PULL 03/28] docs/nuvoton: Update URL for images Peter Maydell
2022-10-10 14:27 ` [PULL 04/28] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr Peter Maydell
2022-10-10 14:27 ` [PULL 05/28] target/arm: Make the final stage1+2 write to secure be unconditional Peter Maydell
2022-10-10 14:27 ` [PULL 06/28] target/arm: Add is_secure parameter to get_phys_addr_lpae Peter Maydell
2022-10-10 14:27 ` [PULL 07/28] target/arm: Fix S2 disabled check in S1_ptw_translate Peter Maydell
2022-10-10 14:27 ` [PULL 08/28] target/arm: Add is_secure parameter to regime_translation_disabled Peter Maydell
2022-10-10 14:27 ` [PULL 09/28] target/arm: Split out get_phys_addr_with_secure Peter Maydell
2022-10-10 14:27 ` Peter Maydell [this message]
2022-10-10 14:27 ` [PULL 11/28] target/arm: Add TBFLAG_M32.SECURE Peter Maydell
2022-10-10 14:27 ` [PULL 12/28] target/arm: Merge regime_is_secure into get_phys_addr Peter Maydell
2022-10-10 14:27 ` [PULL 13/28] target/arm: Add is_secure parameter to do_ats_write Peter Maydell
2022-10-10 14:27 ` [PULL 14/28] target/arm: Fold secure and non-secure a-profile mmu indexes Peter Maydell
2022-10-10 14:27 ` [PULL 15/28] target/arm: Reorg regime_translation_disabled Peter Maydell
2022-10-10 14:27 ` [PULL 16/28] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M Peter Maydell
2022-10-10 14:27 ` [PULL 17/28] target/arm: Introduce arm_hcr_el2_eff_secstate Peter Maydell
2022-10-10 14:27 ` [PULL 18/28] target/arm: Hoist read of *is_secure in S1_ptw_translate Peter Maydell
2022-10-10 14:27 ` [PULL 19/28] target/arm: Remove env argument from combined_attrs_fwb Peter Maydell
2022-10-10 14:27 ` [PULL 20/28] target/arm: Pass HCR to attribute subroutines Peter Maydell
2022-10-10 14:27 ` [PULL 21/28] target/arm: Fix ATS12NSO* from S PL1 Peter Maydell
2022-10-10 14:27 ` [PULL 22/28] target/arm: Split out get_phys_addr_disabled Peter Maydell
2022-10-10 14:27 ` [PULL 23/28] target/arm: Fix cacheattr in get_phys_addr_disabled Peter Maydell
2022-10-10 14:27 ` [PULL 24/28] target/arm: Use tlb_set_page_full Peter Maydell
2022-10-10 14:27 ` [PULL 25/28] hw/arm/boot: set CPTR_EL3.ESM and SCR_EL3.EnTP2 when booting Linux with EL3 Peter Maydell
2022-10-10 14:27 ` [PULL 26/28] target/arm: Don't allow guest to use unimplemented granule sizes Peter Maydell
2022-10-10 14:27 ` [PULL 27/28] target/arm: Use ARMGranuleSize in ARMVAParameters Peter Maydell
2022-10-10 14:27 ` [PULL 28/28] docs/system/arm/emulation.rst: Report FEAT_GTG support Peter Maydell
2022-10-12 21:25 ` [PULL 00/28] target-arm queue Stefan Hajnoczi
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