From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 04/28] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr
Date: Mon, 10 Oct 2022 15:27:06 +0100 [thread overview]
Message-ID: <20221010142730.502083-5-peter.maydell@linaro.org> (raw)
In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
The starting security state comes with the translation regime,
not the current state of arm_is_secure_below_el3().
Create a new local variable, s2walk_secure, which does not need
to be written back to result->attrs.secure -- we compute that
value later, after the S2 walk is complete.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221001162318.153420-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 2ddfc028abb..b8c494ad9f0 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -2298,7 +2298,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
hwaddr ipa;
int s1_prot;
int ret;
- bool ipa_secure;
+ bool ipa_secure, s2walk_secure;
ARMCacheAttrs cacheattrs1;
ARMMMUIdx s2_mmu_idx;
bool is_el0;
@@ -2313,17 +2313,17 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
ipa = result->phys;
ipa_secure = result->attrs.secure;
- if (arm_is_secure_below_el3(env)) {
- if (ipa_secure) {
- result->attrs.secure = !(env->cp15.vstcr_el2 & VSTCR_SW);
- } else {
- result->attrs.secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
- }
+ if (is_secure) {
+ /* Select TCR based on the NS bit from the S1 walk. */
+ s2walk_secure = !(ipa_secure
+ ? env->cp15.vstcr_el2 & VSTCR_SW
+ : env->cp15.vtcr_el2 & VTCR_NSW);
} else {
assert(!ipa_secure);
+ s2walk_secure = false;
}
- s2_mmu_idx = (result->attrs.secure
+ s2_mmu_idx = (s2walk_secure
? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2);
is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0;
@@ -2366,7 +2366,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
result->cacheattrs);
/* Check if IPA translates to secure or non-secure PA space. */
- if (arm_is_secure_below_el3(env)) {
+ if (is_secure) {
if (ipa_secure) {
result->attrs.secure =
!(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW));
--
2.25.1
next prev parent reply other threads:[~2022-10-10 14:29 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-10 14:27 [PULL 00/28] target-arm queue Peter Maydell
2022-10-10 14:27 ` [PULL 01/28] target/arm/kvm: Retry KVM_CREATE_VM call if it fails EINTR Peter Maydell
2022-10-10 14:27 ` [PULL 02/28] target/arm: allow setting SCR_EL3.EnTP2 when FEAT_SME is implemented Peter Maydell
2022-10-10 14:27 ` [PULL 03/28] docs/nuvoton: Update URL for images Peter Maydell
2022-10-10 14:27 ` Peter Maydell [this message]
2022-10-10 14:27 ` [PULL 05/28] target/arm: Make the final stage1+2 write to secure be unconditional Peter Maydell
2022-10-10 14:27 ` [PULL 06/28] target/arm: Add is_secure parameter to get_phys_addr_lpae Peter Maydell
2022-10-10 14:27 ` [PULL 07/28] target/arm: Fix S2 disabled check in S1_ptw_translate Peter Maydell
2022-10-10 14:27 ` [PULL 08/28] target/arm: Add is_secure parameter to regime_translation_disabled Peter Maydell
2022-10-10 14:27 ` [PULL 09/28] target/arm: Split out get_phys_addr_with_secure Peter Maydell
2022-10-10 14:27 ` [PULL 10/28] target/arm: Add is_secure parameter to v7m_read_half_insn Peter Maydell
2022-10-10 14:27 ` [PULL 11/28] target/arm: Add TBFLAG_M32.SECURE Peter Maydell
2022-10-10 14:27 ` [PULL 12/28] target/arm: Merge regime_is_secure into get_phys_addr Peter Maydell
2022-10-10 14:27 ` [PULL 13/28] target/arm: Add is_secure parameter to do_ats_write Peter Maydell
2022-10-10 14:27 ` [PULL 14/28] target/arm: Fold secure and non-secure a-profile mmu indexes Peter Maydell
2022-10-10 14:27 ` [PULL 15/28] target/arm: Reorg regime_translation_disabled Peter Maydell
2022-10-10 14:27 ` [PULL 16/28] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M Peter Maydell
2022-10-10 14:27 ` [PULL 17/28] target/arm: Introduce arm_hcr_el2_eff_secstate Peter Maydell
2022-10-10 14:27 ` [PULL 18/28] target/arm: Hoist read of *is_secure in S1_ptw_translate Peter Maydell
2022-10-10 14:27 ` [PULL 19/28] target/arm: Remove env argument from combined_attrs_fwb Peter Maydell
2022-10-10 14:27 ` [PULL 20/28] target/arm: Pass HCR to attribute subroutines Peter Maydell
2022-10-10 14:27 ` [PULL 21/28] target/arm: Fix ATS12NSO* from S PL1 Peter Maydell
2022-10-10 14:27 ` [PULL 22/28] target/arm: Split out get_phys_addr_disabled Peter Maydell
2022-10-10 14:27 ` [PULL 23/28] target/arm: Fix cacheattr in get_phys_addr_disabled Peter Maydell
2022-10-10 14:27 ` [PULL 24/28] target/arm: Use tlb_set_page_full Peter Maydell
2022-10-10 14:27 ` [PULL 25/28] hw/arm/boot: set CPTR_EL3.ESM and SCR_EL3.EnTP2 when booting Linux with EL3 Peter Maydell
2022-10-10 14:27 ` [PULL 26/28] target/arm: Don't allow guest to use unimplemented granule sizes Peter Maydell
2022-10-10 14:27 ` [PULL 27/28] target/arm: Use ARMGranuleSize in ARMVAParameters Peter Maydell
2022-10-10 14:27 ` [PULL 28/28] docs/system/arm/emulation.rst: Report FEAT_GTG support Peter Maydell
2022-10-12 21:25 ` [PULL 00/28] target-arm queue Stefan Hajnoczi
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