From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 15/28] target/arm: Reorg regime_translation_disabled
Date: Mon, 10 Oct 2022 15:27:17 +0100 [thread overview]
Message-ID: <20221010142730.502083-16-peter.maydell@linaro.org> (raw)
In-Reply-To: <20221010142730.502083-1-peter.maydell@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
Use a switch on mmu_idx for the a-profile indexes, instead of
three different if's vs regime_el and arm_mmu_idx_is_stage1_of_2.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 32 +++++++++++++++++++++++++-------
1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 2055d684e63..a514a78c924 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -148,21 +148,39 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
hcr_el2 = arm_hcr_el2_eff(env);
- if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
+ switch (mmu_idx) {
+ case ARMMMUIdx_Stage2:
+ case ARMMMUIdx_Stage2_S:
/* HCR.DC means HCR.VM behaves as 1 */
return (hcr_el2 & (HCR_DC | HCR_VM)) == 0;
- }
- if (hcr_el2 & HCR_TGE) {
+ case ARMMMUIdx_E10_0:
+ case ARMMMUIdx_E10_1:
+ case ARMMMUIdx_E10_1_PAN:
/* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
- if (!is_secure && regime_el(env, mmu_idx) == 1) {
+ if (!is_secure && (hcr_el2 & HCR_TGE)) {
return true;
}
- }
+ break;
- if ((hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) {
+ case ARMMMUIdx_Stage1_E0:
+ case ARMMMUIdx_Stage1_E1:
+ case ARMMMUIdx_Stage1_E1_PAN:
/* HCR.DC means SCTLR_EL1.M behaves as 0 */
- return true;
+ if (hcr_el2 & HCR_DC) {
+ return true;
+ }
+ break;
+
+ case ARMMMUIdx_E20_0:
+ case ARMMMUIdx_E20_2:
+ case ARMMMUIdx_E20_2_PAN:
+ case ARMMMUIdx_E2:
+ case ARMMMUIdx_E3:
+ break;
+
+ default:
+ g_assert_not_reached();
}
return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
--
2.25.1
next prev parent reply other threads:[~2022-10-10 14:39 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-10 14:27 [PULL 00/28] target-arm queue Peter Maydell
2022-10-10 14:27 ` [PULL 01/28] target/arm/kvm: Retry KVM_CREATE_VM call if it fails EINTR Peter Maydell
2022-10-10 14:27 ` [PULL 02/28] target/arm: allow setting SCR_EL3.EnTP2 when FEAT_SME is implemented Peter Maydell
2022-10-10 14:27 ` [PULL 03/28] docs/nuvoton: Update URL for images Peter Maydell
2022-10-10 14:27 ` [PULL 04/28] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr Peter Maydell
2022-10-10 14:27 ` [PULL 05/28] target/arm: Make the final stage1+2 write to secure be unconditional Peter Maydell
2022-10-10 14:27 ` [PULL 06/28] target/arm: Add is_secure parameter to get_phys_addr_lpae Peter Maydell
2022-10-10 14:27 ` [PULL 07/28] target/arm: Fix S2 disabled check in S1_ptw_translate Peter Maydell
2022-10-10 14:27 ` [PULL 08/28] target/arm: Add is_secure parameter to regime_translation_disabled Peter Maydell
2022-10-10 14:27 ` [PULL 09/28] target/arm: Split out get_phys_addr_with_secure Peter Maydell
2022-10-10 14:27 ` [PULL 10/28] target/arm: Add is_secure parameter to v7m_read_half_insn Peter Maydell
2022-10-10 14:27 ` [PULL 11/28] target/arm: Add TBFLAG_M32.SECURE Peter Maydell
2022-10-10 14:27 ` [PULL 12/28] target/arm: Merge regime_is_secure into get_phys_addr Peter Maydell
2022-10-10 14:27 ` [PULL 13/28] target/arm: Add is_secure parameter to do_ats_write Peter Maydell
2022-10-10 14:27 ` [PULL 14/28] target/arm: Fold secure and non-secure a-profile mmu indexes Peter Maydell
2022-10-10 14:27 ` Peter Maydell [this message]
2022-10-10 14:27 ` [PULL 16/28] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M Peter Maydell
2022-10-10 14:27 ` [PULL 17/28] target/arm: Introduce arm_hcr_el2_eff_secstate Peter Maydell
2022-10-10 14:27 ` [PULL 18/28] target/arm: Hoist read of *is_secure in S1_ptw_translate Peter Maydell
2022-10-10 14:27 ` [PULL 19/28] target/arm: Remove env argument from combined_attrs_fwb Peter Maydell
2022-10-10 14:27 ` [PULL 20/28] target/arm: Pass HCR to attribute subroutines Peter Maydell
2022-10-10 14:27 ` [PULL 21/28] target/arm: Fix ATS12NSO* from S PL1 Peter Maydell
2022-10-10 14:27 ` [PULL 22/28] target/arm: Split out get_phys_addr_disabled Peter Maydell
2022-10-10 14:27 ` [PULL 23/28] target/arm: Fix cacheattr in get_phys_addr_disabled Peter Maydell
2022-10-10 14:27 ` [PULL 24/28] target/arm: Use tlb_set_page_full Peter Maydell
2022-10-10 14:27 ` [PULL 25/28] hw/arm/boot: set CPTR_EL3.ESM and SCR_EL3.EnTP2 when booting Linux with EL3 Peter Maydell
2022-10-10 14:27 ` [PULL 26/28] target/arm: Don't allow guest to use unimplemented granule sizes Peter Maydell
2022-10-10 14:27 ` [PULL 27/28] target/arm: Use ARMGranuleSize in ARMVAParameters Peter Maydell
2022-10-10 14:27 ` [PULL 28/28] docs/system/arm/emulation.rst: Report FEAT_GTG support Peter Maydell
2022-10-12 21:25 ` [PULL 00/28] target-arm queue Stefan Hajnoczi
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