From: Jisheng Zhang <jszhang@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, Guo Ren <guoren@kernel.org>
Subject: [PATCH 2/5] riscv: Add the T-HEAD SoC family Kconfig option
Date: Mon, 8 May 2023 02:23:01 +0800 [thread overview]
Message-ID: <20230507182304.2934-3-jszhang@kernel.org> (raw)
In-Reply-To: <20230507182304.2934-1-jszhang@kernel.org>
The first SoC in the T-HEAD series is light(a.k.a th1520), containing
quad T-HEAD C910 cores.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/riscv/Kconfig.socs | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 1cf69f958f10..ce10a38dff37 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -41,6 +41,12 @@ config ARCH_SUNXI
This enables support for Allwinner sun20i platform hardware,
including boards based on the D1 and D1s SoCs.
+config ARCH_THEAD
+ bool "T-HEAD RISC-V SoCs"
+ select ERRATA_THEAD
+ help
+ This enables support for the RISC-V based T-HEAD SoCs.
+
config ARCH_VIRT
def_bool SOC_VIRT
--
2.40.0
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WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, Guo Ren <guoren@kernel.org>
Subject: [PATCH 2/5] riscv: Add the T-HEAD SoC family Kconfig option
Date: Mon, 8 May 2023 02:23:01 +0800 [thread overview]
Message-ID: <20230507182304.2934-3-jszhang@kernel.org> (raw)
In-Reply-To: <20230507182304.2934-1-jszhang@kernel.org>
The first SoC in the T-HEAD series is light(a.k.a th1520), containing
quad T-HEAD C910 cores.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/riscv/Kconfig.socs | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 1cf69f958f10..ce10a38dff37 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -41,6 +41,12 @@ config ARCH_SUNXI
This enables support for Allwinner sun20i platform hardware,
including boards based on the D1 and D1s SoCs.
+config ARCH_THEAD
+ bool "T-HEAD RISC-V SoCs"
+ select ERRATA_THEAD
+ help
+ This enables support for the RISC-V based T-HEAD SoCs.
+
config ARCH_VIRT
def_bool SOC_VIRT
--
2.40.0
next prev parent reply other threads:[~2023-05-07 18:34 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-07 18:22 [PATCH 0/5] Add Sipeed Lichee Pi 4A RISC-V board support Jisheng Zhang
2023-05-07 18:22 ` Jisheng Zhang
2023-05-07 18:23 ` [PATCH 1/5] irqchip/sifive-plic: Support T-HEAD's C910 PLIC Jisheng Zhang
2023-05-07 18:23 ` Jisheng Zhang
2023-05-07 21:18 ` Conor Dooley
2023-05-07 21:18 ` Conor Dooley
2023-05-08 3:14 ` Icenowy Zheng
2023-05-08 3:14 ` Icenowy Zheng
2023-05-08 6:52 ` Guo Ren
2023-05-08 6:52 ` Guo Ren
2023-05-08 7:07 ` Conor Dooley
2023-05-08 7:07 ` Conor Dooley
2023-05-08 16:09 ` Jisheng Zhang
2023-05-08 16:09 ` Jisheng Zhang
2023-05-08 9:17 ` Krzysztof Kozlowski
2023-05-08 9:17 ` Krzysztof Kozlowski
2023-05-07 18:23 ` Jisheng Zhang [this message]
2023-05-07 18:23 ` [PATCH 2/5] riscv: Add the T-HEAD SoC family Kconfig option Jisheng Zhang
2023-05-07 21:22 ` Conor Dooley
2023-05-07 21:22 ` Conor Dooley
2023-05-08 6:42 ` Guo Ren
2023-05-08 6:42 ` Guo Ren
2023-05-08 6:52 ` Conor Dooley
2023-05-08 6:52 ` Conor Dooley
2023-05-08 6:58 ` Guo Ren
2023-05-08 6:58 ` Guo Ren
2023-05-08 7:04 ` Conor Dooley
2023-05-08 7:04 ` Conor Dooley
2023-05-07 18:23 ` [PATCH 3/5] riscv: dts: add initial T-HEAD light SoC device tree Jisheng Zhang
2023-05-07 18:23 ` Jisheng Zhang
2023-05-07 21:35 ` Conor Dooley
2023-05-07 21:35 ` Conor Dooley
2023-05-08 3:32 ` Icenowy Zheng
2023-05-08 3:32 ` Icenowy Zheng
2023-05-08 7:01 ` Conor Dooley
2023-05-08 7:01 ` Conor Dooley
2023-05-08 8:23 ` Heiko Stübner
2023-05-08 8:23 ` Heiko Stübner
2023-05-08 8:35 ` Conor Dooley
2023-05-08 8:35 ` Conor Dooley
2023-05-08 15:56 ` Heiko Stübner
2023-05-08 15:56 ` Heiko Stübner
2023-05-08 16:26 ` Jisheng Zhang
2023-05-08 16:26 ` Jisheng Zhang
2023-05-08 16:44 ` Conor Dooley
2023-05-08 16:44 ` Conor Dooley
2023-05-08 17:09 ` Heiko Stübner
2023-05-08 17:09 ` Heiko Stübner
2023-05-21 15:37 ` Guo Ren
2023-05-21 15:37 ` Guo Ren
2023-05-21 17:08 ` Conor Dooley
2023-05-21 17:08 ` Conor Dooley
2023-05-22 1:36 ` Guo Ren
2023-05-22 1:36 ` Guo Ren
2023-05-08 9:20 ` Krzysztof Kozlowski
2023-05-08 9:20 ` Krzysztof Kozlowski
2023-05-07 18:23 ` [PATCH 4/5] riscv: dts: thead: add sipeed Lichee Pi 4A board " Jisheng Zhang
2023-05-07 18:23 ` Jisheng Zhang
2023-05-07 21:27 ` Conor Dooley
2023-05-07 21:27 ` Conor Dooley
2023-05-08 6:44 ` Guo Ren
2023-05-08 6:44 ` Guo Ren
2023-05-07 18:23 ` [PATCH 5/5] MAINTAINERS: add entry for T-HEAD RISC-V SoC Jisheng Zhang
2023-05-07 18:23 ` Jisheng Zhang
2023-05-07 21:21 ` Conor Dooley
2023-05-07 21:21 ` Conor Dooley
2023-05-08 16:17 ` Jisheng Zhang
2023-05-08 16:17 ` Jisheng Zhang
2023-05-08 17:23 ` Conor Dooley
2023-05-08 17:23 ` Conor Dooley
2023-05-08 6:22 ` Guo Ren
2023-05-08 6:22 ` Guo Ren
2023-05-08 6:16 ` [PATCH 0/5] Add Sipeed Lichee Pi 4A RISC-V board support Guo Ren
2023-05-08 6:16 ` Guo Ren
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