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From: Andrew Jones <ajones@ventanamicro.com>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: devicetree@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>,
	linux-kernel@vger.kernel.org, conor@kernel.org,
	Rob Herring <robh+dt@kernel.org>,
	palmer@dabbelt.com,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	linux-riscv@lists.infradead.org,
	Heiko Stuebner <heiko.stuebner@vrull.eu>,
	Evan Green <evan@rivosinc.com>
Subject: Re: [PATCH v1 9/9] RISC-V: try new extension properties in of_early_processor_hartid()
Date: Mon, 26 Jun 2023 18:25:28 +0200	[thread overview]
Message-ID: <20230626-9ed40a55c71d2fe50ed3b8da@orel> (raw)
In-Reply-To: <20230626-ardently-caress-7c5886566ea6@wendy>

On Mon, Jun 26, 2023 at 12:19:47PM +0100, Conor Dooley wrote:
> To fully deprecate the kernel's use of "riscv,isa",
> of_early_processor_hartid() needs to first try using the new properties,
> before falling back to "riscv,isa".
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  arch/riscv/kernel/cpu.c | 23 ++++++++++++++++++++++-
>  1 file changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index 046d9d3dac16..332574f27c95 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -61,8 +61,29 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har
>  		return -ENODEV;
>  	}
>  
> +	if (of_property_read_string(node, "riscv,isa-base", &isa))
> +		goto old_interface;
> +
> +	if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32i", 5))
> +		return -ENODEV;
> +
> +	if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64i", 5))
> +		return -ENODEV;
> +
> +	if (!of_property_present(node, "riscv,isa-extensions"))
> +		return -ENODEV;
> +
> +	if (of_property_match_string(node, "riscv,isa-extensions", "i") < 0 ||
> +	    of_property_match_string(node, "riscv,isa-extensions", "m") < 0 ||
> +	    of_property_match_string(node, "riscv,isa-extensions", "a") < 0)
> +		return -ENODEV;
> +
> +	return 0;
> +
> +old_interface:
>  	if (of_property_read_string(node, "riscv,isa", &isa)) {
> -		pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart);
> +		pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n",
> +			*hart);
>  		return -ENODEV;
>  	}
>  
> -- 
> 2.40.1
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

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WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jones <ajones@ventanamicro.com>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: palmer@dabbelt.com, conor@kernel.org,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Heiko Stuebner <heiko.stuebner@vrull.eu>,
	Evan Green <evan@rivosinc.com>,
	Sunil V L <sunilvl@ventanamicro.com>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 9/9] RISC-V: try new extension properties in of_early_processor_hartid()
Date: Mon, 26 Jun 2023 18:25:28 +0200	[thread overview]
Message-ID: <20230626-9ed40a55c71d2fe50ed3b8da@orel> (raw)
In-Reply-To: <20230626-ardently-caress-7c5886566ea6@wendy>

On Mon, Jun 26, 2023 at 12:19:47PM +0100, Conor Dooley wrote:
> To fully deprecate the kernel's use of "riscv,isa",
> of_early_processor_hartid() needs to first try using the new properties,
> before falling back to "riscv,isa".
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  arch/riscv/kernel/cpu.c | 23 ++++++++++++++++++++++-
>  1 file changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index 046d9d3dac16..332574f27c95 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -61,8 +61,29 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har
>  		return -ENODEV;
>  	}
>  
> +	if (of_property_read_string(node, "riscv,isa-base", &isa))
> +		goto old_interface;
> +
> +	if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32i", 5))
> +		return -ENODEV;
> +
> +	if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64i", 5))
> +		return -ENODEV;
> +
> +	if (!of_property_present(node, "riscv,isa-extensions"))
> +		return -ENODEV;
> +
> +	if (of_property_match_string(node, "riscv,isa-extensions", "i") < 0 ||
> +	    of_property_match_string(node, "riscv,isa-extensions", "m") < 0 ||
> +	    of_property_match_string(node, "riscv,isa-extensions", "a") < 0)
> +		return -ENODEV;
> +
> +	return 0;
> +
> +old_interface:
>  	if (of_property_read_string(node, "riscv,isa", &isa)) {
> -		pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart);
> +		pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n",
> +			*hart);
>  		return -ENODEV;
>  	}
>  
> -- 
> 2.40.1
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

  reply	other threads:[~2023-06-26 16:25 UTC|newest]

Thread overview: 66+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-26 11:19 [PATCH v1 0/9] RISC-V: Probe DT extension support using riscv,isa-extensions & riscv,isa-base Conor Dooley
2023-06-26 11:19 ` Conor Dooley
2023-06-26 11:19 ` [PATCH v1 1/9] RISC-V: don't parse dt/acpi isa string to get rv32/rv64 Conor Dooley
2023-06-26 11:19   ` Conor Dooley
2023-06-26 15:14   ` Andrew Jones
2023-06-26 15:14     ` Andrew Jones
2023-06-26 15:51     ` Conor Dooley
2023-06-26 15:51       ` Conor Dooley
2023-06-26 16:05       ` Andrew Jones
2023-06-26 16:05         ` Andrew Jones
2023-06-26 16:16         ` Conor Dooley
2023-06-26 16:16           ` Conor Dooley
2023-06-27  8:02           ` Sunil V L
2023-06-27  8:02             ` Sunil V L
2023-06-27  8:51             ` Conor Dooley
2023-06-27  8:51               ` Conor Dooley
2023-06-27  9:20               ` Sunil V L
2023-06-27  9:20                 ` Sunil V L
2023-06-26 11:19 ` [PATCH v1 2/9] RISC-V: drop a needless check in print_isa_ext() Conor Dooley
2023-06-26 11:19   ` Conor Dooley
2023-06-26 15:19   ` Andrew Jones
2023-06-26 15:19     ` Andrew Jones
2023-06-26 16:08     ` Conor Dooley
2023-06-26 16:08       ` Conor Dooley
2023-06-26 16:29       ` Andrew Jones
2023-06-26 16:29         ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 3/9] RISC-V: shunt isa_ext_arr to cpufeature.c Conor Dooley
2023-06-26 11:19   ` Conor Dooley
2023-06-26 15:29   ` Andrew Jones
2023-06-26 15:29     ` Andrew Jones
2023-06-26 15:44     ` Andrew Jones
2023-06-26 15:44       ` Andrew Jones
2023-06-26 15:59       ` Conor Dooley
2023-06-26 15:59         ` Conor Dooley
2023-06-26 11:19 ` [PATCH v1 4/9] RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap() Conor Dooley
2023-06-26 11:19   ` Conor Dooley
2023-06-26 15:33   ` Andrew Jones
2023-06-26 15:33     ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 5/9] RISC-V: add missing single letter extension definitions Conor Dooley
2023-06-26 11:19   ` Conor Dooley
2023-06-26 15:34   ` Andrew Jones
2023-06-26 15:34     ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 6/9] RISC-V: add single letter extensions to riscv_isa_ext Conor Dooley
2023-06-26 11:19   ` Conor Dooley
2023-06-26 15:42   ` Andrew Jones
2023-06-26 15:42     ` Andrew Jones
2023-06-28 17:33   ` Evan Green
2023-06-28 17:33     ` Evan Green
2023-06-28 17:43     ` Conor Dooley
2023-06-28 17:43       ` Conor Dooley
2023-06-28 17:50       ` Evan Green
2023-06-28 17:50         ` Evan Green
2023-06-26 11:19 ` [PATCH v1 7/9] RISC-V: split riscv_fill_hwcap() in 3 Conor Dooley
2023-06-26 11:19   ` Conor Dooley
2023-06-26 16:17   ` Andrew Jones
2023-06-26 16:17     ` Andrew Jones
2023-06-27 17:42     ` Conor Dooley
2023-06-27 17:42       ` Conor Dooley
2023-06-26 11:19 ` [PATCH v1 8/9] RISC-V: enable extension detection from new properties Conor Dooley
2023-06-26 11:19   ` Conor Dooley
2023-06-26 16:24   ` Andrew Jones
2023-06-26 16:24     ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 9/9] RISC-V: try new extension properties in of_early_processor_hartid() Conor Dooley
2023-06-26 11:19   ` Conor Dooley
2023-06-26 16:25   ` Andrew Jones [this message]
2023-06-26 16:25     ` Andrew Jones

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