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From: Conor Dooley <conor@kernel.org>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: devicetree@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>,
	linux-kernel@vger.kernel.org,
	Conor Dooley <conor.dooley@microchip.com>,
	Rob Herring <robh+dt@kernel.org>,
	palmer@dabbelt.com,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	linux-riscv@lists.infradead.org,
	Heiko Stuebner <heiko.stuebner@vrull.eu>,
	Evan Green <evan@rivosinc.com>
Subject: Re: [PATCH v1 1/9] RISC-V: don't parse dt/acpi isa string to get rv32/rv64
Date: Mon, 26 Jun 2023 16:51:29 +0100	[thread overview]
Message-ID: <20230626-dragonish-romp-9acf4846ae01@spud> (raw)
In-Reply-To: <20230626-e3ea7beb39c584bfbf7ee836@orel>


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On Mon, Jun 26, 2023 at 05:14:15PM +0200, Andrew Jones wrote:
> On Mon, Jun 26, 2023 at 12:19:39PM +0100, Conor Dooley wrote:
> > From: Heiko Stuebner <heiko.stuebner@vrull.eu>
> > @@ -333,8 +335,6 @@ static int c_show(struct seq_file *m, void *v)
> >  
> >  		of_node_put(node);
> >  	} else {
> > -		if (!acpi_get_riscv_isa(NULL, cpu_id, &isa))
> > -			print_isa(m, isa);
> >  
> 
> Extra blank line here to remove. Actually the whole 'else' can be removed
> because the print_mmu() call can be brought up above the
> 'if (acpi_disabled)'

Can it be? I intentionally did not make that change - wasn't sure
whether re-ordering the fields in there was permissible.

One of the few things I know does parsing of /proc/cpuinfo is:
https://github.com/google/cpu_features/blob/main/src/impl_riscv_linux.c
and that doesn't seem to care about the mmu, but does rely on
vendor/uarch ordering.

Makes me wonder, does ACPI break things by leaving out uarch/vendor
fields, if there is something that expects them to exist? We should
not intentionally break stuff in /proc/cpuinfo, but can't say I feel any
sympathy for naively parsing it.

> >  		print_mmu(m);


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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: Conor Dooley <conor.dooley@microchip.com>,
	palmer@dabbelt.com, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Heiko Stuebner <heiko.stuebner@vrull.eu>,
	Evan Green <evan@rivosinc.com>,
	Sunil V L <sunilvl@ventanamicro.com>,
	linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 1/9] RISC-V: don't parse dt/acpi isa string to get rv32/rv64
Date: Mon, 26 Jun 2023 16:51:29 +0100	[thread overview]
Message-ID: <20230626-dragonish-romp-9acf4846ae01@spud> (raw)
In-Reply-To: <20230626-e3ea7beb39c584bfbf7ee836@orel>

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On Mon, Jun 26, 2023 at 05:14:15PM +0200, Andrew Jones wrote:
> On Mon, Jun 26, 2023 at 12:19:39PM +0100, Conor Dooley wrote:
> > From: Heiko Stuebner <heiko.stuebner@vrull.eu>
> > @@ -333,8 +335,6 @@ static int c_show(struct seq_file *m, void *v)
> >  
> >  		of_node_put(node);
> >  	} else {
> > -		if (!acpi_get_riscv_isa(NULL, cpu_id, &isa))
> > -			print_isa(m, isa);
> >  
> 
> Extra blank line here to remove. Actually the whole 'else' can be removed
> because the print_mmu() call can be brought up above the
> 'if (acpi_disabled)'

Can it be? I intentionally did not make that change - wasn't sure
whether re-ordering the fields in there was permissible.

One of the few things I know does parsing of /proc/cpuinfo is:
https://github.com/google/cpu_features/blob/main/src/impl_riscv_linux.c
and that doesn't seem to care about the mmu, but does rely on
vendor/uarch ordering.

Makes me wonder, does ACPI break things by leaving out uarch/vendor
fields, if there is something that expects them to exist? We should
not intentionally break stuff in /proc/cpuinfo, but can't say I feel any
sympathy for naively parsing it.

> >  		print_mmu(m);


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  reply	other threads:[~2023-06-26 15:51 UTC|newest]

Thread overview: 66+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-26 11:19 [PATCH v1 0/9] RISC-V: Probe DT extension support using riscv,isa-extensions & riscv,isa-base Conor Dooley
2023-06-26 11:19 ` Conor Dooley
2023-06-26 11:19 ` [PATCH v1 1/9] RISC-V: don't parse dt/acpi isa string to get rv32/rv64 Conor Dooley
2023-06-26 11:19   ` Conor Dooley
2023-06-26 15:14   ` Andrew Jones
2023-06-26 15:14     ` Andrew Jones
2023-06-26 15:51     ` Conor Dooley [this message]
2023-06-26 15:51       ` Conor Dooley
2023-06-26 16:05       ` Andrew Jones
2023-06-26 16:05         ` Andrew Jones
2023-06-26 16:16         ` Conor Dooley
2023-06-26 16:16           ` Conor Dooley
2023-06-27  8:02           ` Sunil V L
2023-06-27  8:02             ` Sunil V L
2023-06-27  8:51             ` Conor Dooley
2023-06-27  8:51               ` Conor Dooley
2023-06-27  9:20               ` Sunil V L
2023-06-27  9:20                 ` Sunil V L
2023-06-26 11:19 ` [PATCH v1 2/9] RISC-V: drop a needless check in print_isa_ext() Conor Dooley
2023-06-26 11:19   ` Conor Dooley
2023-06-26 15:19   ` Andrew Jones
2023-06-26 15:19     ` Andrew Jones
2023-06-26 16:08     ` Conor Dooley
2023-06-26 16:08       ` Conor Dooley
2023-06-26 16:29       ` Andrew Jones
2023-06-26 16:29         ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 3/9] RISC-V: shunt isa_ext_arr to cpufeature.c Conor Dooley
2023-06-26 11:19   ` Conor Dooley
2023-06-26 15:29   ` Andrew Jones
2023-06-26 15:29     ` Andrew Jones
2023-06-26 15:44     ` Andrew Jones
2023-06-26 15:44       ` Andrew Jones
2023-06-26 15:59       ` Conor Dooley
2023-06-26 15:59         ` Conor Dooley
2023-06-26 11:19 ` [PATCH v1 4/9] RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap() Conor Dooley
2023-06-26 11:19   ` Conor Dooley
2023-06-26 15:33   ` Andrew Jones
2023-06-26 15:33     ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 5/9] RISC-V: add missing single letter extension definitions Conor Dooley
2023-06-26 11:19   ` Conor Dooley
2023-06-26 15:34   ` Andrew Jones
2023-06-26 15:34     ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 6/9] RISC-V: add single letter extensions to riscv_isa_ext Conor Dooley
2023-06-26 11:19   ` Conor Dooley
2023-06-26 15:42   ` Andrew Jones
2023-06-26 15:42     ` Andrew Jones
2023-06-28 17:33   ` Evan Green
2023-06-28 17:33     ` Evan Green
2023-06-28 17:43     ` Conor Dooley
2023-06-28 17:43       ` Conor Dooley
2023-06-28 17:50       ` Evan Green
2023-06-28 17:50         ` Evan Green
2023-06-26 11:19 ` [PATCH v1 7/9] RISC-V: split riscv_fill_hwcap() in 3 Conor Dooley
2023-06-26 11:19   ` Conor Dooley
2023-06-26 16:17   ` Andrew Jones
2023-06-26 16:17     ` Andrew Jones
2023-06-27 17:42     ` Conor Dooley
2023-06-27 17:42       ` Conor Dooley
2023-06-26 11:19 ` [PATCH v1 8/9] RISC-V: enable extension detection from new properties Conor Dooley
2023-06-26 11:19   ` Conor Dooley
2023-06-26 16:24   ` Andrew Jones
2023-06-26 16:24     ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 9/9] RISC-V: try new extension properties in of_early_processor_hartid() Conor Dooley
2023-06-26 11:19   ` Conor Dooley
2023-06-26 16:25   ` Andrew Jones
2023-06-26 16:25     ` Andrew Jones

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