From: Conor Dooley <conor.dooley@microchip.com>
To: <palmer@dabbelt.com>
Cc: devicetree@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>,
linux-kernel@vger.kernel.org, conor@kernel.org,
conor.dooley@microchip.com, Rob Herring <robh+dt@kernel.org>,
Evan Green <evan@rivosinc.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org,
Heiko Stuebner <heiko.stuebner@vrull.eu>,
Andrew Jones <ajones@ventanamicro.com>
Subject: [PATCH v1 4/9] RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap()
Date: Mon, 26 Jun 2023 12:19:42 +0100 [thread overview]
Message-ID: <20230626-thieving-jockstrap-d35d20b535c5@wendy> (raw)
In-Reply-To: <20230626-provable-angrily-81760e8c3cc6@wendy>
In riscv_fill_hwcap() riscv_isa_ext array can be looped over, rather
than duplicating the list of extensions with individual
SET_ISA_EXT_MAP() usage. While at it, drop the statement-of-the-obvious
comments from the struct, rename uprop to something more suitable for
its new use & constify the members.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/include/asm/hwcap.h | 6 ++----
arch/riscv/kernel/cpu.c | 5 +++--
arch/riscv/kernel/cpufeature.c | 26 +++++++-------------------
3 files changed, 12 insertions(+), 25 deletions(-)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 7a57e6109aef..36f46dfd2b87 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -70,10 +70,8 @@
unsigned long riscv_get_elf_hwcap(void);
struct riscv_isa_ext_data {
- /* Name of the extension displayed to userspace via /proc/cpuinfo */
- char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
- /* The logical ISA extension ID */
- unsigned int isa_ext_id;
+ const unsigned int id;
+ const char *name;
};
extern const struct riscv_isa_ext_data riscv_isa_ext[];
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 61fb92e7d524..beb8b16bbf87 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -164,9 +164,10 @@ static void print_isa_ext(struct seq_file *f)
{
for (int i = 0; i < riscv_isa_ext_count; i++) {
const struct riscv_isa_ext_data *edata = &riscv_isa_ext[i];
- if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id))
+ if (!__riscv_isa_extension_available(NULL, edata->id))
continue;
- seq_printf(f, "_%s", edata->uprop);
+
+ seq_printf(f, "_%s", edata->name);
}
}
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index f0ae310006de..b5e23506c4f0 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -99,11 +99,10 @@ static bool riscv_isa_extension_check(int id)
return true;
}
-#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \
- { \
- .uprop = #UPROP, \
- .isa_ext_id = EXTID, \
- }
+#define __RISCV_ISA_EXT_DATA(_name, _id) { \
+ .name = #_name, \
+ .id = _id, \
+}
/*
* The canonical order of ISA extension names in the ISA string is defined in
@@ -367,20 +366,9 @@ void __init riscv_fill_hwcap(void)
set_bit(nr, isainfo->isa);
}
} else {
- /* sorted alphabetically */
- SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA);
- SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA);
- SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
- SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
- SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
- SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT);
- SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
- SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA);
- SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
- SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS);
- SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
- SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ);
- SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
+ for (int i = 0; i < riscv_isa_ext_count; i++)
+ SET_ISA_EXT_MAP(riscv_isa_ext[i].name,
+ riscv_isa_ext[i].id);
}
#undef SET_ISA_EXT_MAP
}
--
2.40.1
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WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor.dooley@microchip.com>
To: <palmer@dabbelt.com>
Cc: <conor@kernel.org>, <conor.dooley@microchip.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Andrew Jones <ajones@ventanamicro.com>,
Heiko Stuebner <heiko.stuebner@vrull.eu>,
"Evan Green" <evan@rivosinc.com>,
Sunil V L <sunilvl@ventanamicro.com>,
<linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH v1 4/9] RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap()
Date: Mon, 26 Jun 2023 12:19:42 +0100 [thread overview]
Message-ID: <20230626-thieving-jockstrap-d35d20b535c5@wendy> (raw)
In-Reply-To: <20230626-provable-angrily-81760e8c3cc6@wendy>
In riscv_fill_hwcap() riscv_isa_ext array can be looped over, rather
than duplicating the list of extensions with individual
SET_ISA_EXT_MAP() usage. While at it, drop the statement-of-the-obvious
comments from the struct, rename uprop to something more suitable for
its new use & constify the members.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/include/asm/hwcap.h | 6 ++----
arch/riscv/kernel/cpu.c | 5 +++--
arch/riscv/kernel/cpufeature.c | 26 +++++++-------------------
3 files changed, 12 insertions(+), 25 deletions(-)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 7a57e6109aef..36f46dfd2b87 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -70,10 +70,8 @@
unsigned long riscv_get_elf_hwcap(void);
struct riscv_isa_ext_data {
- /* Name of the extension displayed to userspace via /proc/cpuinfo */
- char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
- /* The logical ISA extension ID */
- unsigned int isa_ext_id;
+ const unsigned int id;
+ const char *name;
};
extern const struct riscv_isa_ext_data riscv_isa_ext[];
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 61fb92e7d524..beb8b16bbf87 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -164,9 +164,10 @@ static void print_isa_ext(struct seq_file *f)
{
for (int i = 0; i < riscv_isa_ext_count; i++) {
const struct riscv_isa_ext_data *edata = &riscv_isa_ext[i];
- if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id))
+ if (!__riscv_isa_extension_available(NULL, edata->id))
continue;
- seq_printf(f, "_%s", edata->uprop);
+
+ seq_printf(f, "_%s", edata->name);
}
}
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index f0ae310006de..b5e23506c4f0 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -99,11 +99,10 @@ static bool riscv_isa_extension_check(int id)
return true;
}
-#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \
- { \
- .uprop = #UPROP, \
- .isa_ext_id = EXTID, \
- }
+#define __RISCV_ISA_EXT_DATA(_name, _id) { \
+ .name = #_name, \
+ .id = _id, \
+}
/*
* The canonical order of ISA extension names in the ISA string is defined in
@@ -367,20 +366,9 @@ void __init riscv_fill_hwcap(void)
set_bit(nr, isainfo->isa);
}
} else {
- /* sorted alphabetically */
- SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA);
- SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA);
- SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
- SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
- SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
- SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT);
- SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
- SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA);
- SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
- SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS);
- SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
- SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ);
- SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);
+ for (int i = 0; i < riscv_isa_ext_count; i++)
+ SET_ISA_EXT_MAP(riscv_isa_ext[i].name,
+ riscv_isa_ext[i].id);
}
#undef SET_ISA_EXT_MAP
}
--
2.40.1
next prev parent reply other threads:[~2023-06-26 11:21 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-26 11:19 [PATCH v1 0/9] RISC-V: Probe DT extension support using riscv,isa-extensions & riscv,isa-base Conor Dooley
2023-06-26 11:19 ` Conor Dooley
2023-06-26 11:19 ` [PATCH v1 1/9] RISC-V: don't parse dt/acpi isa string to get rv32/rv64 Conor Dooley
2023-06-26 11:19 ` Conor Dooley
2023-06-26 15:14 ` Andrew Jones
2023-06-26 15:14 ` Andrew Jones
2023-06-26 15:51 ` Conor Dooley
2023-06-26 15:51 ` Conor Dooley
2023-06-26 16:05 ` Andrew Jones
2023-06-26 16:05 ` Andrew Jones
2023-06-26 16:16 ` Conor Dooley
2023-06-26 16:16 ` Conor Dooley
2023-06-27 8:02 ` Sunil V L
2023-06-27 8:02 ` Sunil V L
2023-06-27 8:51 ` Conor Dooley
2023-06-27 8:51 ` Conor Dooley
2023-06-27 9:20 ` Sunil V L
2023-06-27 9:20 ` Sunil V L
2023-06-26 11:19 ` [PATCH v1 2/9] RISC-V: drop a needless check in print_isa_ext() Conor Dooley
2023-06-26 11:19 ` Conor Dooley
2023-06-26 15:19 ` Andrew Jones
2023-06-26 15:19 ` Andrew Jones
2023-06-26 16:08 ` Conor Dooley
2023-06-26 16:08 ` Conor Dooley
2023-06-26 16:29 ` Andrew Jones
2023-06-26 16:29 ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 3/9] RISC-V: shunt isa_ext_arr to cpufeature.c Conor Dooley
2023-06-26 11:19 ` Conor Dooley
2023-06-26 15:29 ` Andrew Jones
2023-06-26 15:29 ` Andrew Jones
2023-06-26 15:44 ` Andrew Jones
2023-06-26 15:44 ` Andrew Jones
2023-06-26 15:59 ` Conor Dooley
2023-06-26 15:59 ` Conor Dooley
2023-06-26 11:19 ` Conor Dooley [this message]
2023-06-26 11:19 ` [PATCH v1 4/9] RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap() Conor Dooley
2023-06-26 15:33 ` Andrew Jones
2023-06-26 15:33 ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 5/9] RISC-V: add missing single letter extension definitions Conor Dooley
2023-06-26 11:19 ` Conor Dooley
2023-06-26 15:34 ` Andrew Jones
2023-06-26 15:34 ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 6/9] RISC-V: add single letter extensions to riscv_isa_ext Conor Dooley
2023-06-26 11:19 ` Conor Dooley
2023-06-26 15:42 ` Andrew Jones
2023-06-26 15:42 ` Andrew Jones
2023-06-28 17:33 ` Evan Green
2023-06-28 17:33 ` Evan Green
2023-06-28 17:43 ` Conor Dooley
2023-06-28 17:43 ` Conor Dooley
2023-06-28 17:50 ` Evan Green
2023-06-28 17:50 ` Evan Green
2023-06-26 11:19 ` [PATCH v1 7/9] RISC-V: split riscv_fill_hwcap() in 3 Conor Dooley
2023-06-26 11:19 ` Conor Dooley
2023-06-26 16:17 ` Andrew Jones
2023-06-26 16:17 ` Andrew Jones
2023-06-27 17:42 ` Conor Dooley
2023-06-27 17:42 ` Conor Dooley
2023-06-26 11:19 ` [PATCH v1 8/9] RISC-V: enable extension detection from new properties Conor Dooley
2023-06-26 11:19 ` Conor Dooley
2023-06-26 16:24 ` Andrew Jones
2023-06-26 16:24 ` Andrew Jones
2023-06-26 11:19 ` [PATCH v1 9/9] RISC-V: try new extension properties in of_early_processor_hartid() Conor Dooley
2023-06-26 11:19 ` Conor Dooley
2023-06-26 16:25 ` Andrew Jones
2023-06-26 16:25 ` Andrew Jones
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