From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH 5/6] tty: Add SBI debug console support to HVC SBI driver
Date: Tue, 10 Oct 2023 19:12:42 +0200 [thread overview]
Message-ID: <2023101045-hazard-popcorn-7d19@gregkh> (raw)
In-Reply-To: <20231010170503.657189-6-apatel@ventanamicro.com>
On Tue, Oct 10, 2023 at 10:35:02PM +0530, Anup Patel wrote:
> --- a/drivers/tty/hvc/hvc_riscv_sbi.c
> +++ b/drivers/tty/hvc/hvc_riscv_sbi.c
> @@ -15,6 +15,7 @@
>
> #include "hvc_console.h"
>
> +#ifdef CONFIG_RISCV_SBI_V01
Please no #ifdef in a .c file, that's not a good style for Linux code at
all.
And what if you want to build the driver for both options here? What
will happen?
> +static int hvc_sbi_dbcn_tty_put(uint32_t vtermno, const char *buf, int count)
> {
> - return PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_ops, 16));
> + phys_addr_t pa;
> + struct sbiret ret;
> +
> + if (is_vmalloc_addr(buf))
> + pa = page_to_phys(vmalloc_to_page(buf)) + offset_in_page(buf);
> + else
> + pa = __pa(buf);
> +
> + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE,
> +#ifdef CONFIG_32BIT
> + count, pa, (u64)pa >> 32,
> +#else
> + count, pa, 0,
> +#endif
This is not how to do an api, sorry, again, please no #ifdef if you want
to support this code for the next 20+ years.
thanks,
gre gk-h
WARNING: multiple messages have this Message-ID (diff)
From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Atish Patra <atishp@atishpatra.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Jiri Slaby <jirislaby@kernel.org>,
Conor Dooley <conor@kernel.org>,
Andrew Jones <ajones@ventanamicro.com>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,
Atish Patra <atishp@rivosinc.com>
Subject: Re: [PATCH 5/6] tty: Add SBI debug console support to HVC SBI driver
Date: Tue, 10 Oct 2023 19:12:42 +0200 [thread overview]
Message-ID: <2023101045-hazard-popcorn-7d19@gregkh> (raw)
In-Reply-To: <20231010170503.657189-6-apatel@ventanamicro.com>
On Tue, Oct 10, 2023 at 10:35:02PM +0530, Anup Patel wrote:
> --- a/drivers/tty/hvc/hvc_riscv_sbi.c
> +++ b/drivers/tty/hvc/hvc_riscv_sbi.c
> @@ -15,6 +15,7 @@
>
> #include "hvc_console.h"
>
> +#ifdef CONFIG_RISCV_SBI_V01
Please no #ifdef in a .c file, that's not a good style for Linux code at
all.
And what if you want to build the driver for both options here? What
will happen?
> +static int hvc_sbi_dbcn_tty_put(uint32_t vtermno, const char *buf, int count)
> {
> - return PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_ops, 16));
> + phys_addr_t pa;
> + struct sbiret ret;
> +
> + if (is_vmalloc_addr(buf))
> + pa = page_to_phys(vmalloc_to_page(buf)) + offset_in_page(buf);
> + else
> + pa = __pa(buf);
> +
> + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE,
> +#ifdef CONFIG_32BIT
> + count, pa, (u64)pa >> 32,
> +#else
> + count, pa, 0,
> +#endif
This is not how to do an api, sorry, again, please no #ifdef if you want
to support this code for the next 20+ years.
thanks,
gre gk-h
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linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Atish Patra <atishp@atishpatra.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Jiri Slaby <jirislaby@kernel.org>,
Conor Dooley <conor@kernel.org>,
Andrew Jones <ajones@ventanamicro.com>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,
Atish Patra <atishp@rivosinc.com>
Subject: Re: [PATCH 5/6] tty: Add SBI debug console support to HVC SBI driver
Date: Tue, 10 Oct 2023 19:12:42 +0200 [thread overview]
Message-ID: <2023101045-hazard-popcorn-7d19@gregkh> (raw)
In-Reply-To: <20231010170503.657189-6-apatel@ventanamicro.com>
On Tue, Oct 10, 2023 at 10:35:02PM +0530, Anup Patel wrote:
> --- a/drivers/tty/hvc/hvc_riscv_sbi.c
> +++ b/drivers/tty/hvc/hvc_riscv_sbi.c
> @@ -15,6 +15,7 @@
>
> #include "hvc_console.h"
>
> +#ifdef CONFIG_RISCV_SBI_V01
Please no #ifdef in a .c file, that's not a good style for Linux code at
all.
And what if you want to build the driver for both options here? What
will happen?
> +static int hvc_sbi_dbcn_tty_put(uint32_t vtermno, const char *buf, int count)
> {
> - return PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_ops, 16));
> + phys_addr_t pa;
> + struct sbiret ret;
> +
> + if (is_vmalloc_addr(buf))
> + pa = page_to_phys(vmalloc_to_page(buf)) + offset_in_page(buf);
> + else
> + pa = __pa(buf);
> +
> + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE,
> +#ifdef CONFIG_32BIT
> + count, pa, (u64)pa >> 32,
> +#else
> + count, pa, 0,
> +#endif
This is not how to do an api, sorry, again, please no #ifdef if you want
to support this code for the next 20+ years.
thanks,
gre gk-h
WARNING: multiple messages have this Message-ID (diff)
From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: Anup Patel <apatel@ventanamicro.com>
Cc: linux-serial@vger.kernel.org, kvm@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org,
Atish Patra <atishp@atishpatra.org>,
Atish Patra <atishp@rivosinc.com>,
linux-kernel@vger.kernel.org, Conor Dooley <conor@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
kvm-riscv@lists.infradead.org,
Paul Walmsley <paul.walmsley@sifive.com>,
Paolo Bonzini <pbonzini@redhat.com>,
linux-riscv@lists.infradead.org,
Jiri Slaby <jirislaby@kernel.org>,
Andrew Jones <ajones@ventanamicro.com>
Subject: Re: [PATCH 5/6] tty: Add SBI debug console support to HVC SBI driver
Date: Tue, 10 Oct 2023 19:12:42 +0200 [thread overview]
Message-ID: <2023101045-hazard-popcorn-7d19@gregkh> (raw)
In-Reply-To: <20231010170503.657189-6-apatel@ventanamicro.com>
On Tue, Oct 10, 2023 at 10:35:02PM +0530, Anup Patel wrote:
> --- a/drivers/tty/hvc/hvc_riscv_sbi.c
> +++ b/drivers/tty/hvc/hvc_riscv_sbi.c
> @@ -15,6 +15,7 @@
>
> #include "hvc_console.h"
>
> +#ifdef CONFIG_RISCV_SBI_V01
Please no #ifdef in a .c file, that's not a good style for Linux code at
all.
And what if you want to build the driver for both options here? What
will happen?
> +static int hvc_sbi_dbcn_tty_put(uint32_t vtermno, const char *buf, int count)
> {
> - return PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_ops, 16));
> + phys_addr_t pa;
> + struct sbiret ret;
> +
> + if (is_vmalloc_addr(buf))
> + pa = page_to_phys(vmalloc_to_page(buf)) + offset_in_page(buf);
> + else
> + pa = __pa(buf);
> +
> + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE,
> +#ifdef CONFIG_32BIT
> + count, pa, (u64)pa >> 32,
> +#else
> + count, pa, 0,
> +#endif
This is not how to do an api, sorry, again, please no #ifdef if you want
to support this code for the next 20+ years.
thanks,
gre gk-h
next prev parent reply other threads:[~2023-10-10 17:12 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-10 17:04 [PATCH 0/6] RISC-V SBI debug console extension support Anup Patel
2023-10-10 17:04 ` Anup Patel
2023-10-10 17:04 ` Anup Patel
2023-10-10 17:04 ` Anup Patel
2023-10-10 17:04 ` [PATCH 1/6] RISC-V: Add defines for SBI debug console extension Anup Patel
2023-10-10 17:04 ` Anup Patel
2023-10-10 17:04 ` Anup Patel
2023-10-10 17:04 ` Anup Patel
2023-10-10 17:04 ` [PATCH 2/6] RISC-V: KVM: Change the SBI specification version to v2.0 Anup Patel
2023-10-10 17:04 ` Anup Patel
2023-10-10 17:04 ` Anup Patel
2023-10-10 17:04 ` Anup Patel
2023-10-10 17:13 ` Greg Kroah-Hartman
2023-10-10 17:13 ` Greg Kroah-Hartman
2023-10-10 17:13 ` Greg Kroah-Hartman
2023-10-10 17:13 ` Greg Kroah-Hartman
2023-10-11 6:19 ` Anup Patel
2023-10-11 6:19 ` Anup Patel
2023-10-11 6:19 ` Anup Patel
2023-10-11 6:19 ` Anup Patel
2023-10-11 7:27 ` Greg Kroah-Hartman
2023-10-11 7:27 ` Greg Kroah-Hartman
2023-10-11 7:27 ` Greg Kroah-Hartman
2023-10-11 7:27 ` Greg Kroah-Hartman
2023-10-11 11:02 ` Anup Patel
2023-10-11 11:02 ` Anup Patel
2023-10-11 11:02 ` Anup Patel
2023-10-11 11:02 ` Anup Patel
2023-10-11 15:26 ` Greg Kroah-Hartman
2023-10-11 15:26 ` Greg Kroah-Hartman
2023-10-11 15:26 ` Greg Kroah-Hartman
2023-10-11 15:26 ` Greg Kroah-Hartman
2023-10-11 15:38 ` Anup Patel
2023-10-11 15:38 ` Anup Patel
2023-10-11 15:38 ` Anup Patel
2023-10-11 15:38 ` Anup Patel
2023-10-10 17:05 ` [PATCH 3/6] RISC-V: KVM: Forward SBI DBCN extension to user-space Anup Patel
2023-10-10 17:05 ` Anup Patel
2023-10-10 17:05 ` Anup Patel
2023-10-10 17:05 ` Anup Patel
2023-10-10 17:15 ` Greg Kroah-Hartman
2023-10-10 17:15 ` Greg Kroah-Hartman
2023-10-10 17:15 ` Greg Kroah-Hartman
2023-10-10 17:15 ` Greg Kroah-Hartman
2023-10-11 6:32 ` Anup Patel
2023-10-11 6:32 ` Anup Patel
2023-10-11 6:32 ` Anup Patel
2023-10-11 6:32 ` Anup Patel
2023-10-11 7:25 ` Greg Kroah-Hartman
2023-10-11 7:25 ` Greg Kroah-Hartman
2023-10-11 7:25 ` Greg Kroah-Hartman
2023-10-11 7:25 ` Greg Kroah-Hartman
2023-10-11 10:54 ` Anup Patel
2023-10-11 10:54 ` Anup Patel
2023-10-11 10:54 ` Anup Patel
2023-10-11 10:54 ` Anup Patel
2023-10-10 17:05 ` [PATCH 4/6] tty/serial: Add RISC-V SBI debug console based earlycon Anup Patel
2023-10-10 17:05 ` Anup Patel
2023-10-10 17:05 ` Anup Patel
2023-10-10 17:05 ` Anup Patel
2023-10-10 17:16 ` Greg Kroah-Hartman
2023-10-10 17:16 ` Greg Kroah-Hartman
2023-10-10 17:16 ` Greg Kroah-Hartman
2023-10-10 17:16 ` Greg Kroah-Hartman
2023-10-11 5:52 ` Anup Patel
2023-10-11 5:52 ` Anup Patel
2023-10-11 5:52 ` Anup Patel
2023-10-11 5:52 ` Anup Patel
2023-10-10 17:05 ` [PATCH 5/6] tty: Add SBI debug console support to HVC SBI driver Anup Patel
2023-10-10 17:05 ` Anup Patel
2023-10-10 17:05 ` Anup Patel
2023-10-10 17:05 ` Anup Patel
2023-10-10 17:12 ` Greg Kroah-Hartman [this message]
2023-10-10 17:12 ` Greg Kroah-Hartman
2023-10-10 17:12 ` Greg Kroah-Hartman
2023-10-10 17:12 ` Greg Kroah-Hartman
2023-10-11 5:51 ` Anup Patel
2023-10-11 5:51 ` Anup Patel
2023-10-11 5:51 ` Anup Patel
2023-10-11 5:51 ` Anup Patel
2023-10-10 17:05 ` [PATCH 6/6] RISC-V: Enable SBI based earlycon support Anup Patel
2023-10-10 17:05 ` Anup Patel
2023-10-10 17:05 ` Anup Patel
2023-10-10 17:05 ` Anup Patel
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