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From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Frank Rowand <frowand.list@gmail.com>,
	Conor Dooley <conor+dt@kernel.org>
Cc: "Anup Patel" <apatel@ventanamicro.com>,
	devicetree@vger.kernel.org,
	"Saravana Kannan" <saravanak@google.com>,
	"Marc Zyngier" <maz@kernel.org>,
	"Anup Patel" <anup@brainfault.org>,
	"Atish Patra" <atishp@rivosinc.com>,
	linux-kernel@vger.kernel.org, "Björn Töpel" <bjorn@kernel.org>,
	"Atish Patra" <atishp@atishpatra.org>,
	linux-riscv@lists.infradead.org,
	"Andrew Jones" <ajones@ventanamicro.com>
Subject: [PATCH v11 01/14] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs
Date: Mon, 23 Oct 2023 22:57:47 +0530	[thread overview]
Message-ID: <20231023172800.315343-2-apatel@ventanamicro.com> (raw)
In-Reply-To: <20231023172800.315343-1-apatel@ventanamicro.com>

The riscv_of_processor_hartid() used by riscv_of_parent_hartid() fails
for HARTs disabled in the DT. This results in the following warning
thrown by the RISC-V INTC driver for the E-core on SiFive boards:

[    0.000000] riscv-intc: unable to find hart id for /cpus/cpu@0/interrupt-controller

The riscv_of_parent_hartid() is only expected to read the hartid from
the DT so we should directly call of_get_cpu_hwid() instead of calling
riscv_of_processor_hartid().

Fixes: ad635e723e17 ("riscv: cpu: Add 64bit hartid support on RV64")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
---
 arch/riscv/kernel/cpu.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index c17dacb1141c..157ace8b262c 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -125,13 +125,14 @@ int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned lo
  */
 int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
 {
-	int rc;
-
 	for (; node; node = node->parent) {
 		if (of_device_is_compatible(node, "riscv")) {
-			rc = riscv_of_processor_hartid(node, hartid);
-			if (!rc)
-				return 0;
+			*hartid = (unsigned long)of_get_cpu_hwid(node, 0);
+			if (*hartid == ~0UL) {
+				pr_warn("Found CPU without hart ID\n");
+				return -ENODEV;
+			}
+			return 0;
 		}
 	}
 
-- 
2.34.1


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WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Frank Rowand <frowand.list@gmail.com>,
	Conor Dooley <conor+dt@kernel.org>
Cc: "Marc Zyngier" <maz@kernel.org>, "Björn Töpel" <bjorn@kernel.org>,
	"Atish Patra" <atishp@atishpatra.org>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Sunil V L" <sunilvl@ventanamicro.com>,
	"Saravana Kannan" <saravanak@google.com>,
	"Anup Patel" <anup@brainfault.org>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org,
	"Anup Patel" <apatel@ventanamicro.com>,
	"Atish Patra" <atishp@rivosinc.com>
Subject: [PATCH v11 01/14] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs
Date: Mon, 23 Oct 2023 22:57:47 +0530	[thread overview]
Message-ID: <20231023172800.315343-2-apatel@ventanamicro.com> (raw)
In-Reply-To: <20231023172800.315343-1-apatel@ventanamicro.com>

The riscv_of_processor_hartid() used by riscv_of_parent_hartid() fails
for HARTs disabled in the DT. This results in the following warning
thrown by the RISC-V INTC driver for the E-core on SiFive boards:

[    0.000000] riscv-intc: unable to find hart id for /cpus/cpu@0/interrupt-controller

The riscv_of_parent_hartid() is only expected to read the hartid from
the DT so we should directly call of_get_cpu_hwid() instead of calling
riscv_of_processor_hartid().

Fixes: ad635e723e17 ("riscv: cpu: Add 64bit hartid support on RV64")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
---
 arch/riscv/kernel/cpu.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index c17dacb1141c..157ace8b262c 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -125,13 +125,14 @@ int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned lo
  */
 int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
 {
-	int rc;
-
 	for (; node; node = node->parent) {
 		if (of_device_is_compatible(node, "riscv")) {
-			rc = riscv_of_processor_hartid(node, hartid);
-			if (!rc)
-				return 0;
+			*hartid = (unsigned long)of_get_cpu_hwid(node, 0);
+			if (*hartid == ~0UL) {
+				pr_warn("Found CPU without hart ID\n");
+				return -ENODEV;
+			}
+			return 0;
 		}
 	}
 
-- 
2.34.1


  reply	other threads:[~2023-10-23 17:28 UTC|newest]

Thread overview: 94+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-23 17:27 [PATCH v11 00/14] Linux RISC-V AIA Support Anup Patel
2023-10-23 17:27 ` Anup Patel
2023-10-23 17:27 ` Anup Patel [this message]
2023-10-23 17:27   ` [PATCH v11 01/14] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs Anup Patel
2023-10-24 11:55   ` Björn Töpel
2023-10-24 11:55     ` Björn Töpel
2023-10-24 12:07     ` Anup Patel
2023-10-24 12:07       ` Anup Patel
2023-10-23 17:27 ` [PATCH v11 02/14] of: property: Add fw_devlink support for msi-parent Anup Patel
2023-10-23 17:27   ` Anup Patel
2023-10-23 17:27 ` [PATCH v11 03/14] irqchip/sifive-plic: Fix syscore registration for multi-socket systems Anup Patel
2023-10-23 17:27   ` Anup Patel
2023-10-23 17:27 ` [PATCH v11 04/14] irqchip/sifive-plic: Convert PLIC driver into a platform driver Anup Patel
2023-10-23 17:27   ` Anup Patel
2023-10-23 17:27 ` [PATCH v11 05/14] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2023-10-23 17:27   ` Anup Patel
2023-10-24 12:17   ` Andrew Jones
2023-10-24 12:17     ` Andrew Jones
2023-10-23 17:27 ` [PATCH v11 06/14] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2023-10-23 17:27   ` Anup Patel
2023-10-24 12:30   ` Andrew Jones
2023-10-24 12:30     ` Andrew Jones
2023-10-23 17:27 ` [PATCH v11 07/14] irqchip: Add RISC-V incoming MSI controller early driver Anup Patel
2023-10-23 17:27   ` Anup Patel
2023-10-24  9:25   ` Conor Dooley
2023-10-24  9:25     ` Conor Dooley
2023-10-24 12:08     ` Anup Patel
2023-10-24 12:08       ` Anup Patel
2023-10-24 13:05   ` Björn Töpel
2023-10-24 13:05     ` Björn Töpel
2023-10-25  5:08     ` Anup Patel
2023-10-25  5:08       ` Anup Patel
2023-10-25 16:05       ` Björn Töpel
2023-10-25 16:05         ` Björn Töpel
2023-10-25 17:25         ` Anup Patel
2023-10-25 17:25           ` Anup Patel
2023-10-26  8:51           ` Björn Töpel
2023-10-26  8:51             ` Björn Töpel
2023-10-28 18:18             ` Thomas Gleixner
2023-10-28 18:18               ` Thomas Gleixner
2023-10-28 18:34   ` Thomas Gleixner
2023-10-28 18:34     ` Thomas Gleixner
2023-10-23 17:27 ` [PATCH v11 08/14] irqchip/riscv-imsic: Add support for platform MSI irqdomain Anup Patel
2023-10-23 17:27   ` Anup Patel
2023-10-25 19:56   ` Thomas Gleixner
2023-10-25 19:56     ` Thomas Gleixner
2023-10-23 17:27 ` [PATCH v11 09/14] irqchip/riscv-imsic: Add support for PCI " Anup Patel
2023-10-23 17:27   ` Anup Patel
2023-10-24 13:09   ` Björn Töpel
2023-10-24 13:09     ` Björn Töpel
2023-10-25  5:08     ` Anup Patel
2023-10-25  5:08       ` Anup Patel
2023-10-25  8:55       ` Björn Töpel
2023-10-25  8:55         ` Björn Töpel
2023-10-28 18:36         ` Thomas Gleixner
2023-10-28 18:36           ` Thomas Gleixner
2023-10-29 19:53           ` Björn Töpel
2023-10-29 19:53             ` Björn Töpel
2023-10-25 19:59   ` Thomas Gleixner
2023-10-25 19:59     ` Thomas Gleixner
2023-10-23 17:27 ` [PATCH v11 10/14] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2023-10-23 17:27   ` Anup Patel
2023-10-23 17:27 ` [PATCH v11 11/14] irqchip: Add RISC-V advanced PLIC driver for direct-mode Anup Patel
2023-10-23 17:27   ` Anup Patel
2023-10-23 17:27 ` [PATCH v11 12/14] irqchip/riscv-aplic: Add support for MSI-mode Anup Patel
2023-10-23 17:27   ` Anup Patel
2023-10-24  5:31   ` Sunil V L
2023-10-24  5:31     ` Sunil V L
2023-11-02  6:38   ` Ben
2023-11-02  6:38     ` Ben
     [not found]   ` <210e2757.3169.18b8eb4495c.Coremail.figure1802@126.com>
2023-11-02 12:37     ` [PATCH " Anup Patel
2023-11-02 12:37       ` Anup Patel
2023-11-03  9:39       ` Ben
2023-11-03  9:39         ` Ben
2023-11-03 11:04         ` Anup Patel
2023-11-03 11:04           ` Anup Patel
2023-11-04  0:58   ` Ben
2023-11-04  0:58     ` Ben
2023-11-08 14:20     ` Ben
2023-11-08 14:20       ` Ben
2023-11-08 14:43     ` [PATCH " Anup Patel
2023-11-08 14:43       ` Anup Patel
2023-11-08 14:51       ` Ben
2023-11-08 14:51         ` Ben
2023-11-08 14:56         ` Anup Patel
2023-11-08 14:56           ` Anup Patel
2023-11-08 15:32           ` Ben
2023-11-08 15:32             ` Ben
2023-11-14  9:21             ` Anup Patel
2023-11-14  9:21               ` Anup Patel
2023-10-23 17:27 ` [PATCH v11 13/14] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2023-10-23 17:27   ` Anup Patel
2023-10-23 17:28 ` [PATCH v11 14/14] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel
2023-10-23 17:28   ` Anup Patel

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