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From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, kvm@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Cc: Alexandru Elisei <alexandru.elisei@arm.com>,
	Andre Przywara <andre.przywara@arm.com>,
	Chase Conklin <chase.conklin@arm.com>,
	Christoffer Dall <christoffer.dall@arm.com>,
	Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>,
	Darren Hart <darren@os.amperecomputing.com>,
	Jintack Lim <jintack@cs.columbia.edu>,
	Russell King <rmk+kernel@armlinux.org.uk>,
	Miguel Luis <miguel.luis@oracle.com>,
	James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Zenghui Yu <yuzenghui@huawei.com>
Subject: [PATCH v11 06/43] KVM: arm64: nv: Add include containing the VNCR_EL2 offsets
Date: Mon, 20 Nov 2023 13:09:50 +0000	[thread overview]
Message-ID: <20231120131027.854038-7-maz@kernel.org> (raw)
In-Reply-To: <20231120131027.854038-1-maz@kernel.org>

VNCR_EL2 points to a page containing a number of system registers
accessed by a guest hypervisor when ARMv8.4-NV is enabled.

Let's document the offsets in that page, as we are going to use
this layout.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/include/asm/vncr_mapping.h | 102 ++++++++++++++++++++++++++
 1 file changed, 102 insertions(+)
 create mode 100644 arch/arm64/include/asm/vncr_mapping.h

diff --git a/arch/arm64/include/asm/vncr_mapping.h b/arch/arm64/include/asm/vncr_mapping.h
new file mode 100644
index 000000000000..497d37780d15
--- /dev/null
+++ b/arch/arm64/include/asm/vncr_mapping.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * System register offsets in the VNCR page
+ * All offsets are *byte* displacements!
+ */
+
+#ifndef __ARM64_VNCR_MAPPING_H__
+#define __ARM64_VNCR_MAPPING_H__
+
+#define VNCR_VTTBR_EL2          0x020
+#define VNCR_VTCR_EL2           0x040
+#define VNCR_VMPIDR_EL2         0x050
+#define VNCR_CNTVOFF_EL2        0x060
+#define VNCR_HCR_EL2            0x078
+#define VNCR_HSTR_EL2           0x080
+#define VNCR_VPIDR_EL2          0x088
+#define VNCR_TPIDR_EL2          0x090
+#define VNCR_HCRX_EL2           0x0A0
+#define VNCR_VNCR_EL2           0x0B0
+#define VNCR_CPACR_EL1          0x100
+#define VNCR_CONTEXTIDR_EL1     0x108
+#define VNCR_SCTLR_EL1          0x110
+#define VNCR_ACTLR_EL1          0x118
+#define VNCR_TCR_EL1            0x120
+#define VNCR_AFSR0_EL1          0x128
+#define VNCR_AFSR1_EL1          0x130
+#define VNCR_ESR_EL1            0x138
+#define VNCR_MAIR_EL1           0x140
+#define VNCR_AMAIR_EL1          0x148
+#define VNCR_MDSCR_EL1          0x158
+#define VNCR_SPSR_EL1           0x160
+#define VNCR_CNTV_CVAL_EL0      0x168
+#define VNCR_CNTV_CTL_EL0       0x170
+#define VNCR_CNTP_CVAL_EL0      0x178
+#define VNCR_CNTP_CTL_EL0       0x180
+#define VNCR_SCXTNUM_EL1        0x188
+#define VNCR_TFSR_EL1		0x190
+#define VNCR_HFGRTR_EL2		0x1B8
+#define VNCR_HFGWTR_EL2		0x1C0
+#define VNCR_HFGITR_EL2		0x1C8
+#define VNCR_HDFGRTR_EL2	0x1D0
+#define VNCR_HDFGWTR_EL2	0x1D8
+#define VNCR_ZCR_EL1            0x1E0
+#define VNCR_TTBR0_EL1          0x200
+#define VNCR_TTBR1_EL1          0x210
+#define VNCR_FAR_EL1            0x220
+#define VNCR_ELR_EL1            0x230
+#define VNCR_SP_EL1             0x240
+#define VNCR_VBAR_EL1           0x250
+#define VNCR_TCR2_EL1		0x270
+#define VNCR_PIRE0_EL1		0x290
+#define VNCR_PIRE0_EL2		0x298
+#define VNCR_PIR_EL1		0x2A0
+#define VNCR_ICH_LR0_EL2        0x400
+#define VNCR_ICH_LR1_EL2        0x408
+#define VNCR_ICH_LR2_EL2        0x410
+#define VNCR_ICH_LR3_EL2        0x418
+#define VNCR_ICH_LR4_EL2        0x420
+#define VNCR_ICH_LR5_EL2        0x428
+#define VNCR_ICH_LR6_EL2        0x430
+#define VNCR_ICH_LR7_EL2        0x438
+#define VNCR_ICH_LR8_EL2        0x440
+#define VNCR_ICH_LR9_EL2        0x448
+#define VNCR_ICH_LR10_EL2       0x450
+#define VNCR_ICH_LR11_EL2       0x458
+#define VNCR_ICH_LR12_EL2       0x460
+#define VNCR_ICH_LR13_EL2       0x468
+#define VNCR_ICH_LR14_EL2       0x470
+#define VNCR_ICH_LR15_EL2       0x478
+#define VNCR_ICH_AP0R0_EL2      0x480
+#define VNCR_ICH_AP0R1_EL2      0x488
+#define VNCR_ICH_AP0R2_EL2      0x490
+#define VNCR_ICH_AP0R3_EL2      0x498
+#define VNCR_ICH_AP1R0_EL2      0x4A0
+#define VNCR_ICH_AP1R1_EL2      0x4A8
+#define VNCR_ICH_AP1R2_EL2      0x4B0
+#define VNCR_ICH_AP1R3_EL2      0x4B8
+#define VNCR_ICH_HCR_EL2        0x4C0
+#define VNCR_ICH_VMCR_EL2       0x4C8
+#define VNCR_VDISR_EL2          0x500
+#define VNCR_PMBLIMITR_EL1      0x800
+#define VNCR_PMBPTR_EL1         0x810
+#define VNCR_PMBSR_EL1          0x820
+#define VNCR_PMSCR_EL1          0x828
+#define VNCR_PMSEVFR_EL1        0x830
+#define VNCR_PMSICR_EL1         0x838
+#define VNCR_PMSIRR_EL1         0x840
+#define VNCR_PMSLATFR_EL1       0x848
+#define VNCR_TRFCR_EL1          0x880
+#define VNCR_MPAM1_EL1          0x900
+#define VNCR_MPAMHCR_EL2        0x930
+#define VNCR_MPAMVPMV_EL2       0x938
+#define VNCR_MPAMVPM0_EL2       0x940
+#define VNCR_MPAMVPM1_EL2       0x948
+#define VNCR_MPAMVPM2_EL2       0x950
+#define VNCR_MPAMVPM3_EL2       0x958
+#define VNCR_MPAMVPM4_EL2       0x960
+#define VNCR_MPAMVPM5_EL2       0x968
+#define VNCR_MPAMVPM6_EL2       0x970
+#define VNCR_MPAMVPM7_EL2       0x978
+
+#endif /* __ARM64_VNCR_MAPPING_H__ */
-- 
2.39.2


WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, kvm@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Cc: Alexandru Elisei <alexandru.elisei@arm.com>,
	Andre Przywara <andre.przywara@arm.com>,
	Chase Conklin <chase.conklin@arm.com>,
	Christoffer Dall <christoffer.dall@arm.com>,
	Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>,
	Darren Hart <darren@os.amperecomputing.com>,
	Jintack Lim <jintack@cs.columbia.edu>,
	Russell King <rmk+kernel@armlinux.org.uk>,
	Miguel Luis <miguel.luis@oracle.com>,
	James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Zenghui Yu <yuzenghui@huawei.com>
Subject: [PATCH v11 06/43] KVM: arm64: nv: Add include containing the VNCR_EL2 offsets
Date: Mon, 20 Nov 2023 13:09:50 +0000	[thread overview]
Message-ID: <20231120131027.854038-7-maz@kernel.org> (raw)
In-Reply-To: <20231120131027.854038-1-maz@kernel.org>

VNCR_EL2 points to a page containing a number of system registers
accessed by a guest hypervisor when ARMv8.4-NV is enabled.

Let's document the offsets in that page, as we are going to use
this layout.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/include/asm/vncr_mapping.h | 102 ++++++++++++++++++++++++++
 1 file changed, 102 insertions(+)
 create mode 100644 arch/arm64/include/asm/vncr_mapping.h

diff --git a/arch/arm64/include/asm/vncr_mapping.h b/arch/arm64/include/asm/vncr_mapping.h
new file mode 100644
index 000000000000..497d37780d15
--- /dev/null
+++ b/arch/arm64/include/asm/vncr_mapping.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * System register offsets in the VNCR page
+ * All offsets are *byte* displacements!
+ */
+
+#ifndef __ARM64_VNCR_MAPPING_H__
+#define __ARM64_VNCR_MAPPING_H__
+
+#define VNCR_VTTBR_EL2          0x020
+#define VNCR_VTCR_EL2           0x040
+#define VNCR_VMPIDR_EL2         0x050
+#define VNCR_CNTVOFF_EL2        0x060
+#define VNCR_HCR_EL2            0x078
+#define VNCR_HSTR_EL2           0x080
+#define VNCR_VPIDR_EL2          0x088
+#define VNCR_TPIDR_EL2          0x090
+#define VNCR_HCRX_EL2           0x0A0
+#define VNCR_VNCR_EL2           0x0B0
+#define VNCR_CPACR_EL1          0x100
+#define VNCR_CONTEXTIDR_EL1     0x108
+#define VNCR_SCTLR_EL1          0x110
+#define VNCR_ACTLR_EL1          0x118
+#define VNCR_TCR_EL1            0x120
+#define VNCR_AFSR0_EL1          0x128
+#define VNCR_AFSR1_EL1          0x130
+#define VNCR_ESR_EL1            0x138
+#define VNCR_MAIR_EL1           0x140
+#define VNCR_AMAIR_EL1          0x148
+#define VNCR_MDSCR_EL1          0x158
+#define VNCR_SPSR_EL1           0x160
+#define VNCR_CNTV_CVAL_EL0      0x168
+#define VNCR_CNTV_CTL_EL0       0x170
+#define VNCR_CNTP_CVAL_EL0      0x178
+#define VNCR_CNTP_CTL_EL0       0x180
+#define VNCR_SCXTNUM_EL1        0x188
+#define VNCR_TFSR_EL1		0x190
+#define VNCR_HFGRTR_EL2		0x1B8
+#define VNCR_HFGWTR_EL2		0x1C0
+#define VNCR_HFGITR_EL2		0x1C8
+#define VNCR_HDFGRTR_EL2	0x1D0
+#define VNCR_HDFGWTR_EL2	0x1D8
+#define VNCR_ZCR_EL1            0x1E0
+#define VNCR_TTBR0_EL1          0x200
+#define VNCR_TTBR1_EL1          0x210
+#define VNCR_FAR_EL1            0x220
+#define VNCR_ELR_EL1            0x230
+#define VNCR_SP_EL1             0x240
+#define VNCR_VBAR_EL1           0x250
+#define VNCR_TCR2_EL1		0x270
+#define VNCR_PIRE0_EL1		0x290
+#define VNCR_PIRE0_EL2		0x298
+#define VNCR_PIR_EL1		0x2A0
+#define VNCR_ICH_LR0_EL2        0x400
+#define VNCR_ICH_LR1_EL2        0x408
+#define VNCR_ICH_LR2_EL2        0x410
+#define VNCR_ICH_LR3_EL2        0x418
+#define VNCR_ICH_LR4_EL2        0x420
+#define VNCR_ICH_LR5_EL2        0x428
+#define VNCR_ICH_LR6_EL2        0x430
+#define VNCR_ICH_LR7_EL2        0x438
+#define VNCR_ICH_LR8_EL2        0x440
+#define VNCR_ICH_LR9_EL2        0x448
+#define VNCR_ICH_LR10_EL2       0x450
+#define VNCR_ICH_LR11_EL2       0x458
+#define VNCR_ICH_LR12_EL2       0x460
+#define VNCR_ICH_LR13_EL2       0x468
+#define VNCR_ICH_LR14_EL2       0x470
+#define VNCR_ICH_LR15_EL2       0x478
+#define VNCR_ICH_AP0R0_EL2      0x480
+#define VNCR_ICH_AP0R1_EL2      0x488
+#define VNCR_ICH_AP0R2_EL2      0x490
+#define VNCR_ICH_AP0R3_EL2      0x498
+#define VNCR_ICH_AP1R0_EL2      0x4A0
+#define VNCR_ICH_AP1R1_EL2      0x4A8
+#define VNCR_ICH_AP1R2_EL2      0x4B0
+#define VNCR_ICH_AP1R3_EL2      0x4B8
+#define VNCR_ICH_HCR_EL2        0x4C0
+#define VNCR_ICH_VMCR_EL2       0x4C8
+#define VNCR_VDISR_EL2          0x500
+#define VNCR_PMBLIMITR_EL1      0x800
+#define VNCR_PMBPTR_EL1         0x810
+#define VNCR_PMBSR_EL1          0x820
+#define VNCR_PMSCR_EL1          0x828
+#define VNCR_PMSEVFR_EL1        0x830
+#define VNCR_PMSICR_EL1         0x838
+#define VNCR_PMSIRR_EL1         0x840
+#define VNCR_PMSLATFR_EL1       0x848
+#define VNCR_TRFCR_EL1          0x880
+#define VNCR_MPAM1_EL1          0x900
+#define VNCR_MPAMHCR_EL2        0x930
+#define VNCR_MPAMVPMV_EL2       0x938
+#define VNCR_MPAMVPM0_EL2       0x940
+#define VNCR_MPAMVPM1_EL2       0x948
+#define VNCR_MPAMVPM2_EL2       0x950
+#define VNCR_MPAMVPM3_EL2       0x958
+#define VNCR_MPAMVPM4_EL2       0x960
+#define VNCR_MPAMVPM5_EL2       0x968
+#define VNCR_MPAMVPM6_EL2       0x970
+#define VNCR_MPAMVPM7_EL2       0x978
+
+#endif /* __ARM64_VNCR_MAPPING_H__ */
-- 
2.39.2


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2023-11-20 13:10 UTC|newest]

Thread overview: 158+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-20 13:09 [PATCH v11 00/43] KVM: arm64: Nested Virtualization support (FEAT_NV2 only) Marc Zyngier
2023-11-20 13:09 ` Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 01/43] arm64: cpufeatures: Restrict NV support to FEAT_NV2 Marc Zyngier
2023-11-20 13:09   ` Marc Zyngier
2023-11-21  9:07   ` Ganapatrao Kulkarni
2023-11-21  9:07     ` Ganapatrao Kulkarni
2023-11-21  9:27     ` Marc Zyngier
2023-11-21  9:27       ` Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 02/43] KVM: arm64: nv: Hoist vcpu_has_nv() into is_hyp_ctxt() Marc Zyngier
2023-11-20 13:09   ` Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 03/43] KVM: arm64: nv: Compute NV view of idregs as a one-off Marc Zyngier
2023-11-20 13:09   ` Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 04/43] KVM: arm64: nv: Drop EL12 register traps that are redirected to VNCR Marc Zyngier
2023-11-20 13:09   ` Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 05/43] KVM: arm64: nv: Add non-VHE-EL2->EL1 translation helpers Marc Zyngier
2023-11-20 13:09   ` Marc Zyngier
2023-11-20 13:09 ` Marc Zyngier [this message]
2023-11-20 13:09   ` [PATCH v11 06/43] KVM: arm64: nv: Add include containing the VNCR_EL2 offsets Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 07/43] KVM: arm64: Introduce a bad_trap() primitive for unexpected trap handling Marc Zyngier
2023-11-20 13:09   ` Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 08/43] KVM: arm64: nv: Add EL2_REG_VNCR()/EL2_REG_REDIR() sysreg helpers Marc Zyngier
2023-11-20 13:09   ` Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 09/43] KVM: arm64: nv: Map VNCR-capable registers to a separate page Marc Zyngier
2023-11-20 13:09   ` Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 10/43] KVM: arm64: nv: Handle virtual EL2 registers in vcpu_read/write_sys_reg() Marc Zyngier
2023-11-20 13:09   ` Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 11/43] KVM: arm64: nv: Handle HCR_EL2.E2H specially Marc Zyngier
2023-11-20 13:09   ` Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 12/43] KVM: arm64: nv: Handle CNTHCTL_EL2 specially Marc Zyngier
2023-11-20 13:09   ` Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 13/43] KVM: arm64: nv: Save/Restore vEL2 sysregs Marc Zyngier
2023-11-20 13:09   ` Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 14/43] KVM: arm64: nv: Respect virtual HCR_EL2.TWX setting Marc Zyngier
2023-11-20 13:09   ` Marc Zyngier
2023-11-20 13:09 ` [PATCH v11 15/43] KVM: arm64: nv: Respect virtual CPTR_EL2.{TFP,FPEN} settings Marc Zyngier
2023-11-20 13:09   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 16/43] KVM: arm64: nv: Configure HCR_EL2 for FEAT_NV2 Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 17/43] KVM: arm64: nv: Support multiple nested Stage-2 mmu structures Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2024-01-23  9:55   ` Ganapatrao Kulkarni
2024-01-23  9:55     ` Ganapatrao Kulkarni
2024-01-23 14:26     ` Marc Zyngier
2024-01-23 14:26       ` Marc Zyngier
2024-01-25  8:14       ` Ganapatrao Kulkarni
2024-01-25  8:14         ` Ganapatrao Kulkarni
2024-01-25  8:58         ` Marc Zyngier
2024-01-25  8:58           ` Marc Zyngier
2024-01-31  9:39           ` Ganapatrao Kulkarni
2024-01-31  9:39             ` Ganapatrao Kulkarni
2024-01-31 13:50             ` Marc Zyngier
2024-01-31 13:50               ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 18/43] KVM: arm64: nv: Implement nested Stage-2 page table walk logic Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 19/43] KVM: arm64: nv: Handle shadow stage 2 page faults Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2024-01-17 14:53   ` Joey Gouly
2024-01-17 14:53     ` Joey Gouly
2024-01-17 15:53     ` Marc Zyngier
2024-01-17 15:53       ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 20/43] KVM: arm64: nv: Restrict S2 RD/WR permissions to match the guest's Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 21/43] KVM: arm64: nv: Unmap/flush shadow stage 2 page tables Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 22/43] KVM: arm64: nv: Set a handler for the system instruction traps Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 23/43] KVM: arm64: nv: Trap and emulate AT instructions from virtual EL2 Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 24/43] KVM: arm64: nv: Trap and emulate TLBI " Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 25/43] KVM: arm64: nv: Hide RAS from nested guests Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 26/43] KVM: arm64: nv: Add handling of EL2-specific timer registers Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 27/43] KVM: arm64: nv: Sync nested timer state with FEAT_NV2 Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 28/43] KVM: arm64: nv: Publish emulated timer interrupt state in the in-memory state Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 29/43] KVM: arm64: nv: Load timer before the GIC Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 30/43] KVM: arm64: nv: Nested GICv3 Support Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 31/43] KVM: arm64: nv: Don't block in WFI from nested state Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 32/43] KVM: arm64: nv: vgic: Allow userland to set VGIC maintenance IRQ Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 33/43] KVM: arm64: nv: Fold GICv3 host trapping requirements into guest setup Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 34/43] KVM: arm64: nv: Deal with broken VGIC on maintenance interrupt delivery Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 35/43] KVM: arm64: nv: Add handling of FEAT_TTL TLB invalidation Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 36/43] KVM: arm64: nv: Invalidate TLBs based on shadow S2 TTL-like information Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 37/43] KVM: arm64: nv: Tag shadow S2 entries with nested level Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 38/43] KVM: arm64: nv: Allocate VNCR page when required Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 39/43] KVM: arm64: nv: Fast-track 'InHost' exception returns Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 40/43] KVM: arm64: nv: Fast-track EL1 TLBIs for VHE guests Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 41/43] KVM: arm64: nv: Use FEAT_ECV to trap access to EL0 timers Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 42/43] KVM: arm64: nv: Accelerate EL0 timer read accesses when FEAT_ECV is on Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-20 13:10 ` [PATCH v11 43/43] KVM: arm64: nv: Allow userspace to request KVM_ARM_VCPU_NESTED_VIRT Marc Zyngier
2023-11-20 13:10   ` Marc Zyngier
2023-11-21  8:51 ` [PATCH v11 00/43] KVM: arm64: Nested Virtualization support (FEAT_NV2 only) Ganapatrao Kulkarni
2023-11-21  8:51   ` Ganapatrao Kulkarni
2023-11-21  9:08   ` Marc Zyngier
2023-11-21  9:08     ` Marc Zyngier
2023-11-21  9:26     ` Ganapatrao Kulkarni
2023-11-21  9:26       ` Ganapatrao Kulkarni
2023-11-21  9:41       ` Marc Zyngier
2023-11-21  9:41         ` Marc Zyngier
2023-11-22 11:10         ` Ganapatrao Kulkarni
2023-11-22 11:10           ` Ganapatrao Kulkarni
2023-11-22 11:39           ` Marc Zyngier
2023-11-22 11:39             ` Marc Zyngier
2023-11-21 16:49 ` Miguel Luis
2023-11-21 16:49   ` Miguel Luis
2023-11-21 19:02   ` Marc Zyngier
2023-11-21 19:02     ` Marc Zyngier
2023-11-23 16:21     ` Miguel Luis
2023-11-23 16:21       ` Miguel Luis
2023-11-23 16:44       ` Marc Zyngier
2023-11-23 16:44         ` Marc Zyngier
2023-11-24  9:50         ` Ganapatrao Kulkarni
2023-11-24  9:50           ` Ganapatrao Kulkarni
2023-11-24 10:19           ` Marc Zyngier
2023-11-24 10:19             ` Marc Zyngier
2023-11-24 12:34             ` Ganapatrao Kulkarni
2023-11-24 12:34               ` Ganapatrao Kulkarni
2023-11-24 12:51               ` Marc Zyngier
2023-11-24 12:51                 ` Marc Zyngier
2023-11-24 13:22                 ` Ganapatrao Kulkarni
2023-11-24 13:22                   ` Ganapatrao Kulkarni
2023-11-24 14:32                   ` Marc Zyngier
2023-11-24 14:32                     ` Marc Zyngier
2023-11-27  7:26                     ` Ganapatrao Kulkarni
2023-11-27  7:26                       ` Ganapatrao Kulkarni
2023-11-27  9:22                       ` Marc Zyngier
2023-11-27  9:22                         ` Marc Zyngier
2023-11-27 10:59                         ` Ganapatrao Kulkarni
2023-11-27 10:59                           ` Ganapatrao Kulkarni
2023-11-27 11:45                           ` Marc Zyngier
2023-11-27 11:45                             ` Marc Zyngier
2023-11-27 12:18                             ` Ganapatrao Kulkarni
2023-11-27 12:18                               ` Ganapatrao Kulkarni
2023-11-27 13:57                               ` Marc Zyngier
2023-11-27 13:57                                 ` Marc Zyngier
2023-12-18 12:39 ` Marc Zyngier
2023-12-18 12:39   ` Marc Zyngier
2023-12-18 19:51   ` Oliver Upton
2023-12-18 19:51     ` Oliver Upton
2023-12-19 10:32 ` (subset) " Marc Zyngier
2023-12-19 10:32   ` Marc Zyngier

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