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From: "David E. Box" <david.e.box@linux.intel.com>
To: linux-kernel@vger.kernel.org,
	platform-driver-x86@vger.kernel.org,
	ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com
Subject: [PATCH V6 03/20] platform/x86/intel/vsec: Move structures to header
Date: Wed, 29 Nov 2023 14:21:15 -0800	[thread overview]
Message-ID: <20231129222132.2331261-4-david.e.box@linux.intel.com> (raw)
In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com>

In preparation for exporting an API to register Intel Vendor Specific
Extended Capabilities (VSEC) from other drivers, move needed structures to
the header file.

Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
---
V6 - No change

V5 - No change

V4 - No change

V3 - No change

V2 - New patch splitting previous PATCH 1

 drivers/platform/x86/intel/vsec.c | 35 ------------------------------
 drivers/platform/x86/intel/vsec.h | 36 +++++++++++++++++++++++++++++++
 2 files changed, 36 insertions(+), 35 deletions(-)

diff --git a/drivers/platform/x86/intel/vsec.c b/drivers/platform/x86/intel/vsec.c
index 340562ae2041..c83e2c549fc7 100644
--- a/drivers/platform/x86/intel/vsec.c
+++ b/drivers/platform/x86/intel/vsec.c
@@ -24,13 +24,6 @@
 
 #include "vsec.h"
 
-/* Intel DVSEC offsets */
-#define INTEL_DVSEC_ENTRIES		0xA
-#define INTEL_DVSEC_SIZE		0xB
-#define INTEL_DVSEC_TABLE		0xC
-#define INTEL_DVSEC_TABLE_BAR(x)	((x) & GENMASK(2, 0))
-#define INTEL_DVSEC_TABLE_OFFSET(x)	((x) & GENMASK(31, 3))
-#define TABLE_OFFSET_SHIFT		3
 #define PMT_XA_START			0
 #define PMT_XA_MAX			INT_MAX
 #define PMT_XA_LIMIT			XA_LIMIT(PMT_XA_START, PMT_XA_MAX)
@@ -39,34 +32,6 @@ static DEFINE_IDA(intel_vsec_ida);
 static DEFINE_IDA(intel_vsec_sdsi_ida);
 static DEFINE_XARRAY_ALLOC(auxdev_array);
 
-/**
- * struct intel_vsec_header - Common fields of Intel VSEC and DVSEC registers.
- * @rev:         Revision ID of the VSEC/DVSEC register space
- * @length:      Length of the VSEC/DVSEC register space
- * @id:          ID of the feature
- * @num_entries: Number of instances of the feature
- * @entry_size:  Size of the discovery table for each feature
- * @tbir:        BAR containing the discovery tables
- * @offset:      BAR offset of start of the first discovery table
- */
-struct intel_vsec_header {
-	u8	rev;
-	u16	length;
-	u16	id;
-	u8	num_entries;
-	u8	entry_size;
-	u8	tbir;
-	u32	offset;
-};
-
-enum intel_vsec_id {
-	VSEC_ID_TELEMETRY	= 2,
-	VSEC_ID_WATCHER		= 3,
-	VSEC_ID_CRASHLOG	= 4,
-	VSEC_ID_SDSI		= 65,
-	VSEC_ID_TPMI		= 66,
-};
-
 static const char *intel_vsec_name(enum intel_vsec_id id)
 {
 	switch (id) {
diff --git a/drivers/platform/x86/intel/vsec.h b/drivers/platform/x86/intel/vsec.h
index 0a6201b4a0e9..c242c07ea69c 100644
--- a/drivers/platform/x86/intel/vsec.h
+++ b/drivers/platform/x86/intel/vsec.h
@@ -11,9 +11,45 @@
 #define VSEC_CAP_SDSI		BIT(3)
 #define VSEC_CAP_TPMI		BIT(4)
 
+/* Intel DVSEC offsets */
+#define INTEL_DVSEC_ENTRIES		0xA
+#define INTEL_DVSEC_SIZE		0xB
+#define INTEL_DVSEC_TABLE		0xC
+#define INTEL_DVSEC_TABLE_BAR(x)	((x) & GENMASK(2, 0))
+#define INTEL_DVSEC_TABLE_OFFSET(x)	((x) & GENMASK(31, 3))
+#define TABLE_OFFSET_SHIFT		3
+
 struct pci_dev;
 struct resource;
 
+enum intel_vsec_id {
+	VSEC_ID_TELEMETRY	= 2,
+	VSEC_ID_WATCHER		= 3,
+	VSEC_ID_CRASHLOG	= 4,
+	VSEC_ID_SDSI		= 65,
+	VSEC_ID_TPMI		= 66,
+};
+
+/**
+ * struct intel_vsec_header - Common fields of Intel VSEC and DVSEC registers.
+ * @rev:         Revision ID of the VSEC/DVSEC register space
+ * @length:      Length of the VSEC/DVSEC register space
+ * @id:          ID of the feature
+ * @num_entries: Number of instances of the feature
+ * @entry_size:  Size of the discovery table for each feature
+ * @tbir:        BAR containing the discovery tables
+ * @offset:      BAR offset of start of the first discovery table
+ */
+struct intel_vsec_header {
+	u8	rev;
+	u16	length;
+	u16	id;
+	u8	num_entries;
+	u8	entry_size;
+	u8	tbir;
+	u32	offset;
+};
+
 enum intel_vsec_quirks {
 	/* Watcher feature not supported */
 	VSEC_QUIRK_NO_WATCHER	= BIT(0),
-- 
2.34.1


  parent reply	other threads:[~2023-11-29 22:21 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-29 22:21 [PATCH V6 00/20] intel_pmc: Add telemetry API to read counters David E. Box
2023-11-29 22:21 ` [PATCH V6 01/20] platform/x86/intel/vsec: Fix xa_alloc memory leak David E. Box
2023-11-30 11:02   ` Ilpo Järvinen
2023-12-04 13:51     ` Hans de Goede
2023-12-04 19:57       ` David E. Box
2023-12-04 20:13         ` Hans de Goede
2023-11-29 22:21 ` [PATCH V6 02/20] platform/x86/intel/vsec: Remove unnecessary return David E. Box
2023-11-30 11:03   ` Ilpo Järvinen
2023-11-29 22:21 ` David E. Box [this message]
2023-11-29 22:21 ` [PATCH V6 04/20] platform/x86/intel/vsec: remove platform_info from vsec device structure David E. Box
2023-11-29 22:21 ` [PATCH V6 05/20] platform/x86/intel/vsec: Use cleanup.h David E. Box
2023-11-29 22:21 ` [PATCH V6 06/20] platform/x86/intel/vsec: Assign auxdev parent by argument David E. Box
2023-11-29 22:21 ` [PATCH V6 07/20] platform/x86/intel/vsec: Add intel_vsec_register David E. Box
2023-11-30 11:23   ` Ilpo Järvinen
2023-11-29 22:21 ` [PATCH V6 08/20] platform/x86/intel/vsec: Add base address field David E. Box
2023-11-29 22:21 ` [PATCH V6 09/20] platform/x86/intel/pmt: Add header to struct intel_pmt_entry David E. Box
2023-11-29 22:21 ` [PATCH V6 10/20] platform/x86/intel/pmt: telemetry: Export API to read telemetry David E. Box
2023-11-29 22:21 ` [PATCH V6 11/20] platform/x86:intel/pmc: Call pmc_get_low_power_modes from platform init David E. Box
2023-11-29 22:21 ` [PATCH V6 12/20] platform/x86/intel/pmc: Allow pmc_core_ssram_init to fail David E. Box
2023-11-29 22:21 ` [PATCH V6 13/20] platform/x86/intel/pmc: Cleanup SSRAM discovery David E. Box
2023-11-29 22:21 ` [PATCH V6 14/20] platform/x86/intel/pmc/mtl: Use return value from pmc_core_ssram_init() David E. Box
2023-11-29 22:21 ` [PATCH V6 15/20] platform/x86/intel/pmc: Find and register PMC telemetry entries David E. Box
2023-11-29 22:21 ` [PATCH V6 16/20] platform/x86/intel/pmc: Display LPM requirements for multiple PMCs David E. Box
2023-11-29 22:21 ` [PATCH V6 17/20] platform/x86/intel/pmc: Retrieve LPM information using Intel PMT David E. Box
2023-11-29 22:21 ` [PATCH V6 18/20] platform/x86/intel/pmc: Read low power mode requirements for MTL-M and MTL-P David E. Box
2023-11-29 22:21 ` [PATCH V6 19/20] platform/x86/intel/pmc: Add debug attribute for Die C6 counter David E. Box
2023-11-29 22:21 ` [PATCH V6 20/20] platform/x86/intel/pmc: Show Die C6 counter on Meteor Lake David E. Box
2023-12-04 13:55 ` [PATCH V6 00/20] intel_pmc: Add telemetry API to read counters Hans de Goede

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