From: Maxime Chevallier <maxime.chevallier@bootlin.com>
To: Daniel Golle <daniel@makrotopia.org>
Cc: "David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Felix Fietkau <nbd@nbd.name>, John Crispin <john@phrozen.org>,
Sean Wang <sean.wang@mediatek.com>,
Mark Lee <Mark-MC.Lee@mediatek.com>,
Lorenzo Bianconi <lorenzo@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Andrew Lunn <andrew@lunn.ch>,
Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <linux@armlinux.org.uk>,
Alexander Couzens <lynxis@fe80.eu>,
Qingfang Deng <dqfext@gmail.com>,
SkyLake Huang <SkyLake.Huang@mediatek.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
netdev@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
linux-phy@lists.infradead.org
Subject: Re: [RFC PATCH v2 2/8] phy: add driver for MediaTek pextp 10GE SerDes PHY
Date: Wed, 6 Dec 2023 10:44:48 +0100 [thread overview]
Message-ID: <20231206104448.0774da58@device.home> (raw)
In-Reply-To: <63636378a52dd1ea7370dbf0ca3037a7d24004b9.1701826319.git.daniel@makrotopia.org>
Hello Daniel,
On Wed, 6 Dec 2023 01:44:08 +0000
Daniel Golle <daniel@makrotopia.org> wrote:
> Add driver for MediaTek's pextp 10 Gigabit/s Ethernet SerDes PHY which
> can be found in the MT7988 SoC.
>
> The PHY can operates only in PHY_MODE_ETHERNET, the submode is one of
> PHY_INTERFACE_MODE_* corresponding to the supported modes:
>
> * USXGMII
> * 10GBase-R
> * 5GBase-R
> * 2500Base-X
> * 1000Base-X
> * Cisco SGMII (MAC side)
>
> In order to work-around a performance issue present on the first of
> two PEXTP present in MT7988 special tuning is applied which can be
> selected by adding the mediatek,usxgmii-performance-errata property to
> the device tree node.
>
> There is no documentation what-so-ever for the pextp registers and
> this driver is based on a GPL licensed implementation found in
> MediaTek's SDK.
>
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> ---
[...]
> +
> +static int mtk_pextp_power_on(struct phy *phy)
> +{
> + struct mtk_pextp_phy *pextp = phy_get_drvdata(phy);
> + int ret;
> +
> + ret = clk_prepare_enable(pextp->clk[0]);
> + if (ret)
> + return ret;
> +
> + return clk_prepare_enable(pextp->clk[1]);
> +}
clk_bulk operations could be used here
> +static int mtk_pextp_power_off(struct phy *phy)
> +{
> + struct mtk_pextp_phy *pextp = phy_get_drvdata(phy);
> +
> + clk_disable_unprepare(pextp->clk[1]);
> + clk_disable_unprepare(pextp->clk[0]);
> +
> + return 0;
> +}
Here
> +static const struct phy_ops mtk_pextp_ops = {
> + .power_on = mtk_pextp_power_on,
> + .power_off = mtk_pextp_power_off,
> + .set_mode = mtk_pextp_set_mode,
> + .reset = mtk_pextp_reset,
> + .owner = THIS_MODULE,
> +};
> +
> +static int mtk_pextp_probe(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + struct phy_provider *phy_provider;
> + struct mtk_pextp_phy *pextp;
> + struct phy *phy;
> +
> + if (!np)
> + return -ENODEV;
> +
> + pextp = devm_kzalloc(&pdev->dev, sizeof(*pextp), GFP_KERNEL);
> + if (!pextp)
> + return -ENOMEM;
> +
> + pextp->base = devm_of_iomap(&pdev->dev, np, 0, NULL);
> + if (!pextp->base)
> + return -EIO;
> +
> + pextp->dev = &pdev->dev;
> + pextp->clk[0] = devm_clk_get(&pdev->dev, "topxtal");
> + if (IS_ERR(pextp->clk[0]))
> + return PTR_ERR(pextp->clk[0]);
> +
> + pextp->clk[1] = devm_clk_get(&pdev->dev, "xfipll");
> + if (IS_ERR(pextp->clk[1]))
> + return PTR_ERR(pextp->clk[1]);
And here as well.
Thanks,
Maxime
WARNING: multiple messages have this Message-ID (diff)
From: Maxime Chevallier <maxime.chevallier@bootlin.com>
To: Daniel Golle <daniel@makrotopia.org>
Cc: "David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Felix Fietkau <nbd@nbd.name>, John Crispin <john@phrozen.org>,
Sean Wang <sean.wang@mediatek.com>,
Mark Lee <Mark-MC.Lee@mediatek.com>,
Lorenzo Bianconi <lorenzo@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Andrew Lunn <andrew@lunn.ch>,
Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <linux@armlinux.org.uk>,
Alexander Couzens <lynxis@fe80.eu>,
Qingfang Deng <dqfext@gmail.com>,
SkyLake Huang <SkyLake.Huang@mediatek.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
netdev@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
linux-phy@lists.infradead.org
Subject: Re: [RFC PATCH v2 2/8] phy: add driver for MediaTek pextp 10GE SerDes PHY
Date: Wed, 6 Dec 2023 10:44:48 +0100 [thread overview]
Message-ID: <20231206104448.0774da58@device.home> (raw)
In-Reply-To: <63636378a52dd1ea7370dbf0ca3037a7d24004b9.1701826319.git.daniel@makrotopia.org>
Hello Daniel,
On Wed, 6 Dec 2023 01:44:08 +0000
Daniel Golle <daniel@makrotopia.org> wrote:
> Add driver for MediaTek's pextp 10 Gigabit/s Ethernet SerDes PHY which
> can be found in the MT7988 SoC.
>
> The PHY can operates only in PHY_MODE_ETHERNET, the submode is one of
> PHY_INTERFACE_MODE_* corresponding to the supported modes:
>
> * USXGMII
> * 10GBase-R
> * 5GBase-R
> * 2500Base-X
> * 1000Base-X
> * Cisco SGMII (MAC side)
>
> In order to work-around a performance issue present on the first of
> two PEXTP present in MT7988 special tuning is applied which can be
> selected by adding the mediatek,usxgmii-performance-errata property to
> the device tree node.
>
> There is no documentation what-so-ever for the pextp registers and
> this driver is based on a GPL licensed implementation found in
> MediaTek's SDK.
>
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> ---
[...]
> +
> +static int mtk_pextp_power_on(struct phy *phy)
> +{
> + struct mtk_pextp_phy *pextp = phy_get_drvdata(phy);
> + int ret;
> +
> + ret = clk_prepare_enable(pextp->clk[0]);
> + if (ret)
> + return ret;
> +
> + return clk_prepare_enable(pextp->clk[1]);
> +}
clk_bulk operations could be used here
> +static int mtk_pextp_power_off(struct phy *phy)
> +{
> + struct mtk_pextp_phy *pextp = phy_get_drvdata(phy);
> +
> + clk_disable_unprepare(pextp->clk[1]);
> + clk_disable_unprepare(pextp->clk[0]);
> +
> + return 0;
> +}
Here
> +static const struct phy_ops mtk_pextp_ops = {
> + .power_on = mtk_pextp_power_on,
> + .power_off = mtk_pextp_power_off,
> + .set_mode = mtk_pextp_set_mode,
> + .reset = mtk_pextp_reset,
> + .owner = THIS_MODULE,
> +};
> +
> +static int mtk_pextp_probe(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + struct phy_provider *phy_provider;
> + struct mtk_pextp_phy *pextp;
> + struct phy *phy;
> +
> + if (!np)
> + return -ENODEV;
> +
> + pextp = devm_kzalloc(&pdev->dev, sizeof(*pextp), GFP_KERNEL);
> + if (!pextp)
> + return -ENOMEM;
> +
> + pextp->base = devm_of_iomap(&pdev->dev, np, 0, NULL);
> + if (!pextp->base)
> + return -EIO;
> +
> + pextp->dev = &pdev->dev;
> + pextp->clk[0] = devm_clk_get(&pdev->dev, "topxtal");
> + if (IS_ERR(pextp->clk[0]))
> + return PTR_ERR(pextp->clk[0]);
> +
> + pextp->clk[1] = devm_clk_get(&pdev->dev, "xfipll");
> + if (IS_ERR(pextp->clk[1]))
> + return PTR_ERR(pextp->clk[1]);
And here as well.
Thanks,
Maxime
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
WARNING: multiple messages have this Message-ID (diff)
From: Maxime Chevallier <maxime.chevallier@bootlin.com>
To: Daniel Golle <daniel@makrotopia.org>
Cc: "David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Felix Fietkau <nbd@nbd.name>, John Crispin <john@phrozen.org>,
Sean Wang <sean.wang@mediatek.com>,
Mark Lee <Mark-MC.Lee@mediatek.com>,
Lorenzo Bianconi <lorenzo@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Andrew Lunn <andrew@lunn.ch>,
Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <linux@armlinux.org.uk>,
Alexander Couzens <lynxis@fe80.eu>,
Qingfang Deng <dqfext@gmail.com>,
SkyLake Huang <SkyLake.Huang@mediatek.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
netdev@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
linux-phy@lists.infradead.org
Subject: Re: [RFC PATCH v2 2/8] phy: add driver for MediaTek pextp 10GE SerDes PHY
Date: Wed, 6 Dec 2023 10:44:48 +0100 [thread overview]
Message-ID: <20231206104448.0774da58@device.home> (raw)
In-Reply-To: <63636378a52dd1ea7370dbf0ca3037a7d24004b9.1701826319.git.daniel@makrotopia.org>
Hello Daniel,
On Wed, 6 Dec 2023 01:44:08 +0000
Daniel Golle <daniel@makrotopia.org> wrote:
> Add driver for MediaTek's pextp 10 Gigabit/s Ethernet SerDes PHY which
> can be found in the MT7988 SoC.
>
> The PHY can operates only in PHY_MODE_ETHERNET, the submode is one of
> PHY_INTERFACE_MODE_* corresponding to the supported modes:
>
> * USXGMII
> * 10GBase-R
> * 5GBase-R
> * 2500Base-X
> * 1000Base-X
> * Cisco SGMII (MAC side)
>
> In order to work-around a performance issue present on the first of
> two PEXTP present in MT7988 special tuning is applied which can be
> selected by adding the mediatek,usxgmii-performance-errata property to
> the device tree node.
>
> There is no documentation what-so-ever for the pextp registers and
> this driver is based on a GPL licensed implementation found in
> MediaTek's SDK.
>
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> ---
[...]
> +
> +static int mtk_pextp_power_on(struct phy *phy)
> +{
> + struct mtk_pextp_phy *pextp = phy_get_drvdata(phy);
> + int ret;
> +
> + ret = clk_prepare_enable(pextp->clk[0]);
> + if (ret)
> + return ret;
> +
> + return clk_prepare_enable(pextp->clk[1]);
> +}
clk_bulk operations could be used here
> +static int mtk_pextp_power_off(struct phy *phy)
> +{
> + struct mtk_pextp_phy *pextp = phy_get_drvdata(phy);
> +
> + clk_disable_unprepare(pextp->clk[1]);
> + clk_disable_unprepare(pextp->clk[0]);
> +
> + return 0;
> +}
Here
> +static const struct phy_ops mtk_pextp_ops = {
> + .power_on = mtk_pextp_power_on,
> + .power_off = mtk_pextp_power_off,
> + .set_mode = mtk_pextp_set_mode,
> + .reset = mtk_pextp_reset,
> + .owner = THIS_MODULE,
> +};
> +
> +static int mtk_pextp_probe(struct platform_device *pdev)
> +{
> + struct device_node *np = pdev->dev.of_node;
> + struct phy_provider *phy_provider;
> + struct mtk_pextp_phy *pextp;
> + struct phy *phy;
> +
> + if (!np)
> + return -ENODEV;
> +
> + pextp = devm_kzalloc(&pdev->dev, sizeof(*pextp), GFP_KERNEL);
> + if (!pextp)
> + return -ENOMEM;
> +
> + pextp->base = devm_of_iomap(&pdev->dev, np, 0, NULL);
> + if (!pextp->base)
> + return -EIO;
> +
> + pextp->dev = &pdev->dev;
> + pextp->clk[0] = devm_clk_get(&pdev->dev, "topxtal");
> + if (IS_ERR(pextp->clk[0]))
> + return PTR_ERR(pextp->clk[0]);
> +
> + pextp->clk[1] = devm_clk_get(&pdev->dev, "xfipll");
> + if (IS_ERR(pextp->clk[1]))
> + return PTR_ERR(pextp->clk[1]);
And here as well.
Thanks,
Maxime
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-12-06 9:45 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-06 1:43 [RFC PATCH v2 0/8] Add support for 10G Ethernet SerDes on MT7988 Daniel Golle
2023-12-06 1:43 ` Daniel Golle
2023-12-06 1:43 ` Daniel Golle
2023-12-06 1:43 ` [RFC PATCH v2 1/8] dt-bindings: phy: mediatek,xfi-pextp: add new bindings Daniel Golle
2023-12-06 1:43 ` Daniel Golle
2023-12-06 1:43 ` Daniel Golle
2023-12-06 3:39 ` Rob Herring
2023-12-06 3:39 ` Rob Herring
2023-12-06 3:39 ` Rob Herring
2023-12-06 1:44 ` [RFC PATCH v2 2/8] phy: add driver for MediaTek pextp 10GE SerDes PHY Daniel Golle
2023-12-06 1:44 ` Daniel Golle
2023-12-06 1:44 ` Daniel Golle
2023-12-06 9:44 ` Maxime Chevallier [this message]
2023-12-06 9:44 ` Maxime Chevallier
2023-12-06 9:44 ` Maxime Chevallier
2023-12-06 1:44 ` [RFC PATCH v2 3/8] net: pcs: pcs-mtk-lynxi: add platform driver for MT7988 Daniel Golle
2023-12-06 1:44 ` Daniel Golle
2023-12-06 1:44 ` Daniel Golle
2023-12-06 9:38 ` Maxime Chevallier
2023-12-06 9:38 ` Maxime Chevallier
2023-12-06 9:38 ` Maxime Chevallier
2023-12-06 17:51 ` Russell King (Oracle)
2023-12-06 17:51 ` Russell King (Oracle)
2023-12-06 17:51 ` Russell King (Oracle)
2023-12-07 0:07 ` Daniel Golle
2023-12-07 0:07 ` Daniel Golle
2023-12-07 0:07 ` Daniel Golle
2023-12-06 1:44 ` [RFC PATCH v2 4/8] dt-bindings: net: pcs: add bindings for MediaTek USXGMII PCS Daniel Golle
2023-12-06 1:44 ` Daniel Golle
2023-12-06 1:44 ` Daniel Golle
2023-12-06 3:39 ` Rob Herring
2023-12-06 3:39 ` Rob Herring
2023-12-06 3:39 ` Rob Herring
2023-12-06 1:44 ` [RFC PATCH v2 5/8] net: pcs: add driver " Daniel Golle
2023-12-06 1:44 ` Daniel Golle
2023-12-06 1:44 ` Daniel Golle
2023-12-06 3:39 ` Rob Herring
2023-12-06 3:39 ` Rob Herring
2023-12-06 3:39 ` Rob Herring
2023-12-06 9:58 ` Maxime Chevallier
2023-12-06 9:58 ` Maxime Chevallier
2023-12-06 9:58 ` Maxime Chevallier
2023-12-06 17:58 ` Russell King (Oracle)
2023-12-06 17:58 ` Russell King (Oracle)
2023-12-06 17:58 ` Russell King (Oracle)
2023-12-06 18:58 ` Maxime Chevallier
2023-12-06 18:58 ` Maxime Chevallier
2023-12-06 18:58 ` Maxime Chevallier
2023-12-06 13:34 ` Rob Herring
2023-12-06 13:34 ` Rob Herring
2023-12-06 13:34 ` Rob Herring
2023-12-06 13:37 ` Daniel Golle
2023-12-06 13:37 ` Daniel Golle
2023-12-06 13:37 ` Daniel Golle
2023-12-06 17:56 ` Russell King (Oracle)
2023-12-06 17:56 ` Russell King (Oracle)
2023-12-06 17:56 ` Russell King (Oracle)
2023-12-06 1:44 ` [RFC PATCH v2 6/8] dt-bindings: net: mediatek: remove wrongly added clocks and SerDes Daniel Golle
2023-12-06 1:44 ` Daniel Golle
2023-12-06 1:44 ` Daniel Golle
2023-12-06 3:39 ` Rob Herring
2023-12-06 3:39 ` Rob Herring
2023-12-06 3:39 ` Rob Herring
2023-12-06 1:45 ` [RFC PATCH v2 7/8] dt-bindings: net: mediatek,net: fix and complete mt7988-eth binding Daniel Golle
2023-12-06 1:45 ` Daniel Golle
2023-12-06 1:45 ` Daniel Golle
2023-12-06 3:39 ` Rob Herring
2023-12-06 3:39 ` Rob Herring
2023-12-06 3:39 ` Rob Herring
2023-12-06 13:38 ` Rob Herring
2023-12-06 13:38 ` Rob Herring
2023-12-06 13:38 ` Rob Herring
2023-12-06 16:08 ` Daniel Golle
2023-12-06 16:08 ` Daniel Golle
2023-12-06 16:08 ` Daniel Golle
2023-12-06 1:45 ` [RFC PATCH v2 8/8] net: ethernet: mtk_eth_soc: add paths and SerDes modes for MT7988 Daniel Golle
2023-12-06 1:45 ` Daniel Golle
2023-12-06 1:45 ` Daniel Golle
2023-12-06 18:55 ` Russell King (Oracle)
2023-12-06 18:55 ` Russell King (Oracle)
2023-12-06 18:55 ` Russell King (Oracle)
2023-12-06 19:52 ` Daniel Golle
2023-12-06 19:52 ` Daniel Golle
2023-12-06 19:52 ` Daniel Golle
2023-12-06 20:23 ` Russell King (Oracle)
2023-12-06 20:23 ` Russell King (Oracle)
2023-12-06 20:23 ` Russell King (Oracle)
2023-12-06 20:47 ` Daniel Golle
2023-12-06 20:47 ` Daniel Golle
2023-12-06 20:47 ` Daniel Golle
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