From: Ben Cheatham <Benjamin.Cheatham@amd.com>
To: <linux-cxl@vger.kernel.org>, <linux-pci@vger.kernel.org>
Cc: <dave@stgolabs.net>, <jonathan.cameron@huawei.com>,
<dave.jiang@intel.com>, <alison.schofield@intel.com>,
<vishal.l.verma@intel.com>, <ira.weiny@intel.com>,
<dan.j.williams@intel.com>, <bhelgaas@google.com>,
<benjamin.cheatham@amd.com>
Subject: [RFC PATCH 1/6] cxl/core: Add CXL Timeout & Isolation capability parsing
Date: Thu, 15 Feb 2024 13:40:43 -0600 [thread overview]
Message-ID: <20240215194048.141411-2-Benjamin.Cheatham@amd.com> (raw)
In-Reply-To: <20240215194048.141411-1-Benjamin.Cheatham@amd.com>
Add parsing and mapping of the CXL Timeout & Isolation capability
structure (CXL 3.1 8.2.4.24) to regs.c.
Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
drivers/cxl/core/regs.c | 7 +++++++
drivers/cxl/cxl.h | 6 ++++++
2 files changed, 13 insertions(+)
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index 372786f80955..fe0c19826a6a 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -92,6 +92,12 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base,
length = CXL_RAS_CAPABILITY_LENGTH;
rmap = &map->ras;
break;
+ case CXL_CM_CAP_CAP_ID_TIMEOUT:
+ dev_dbg(dev, "found Isolation & Timeout capability (0x%x)\n",
+ offset);
+ length = CXL_TIMEOUT_CAPABILITY_LENGTH;
+ rmap = &map->timeout;
+ break;
default:
dev_dbg(dev, "Unknown CM cap ID: %d (0x%x)\n", cap_id,
offset);
@@ -211,6 +217,7 @@ int cxl_map_component_regs(const struct cxl_register_map *map,
} mapinfo[] = {
{ &map->component_map.hdm_decoder, ®s->hdm_decoder },
{ &map->component_map.ras, ®s->ras },
+ { &map->component_map.timeout, ®s->timeout },
};
int i;
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index b6017c0c57b4..87f3178d6642 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -36,6 +36,7 @@
#define CXL_CM_CAP_CAP_ID_RAS 0x2
#define CXL_CM_CAP_CAP_ID_HDM 0x5
+#define CXL_CM_CAP_CAP_ID_TIMEOUT 0x9
#define CXL_CM_CAP_CAP_HDM_VERSION 1
/* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */
@@ -126,6 +127,9 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw)
return 0;
}
+/* CXL 3.0 8.2.4.23 CXL Timeout and Isolation Capability Structure */
+#define CXL_TIMEOUT_CAPABILITY_OFFSET 0x0
+#define CXL_TIMEOUT_CAPABILITY_LENGTH 0x10
/* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */
#define CXL_RAS_UNCORRECTABLE_STATUS_OFFSET 0x0
#define CXL_RAS_UNCORRECTABLE_STATUS_MASK (GENMASK(16, 14) | GENMASK(11, 0))
@@ -208,6 +212,7 @@ struct cxl_regs {
struct_group_tagged(cxl_component_regs, component,
void __iomem *hdm_decoder;
void __iomem *ras;
+ void __iomem *timeout;
);
/*
* Common set of CXL Device register block base pointers
@@ -242,6 +247,7 @@ struct cxl_reg_map {
struct cxl_component_reg_map {
struct cxl_reg_map hdm_decoder;
struct cxl_reg_map ras;
+ struct cxl_reg_map timeout;
};
struct cxl_device_reg_map {
--
2.34.1
next prev parent reply other threads:[~2024-02-15 19:41 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-15 19:40 [RFC PATCH 0/6] Implement initial CXL Timeout & Isolation support Ben Cheatham
2024-02-15 19:40 ` Ben Cheatham [this message]
2024-02-15 19:40 ` [RFC PATCH 2/6] pcie/cxl_timeout: Add CXL Timeout & Isolation service driver Ben Cheatham
2024-02-15 21:13 ` Bjorn Helgaas
2024-02-15 22:21 ` Ben Cheatham
2024-02-15 22:26 ` Bjorn Helgaas
2024-02-15 19:40 ` [RFC PATCH 3/6] pcie/cxl_timeout: Add CXL.mem timeout range programming Ben Cheatham
2024-02-15 21:35 ` Bjorn Helgaas
2024-02-15 22:21 ` Ben Cheatham
2024-02-15 22:29 ` Bjorn Helgaas
2024-02-15 22:30 ` Ben Cheatham
2024-02-15 19:40 ` [RFC PATCH 4/6] pcie/cxl_timeout: Add CXL.mem error isolation support Ben Cheatham
2024-02-15 21:49 ` Bjorn Helgaas
2024-02-15 22:21 ` Ben Cheatham
2024-02-15 19:40 ` [RFC PATCH 5/6] pcie/portdrv: Add CXL MSI/-X allocation Ben Cheatham
2024-02-15 21:51 ` Bjorn Helgaas
2024-02-15 22:22 ` Ben Cheatham
2024-02-15 19:40 ` [RFC PATCH 6/6] pcie/cxl_timeout: Add CXL.mem Timeout & Isolation interrupt support Ben Cheatham
2024-02-15 21:57 ` Bjorn Helgaas
2024-02-15 22:22 ` Ben Cheatham
2024-02-17 21:31 ` kernel test robot
2024-02-17 22:44 ` kernel test robot
2024-02-17 22:55 ` kernel test robot
2024-02-15 23:43 ` [RFC PATCH 0/6] Implement initial CXL Timeout & Isolation support Dan Williams
2024-03-25 15:15 ` Ben Cheatham
2024-03-25 15:54 ` Dan Williams
2024-04-01 19:41 ` Ben Cheatham
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240215194048.141411-2-Benjamin.Cheatham@amd.com \
--to=benjamin.cheatham@amd.com \
--cc=alison.schofield@intel.com \
--cc=bhelgaas@google.com \
--cc=dan.j.williams@intel.com \
--cc=dave.jiang@intel.com \
--cc=dave@stgolabs.net \
--cc=ira.weiny@intel.com \
--cc=jonathan.cameron@huawei.com \
--cc=linux-cxl@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=vishal.l.verma@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.