[RFC PATCH 5/6] pcie/portdrv: Add CXL MSI/-X allocation

[Ben Cheatham <Benjamin.Cheatham@amd.com>]

Allocate an MSI/-X for CXL-enabled PCIe root ports that support
timeout & isolation interrupts. This vector will be used by the
CXL timeout & isolation service driver to disable the root port
in the CXL port hierarchy and any associated memory if the port
enters isolation.

Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
 drivers/cxl/cxl.h              |  2 ++
 drivers/pci/pcie/cxl_timeout.c | 11 ++++++++++-
 drivers/pci/pcie/portdrv.c     | 35 +++++++++++++++++++++++++++++++---
 drivers/pci/pcie/portdrv.h     |  6 ++++++
 4 files changed, 50 insertions(+), 4 deletions(-)

diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index b1d5232a0127..3b5645ec95b9 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -132,6 +132,8 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw)
 #define   CXL_TIMEOUT_CAP_MEM_TIMEOUT_MASK GENMASK(3, 0)
 #define   CXL_TIMEOUT_CAP_MEM_TIMEOUT_SUPP BIT(4)
 #define   CXL_TIMEOUT_CAP_MEM_ISO_SUPP BIT(16)
+#define   CXL_TIMEOUT_CAP_INTR_SUPP BIT(26)
+#define   CXL_TIMEOUT_CAP_INTR_MASK GENMASK(31, 27)
 #define CXL_TIMEOUT_CONTROL_OFFSET 0x8
 #define   CXL_TIMEOUT_CONTROL_MEM_TIMEOUT_MASK GENMASK(3, 0)
 #define   CXL_TIMEOUT_CONTROL_MEM_TIMEOUT_ENABLE BIT(4)
diff --git a/drivers/pci/pcie/cxl_timeout.c b/drivers/pci/pcie/cxl_timeout.c
index 5900239e5bbf..352d9370a999 100644
--- a/drivers/pci/pcie/cxl_timeout.c
+++ b/drivers/pci/pcie/cxl_timeout.c
@@ -99,7 +99,7 @@ static struct cxl_timeout *cxl_create_cxlt(struct pcie_device *dev)
 	return ERR_PTR(rc);
 }
 
-int cxl_find_timeout_cap(struct pci_dev *dev, u32 *cap)
+int pcie_cxl_find_timeout_cap(struct pci_dev *dev, u32 *cap)
 {
 	struct cxl_component_regs regs;
 	struct cxl_register_map map;
@@ -115,6 +115,15 @@ int cxl_find_timeout_cap(struct pci_dev *dev, u32 *cap)
 	return rc;
 }
 
+bool pcie_supports_cxl_timeout_interrupts(u32 cap)
+{
+	if (!(cap & CXL_TIMEOUT_CAP_INTR_SUPP))
+		return false;
+
+	return (cap & CXL_TIMEOUT_CAP_MEM_ISO_SUPP) ||
+		(cap & CXL_TIMEOUT_CAP_MEM_TIMEOUT_SUPP);
+}
+
 static struct pcie_cxlt_data *cxlt_create_pdata(struct pcie_device *dev)
 {
 	struct pcie_cxlt_data *data;
diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c
index 7aa0a6f2da4e..c36fe6ccfeae 100644
--- a/drivers/pci/pcie/portdrv.c
+++ b/drivers/pci/pcie/portdrv.c
@@ -21,6 +21,7 @@
 
 #include "../pci.h"
 #include "portdrv.h"
+#include "../../cxl/cxlpci.h"
 
 /*
  * The PCIe Capability Interrupt Message Number (PCIe r3.1, sec 7.8.2) must
@@ -55,7 +56,7 @@ static void release_pcie_device(struct device *dev)
  * required to accommodate the largest Message Number.
  */
 static int pcie_message_numbers(struct pci_dev *dev, int mask,
-				u32 *pme, u32 *aer, u32 *dpc)
+				u32 *pme, u32 *aer, u32 *dpc, u32 *cxl)
 {
 	u32 nvec = 0, pos;
 	u16 reg16;
@@ -98,6 +99,19 @@ static int pcie_message_numbers(struct pci_dev *dev, int mask,
 		}
 	}
 
+#ifdef CONFIG_PCIE_CXL_TIMEOUT
+	if (mask & PCIE_PORT_SERVICE_CXLT) {
+		u32 cap;
+
+		if (!pcie_cxl_find_timeout_cap(dev, &cap) &&
+		    pcie_supports_cxl_timeout_interrupts(cap)) {
+			*cxl = FIELD_GET(CXL_TIMEOUT_CAP_INTR_MASK,
+					 pos);
+			nvec = max(nvec, *cxl + 1);
+		}
+	}
+#endif
+
 	return nvec;
 }
 
@@ -113,7 +127,7 @@ static int pcie_message_numbers(struct pci_dev *dev, int mask,
 static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask)
 {
 	int nr_entries, nvec, pcie_irq;
-	u32 pme = 0, aer = 0, dpc = 0;
+	u32 pme = 0, aer = 0, dpc = 0, cxlt = 0;
 
 	/* Allocate the maximum possible number of MSI/MSI-X vectors */
 	nr_entries = pci_alloc_irq_vectors(dev, 1, PCIE_PORT_MAX_MSI_ENTRIES,
@@ -122,7 +136,7 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask)
 		return nr_entries;
 
 	/* See how many and which Interrupt Message Numbers we actually use */
-	nvec = pcie_message_numbers(dev, mask, &pme, &aer, &dpc);
+	nvec = pcie_message_numbers(dev, mask, &pme, &aer, &dpc, &cxlt);
 	if (nvec > nr_entries) {
 		pci_free_irq_vectors(dev);
 		return -EIO;
@@ -163,6 +177,9 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev, int *irqs, int mask)
 	if (mask & PCIE_PORT_SERVICE_DPC)
 		irqs[PCIE_PORT_SERVICE_DPC_SHIFT] = pci_irq_vector(dev, dpc);
 
+	if (mask & PCIE_PORT_SERVICE_CXLT)
+		irqs[PCIE_PORT_SERVICE_CXLT_SHIFT] = pci_irq_vector(dev, cxlt);
+
 	return 0;
 }
 
@@ -274,6 +291,18 @@ static int get_port_device_capability(struct pci_dev *dev)
 			services |= PCIE_PORT_SERVICE_BWNOTIF;
 	}
 
+#ifdef CONFIG_PCIE_CXL_TIMEOUT
+	if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT &&
+	    pci_find_dvsec_capability(dev, PCI_DVSEC_VENDOR_ID_CXL,
+				      CXL_DVSEC_PORT_EXTENSIONS)) {
+		u32 cap;
+
+		if (!pcie_cxl_find_timeout_cap(dev, &cap) &&
+		    pcie_supports_cxl_timeout_interrupts(cap))
+			services |= PCIE_PORT_SERVICE_CXLT;
+	}
+#endif
+
 	return services;
 }
 
diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h
index 5395a0e36956..f89e7366e986 100644
--- a/drivers/pci/pcie/portdrv.h
+++ b/drivers/pci/pcie/portdrv.h
@@ -129,4 +129,10 @@ static inline void pcie_pme_interrupt_enable(struct pci_dev *dev, bool en) {}
 #endif /* !CONFIG_PCIE_PME */
 
 struct device *pcie_port_find_device(struct pci_dev *dev, u32 service);
+
+#ifdef CONFIG_PCIE_CXL_TIMEOUT
+int pcie_cxl_find_timeout_cap(struct pci_dev *dev, u32 *cap);
+bool pcie_supports_cxl_timeout_interrupts(u32 cap);
+#endif
+
 #endif /* _PORTDRV_H_ */
-- 
2.34.1