All of lore.kernel.org
 help / color / mirror / Atom feed
From: Deepak Gupta <debug@rivosinc.com>
To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	llvm@lists.linux.dev
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, nathan@kernel.org,
	ndesaulniers@google.com, morbo@google.com,
	justinstitt@google.com, andy.chiu@sifive.com, debug@rivosinc.com,
	hankuan.chen@sifive.com, guoren@kernel.org,
	greentime.hu@sifive.com, samitolvanen@google.com,
	cleger@rivosinc.com, apatel@ventanamicro.com,
	ajones@ventanamicro.com, conor.dooley@microchip.com,
	mchitale@ventanamicro.com, dbarboza@ventanamicro.com,
	waylingii@gmail.com, sameo@rivosinc.com, alexghiti@rivosinc.com,
	akpm@linux-foundation.org, shikemeng@huaweicloud.com,
	rppt@kernel.org, charlie@rivosinc.com, xiao.w.wang@intel.com,
	willy@infradead.org, jszhang@kernel.org, leobras@redhat.com,
	songshuaishuai@tinylab.org, haxel@fzi.de,
	samuel.holland@sifive.com, namcaov@gmail.com, bjorn@rivosinc.com,
	cuiyunhui@bytedance.com, wangkefeng.wang@huawei.com,
	falcon@tinylab.org, viro@zeniv.linux.org.uk, bhe@redhat.com,
	chenjiahao16@huawei.com, hca@linux.ibm.com, arnd@arndb.de,
	kent.overstreet@linux.dev, boqun.feng@gmail.com, oleg@redhat.com,
	paulmck@kernel.org, broonie@kernel.org,
	rick.p.edgecombe@intel.com
Subject: [RFC PATCH 05/12] riscv: fix certain indirect jumps for kernel cfi
Date: Mon,  8 Apr 2024 23:10:36 -0700	[thread overview]
Message-ID: <20240409061043.3269676-6-debug@rivosinc.com> (raw)
In-Reply-To: <20240409061043.3269676-1-debug@rivosinc.com>

Handwritten `__memset` asm routine performs certain static jumps within
function and uses `a5` to do that. This would require a landing pad
instruction at the target. Since its static jump and no memory load is
involved, use `t2` instead which is exempt from requiring a landing pad.

Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
 arch/riscv/lib/memset.S | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/lib/memset.S b/arch/riscv/lib/memset.S
index 35f358e70bdb..e129ebf66986 100644
--- a/arch/riscv/lib/memset.S
+++ b/arch/riscv/lib/memset.S
@@ -56,12 +56,12 @@ SYM_FUNC_START(__memset)
 
 	/* Jump into loop body */
 	/* Assumes 32-bit instruction lengths */
-	la a5, 3f
+	la t2, 3f
 #ifdef CONFIG_64BIT
 	srli a4, a4, 1
 #endif
-	add a5, a5, a4
-	jr a5
+	add t2, t2, a4
+	jr t2
 3:
 	REG_S a1,        0(t0)
 	REG_S a1,    SZREG(t0)
-- 
2.43.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Deepak Gupta <debug@rivosinc.com>
To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	llvm@lists.linux.dev
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, nathan@kernel.org,
	ndesaulniers@google.com, morbo@google.com,
	justinstitt@google.com, andy.chiu@sifive.com, debug@rivosinc.com,
	hankuan.chen@sifive.com, guoren@kernel.org,
	greentime.hu@sifive.com, samitolvanen@google.com,
	cleger@rivosinc.com, apatel@ventanamicro.com,
	ajones@ventanamicro.com, conor.dooley@microchip.com,
	mchitale@ventanamicro.com, dbarboza@ventanamicro.com,
	waylingii@gmail.com, sameo@rivosinc.com, alexghiti@rivosinc.com,
	akpm@linux-foundation.org, shikemeng@huaweicloud.com,
	rppt@kernel.org, charlie@rivosinc.com, xiao.w.wang@intel.com,
	willy@infradead.org, jszhang@kernel.org, leobras@redhat.com,
	songshuaishuai@tinylab.org, haxel@fzi.de,
	samuel.holland@sifive.com, namcaov@gmail.com, bjorn@rivosinc.com,
	cuiyunhui@bytedance.com, wangkefeng.wang@huawei.com,
	falcon@tinylab.org, viro@zeniv.linux.org.uk, bhe@redhat.com,
	chenjiahao16@huawei.com, hca@linux.ibm.com, arnd@arndb.de,
	kent.overstreet@linux.dev, boqun.feng@gmail.com, oleg@redhat.com,
	paulmck@kernel.org, broonie@kernel.org,
	rick.p.edgecombe@intel.com
Subject: [RFC PATCH 05/12] riscv: fix certain indirect jumps for kernel cfi
Date: Mon,  8 Apr 2024 23:10:36 -0700	[thread overview]
Message-ID: <20240409061043.3269676-6-debug@rivosinc.com> (raw)
In-Reply-To: <20240409061043.3269676-1-debug@rivosinc.com>

Handwritten `__memset` asm routine performs certain static jumps within
function and uses `a5` to do that. This would require a landing pad
instruction at the target. Since its static jump and no memory load is
involved, use `t2` instead which is exempt from requiring a landing pad.

Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
 arch/riscv/lib/memset.S | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/lib/memset.S b/arch/riscv/lib/memset.S
index 35f358e70bdb..e129ebf66986 100644
--- a/arch/riscv/lib/memset.S
+++ b/arch/riscv/lib/memset.S
@@ -56,12 +56,12 @@ SYM_FUNC_START(__memset)
 
 	/* Jump into loop body */
 	/* Assumes 32-bit instruction lengths */
-	la a5, 3f
+	la t2, 3f
 #ifdef CONFIG_64BIT
 	srli a4, a4, 1
 #endif
-	add a5, a5, a4
-	jr a5
+	add t2, t2, a4
+	jr t2
 3:
 	REG_S a1,        0(t0)
 	REG_S a1,    SZREG(t0)
-- 
2.43.2


  parent reply	other threads:[~2024-04-09  6:12 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-09  6:10 [RFC PATCH v1] riscv kernel control flow integrity Deepak Gupta
2024-04-09  6:10 ` Deepak Gupta
2024-04-09  6:10 ` [RFC PATCH 01/12] riscv: zicfiss / zicfilp extension csr and bit definitions Deepak Gupta
2024-04-09  6:10   ` Deepak Gupta
2024-04-09  6:10 ` [RFC PATCH 02/12] riscv: add landing pad for asm routines Deepak Gupta
2024-04-09  6:10   ` Deepak Gupta
2024-04-11 17:15   ` Sami Tolvanen
2024-04-11 17:15     ` Sami Tolvanen
2024-04-11 17:53     ` Deepak Gupta
2024-04-11 17:53       ` Deepak Gupta
2024-04-11 18:33       ` Sami Tolvanen
2024-04-11 18:33         ` Sami Tolvanen
2024-04-09  6:10 ` [RFC PATCH 03/12] riscv: after saving expected landing pad (elp), clear elp state Deepak Gupta
2024-04-09  6:10   ` Deepak Gupta
2024-04-09  6:10 ` [RFC PATCH 04/12] riscv: update asm call sites with label setup Deepak Gupta
2024-04-09  6:10   ` Deepak Gupta
2024-04-09  6:10 ` Deepak Gupta [this message]
2024-04-09  6:10   ` [RFC PATCH 05/12] riscv: fix certain indirect jumps for kernel cfi Deepak Gupta
2024-04-09  6:10 ` [RFC PATCH 06/12] scs: place init shadow stack in .shadowstack section Deepak Gupta
2024-04-09  6:10   ` Deepak Gupta
2024-04-09  6:10 ` [RFC PATCH 07/12] riscv/mm: prepare shadow stack for init task for kernel cfi Deepak Gupta
2024-04-09  6:10   ` Deepak Gupta
2024-05-12 20:12   ` Alexandre Ghiti
2024-05-12 20:12     ` Alexandre Ghiti
2024-05-13 18:59     ` Deepak Gupta
2024-05-13 18:59       ` Deepak Gupta
2024-04-09  6:10 ` [RFC PATCH 08/12] riscv: dynamic (zicfiss) shadow call stack support Deepak Gupta
2024-04-09  6:10   ` Deepak Gupta
2024-04-11 17:05   ` Sami Tolvanen
2024-04-11 17:05     ` Sami Tolvanen
2024-04-11 17:30     ` Deepak Gupta
2024-04-11 17:30       ` Deepak Gupta
2024-04-11 17:47       ` Sami Tolvanen
2024-04-11 17:47         ` Sami Tolvanen
2024-04-09  6:10 ` [RFC PATCH 09/12] scs: kernel shadow stack with hardware assistance Deepak Gupta
2024-04-09  6:10   ` Deepak Gupta
2024-04-09  6:10 ` [RFC PATCH 10/12] riscv/traps: Introduce software check exception Deepak Gupta
2024-04-09  6:10   ` Deepak Gupta
2024-04-09  6:10 ` [RFC PATCH 11/12] riscv: Kconfig & Makefile for riscv kernel control flow integrity Deepak Gupta
2024-04-09  6:10   ` Deepak Gupta
2024-04-09  6:10 ` [RFC PATCH 12/12] riscv: enable kernel shadow stack and landing pad enforcement Deepak Gupta
2024-04-09  6:10   ` Deepak Gupta

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20240409061043.3269676-6-debug@rivosinc.com \
    --to=debug@rivosinc.com \
    --cc=ajones@ventanamicro.com \
    --cc=akpm@linux-foundation.org \
    --cc=alexghiti@rivosinc.com \
    --cc=andy.chiu@sifive.com \
    --cc=aou@eecs.berkeley.edu \
    --cc=apatel@ventanamicro.com \
    --cc=arnd@arndb.de \
    --cc=bhe@redhat.com \
    --cc=bjorn@rivosinc.com \
    --cc=boqun.feng@gmail.com \
    --cc=broonie@kernel.org \
    --cc=charlie@rivosinc.com \
    --cc=chenjiahao16@huawei.com \
    --cc=cleger@rivosinc.com \
    --cc=conor.dooley@microchip.com \
    --cc=cuiyunhui@bytedance.com \
    --cc=dbarboza@ventanamicro.com \
    --cc=falcon@tinylab.org \
    --cc=greentime.hu@sifive.com \
    --cc=guoren@kernel.org \
    --cc=hankuan.chen@sifive.com \
    --cc=haxel@fzi.de \
    --cc=hca@linux.ibm.com \
    --cc=jszhang@kernel.org \
    --cc=justinstitt@google.com \
    --cc=kent.overstreet@linux.dev \
    --cc=leobras@redhat.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=llvm@lists.linux.dev \
    --cc=mchitale@ventanamicro.com \
    --cc=morbo@google.com \
    --cc=namcaov@gmail.com \
    --cc=nathan@kernel.org \
    --cc=ndesaulniers@google.com \
    --cc=oleg@redhat.com \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    --cc=paulmck@kernel.org \
    --cc=rick.p.edgecombe@intel.com \
    --cc=rppt@kernel.org \
    --cc=sameo@rivosinc.com \
    --cc=samitolvanen@google.com \
    --cc=samuel.holland@sifive.com \
    --cc=shikemeng@huaweicloud.com \
    --cc=songshuaishuai@tinylab.org \
    --cc=viro@zeniv.linux.org.uk \
    --cc=wangkefeng.wang@huawei.com \
    --cc=waylingii@gmail.com \
    --cc=willy@infradead.org \
    --cc=xiao.w.wang@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.