From: Frank Li <Frank.Li@nxp.com>
To: Shawn Guo <shawnguo@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-arm-kernel@lists.infradead.org (moderated
list:ARM/FREESCALE LAYERSCAPE ARM ARCHITECTURE),
devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND
FLATTENED DEVICE TREE BINDINGS),
linux-kernel@vger.kernel.org (open list)
Cc: imx@lists.linux.dev
Subject: [PATCH v2 08/13] arm64: dts: layerscape: rename node name "wdt" to "watchdog"
Date: Wed, 26 Jun 2024 16:25:28 -0400 [thread overview]
Message-ID: <20240626202533.2182846-9-Frank.Li@nxp.com> (raw)
In-Reply-To: <20240626202533.2182846-1-Frank.Li@nxp.com>
Rename node name "wdt" to "watchdog" to fix below warning:
arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dtb:
wdt@c000000: $nodename:0: 'wdt@c000000' does not match '^(timer|watchdog)(@.*|-([0-9]|[1-9][0-9]+))?$
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 16 ++++++++--------
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 16 ++++++++--------
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 81b80b6b27d31..83236428e4cfd 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -880,7 +880,7 @@ pcs7_3: ethernet-phy@3 {
};
};
- cluster1_core0_watchdog: wdt@c000000 {
+ cluster1_core0_watchdog: watchdog@c000000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc000000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -890,7 +890,7 @@ QORIQ_CLK_PLL_DIV(16)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster1_core1_watchdog: wdt@c010000 {
+ cluster1_core1_watchdog: watchdog@c010000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc010000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -900,7 +900,7 @@ QORIQ_CLK_PLL_DIV(16)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster1_core2_watchdog: wdt@c020000 {
+ cluster1_core2_watchdog: watchdog@c020000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc020000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -910,7 +910,7 @@ QORIQ_CLK_PLL_DIV(16)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster1_core3_watchdog: wdt@c030000 {
+ cluster1_core3_watchdog: watchdog@c030000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc030000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -920,7 +920,7 @@ QORIQ_CLK_PLL_DIV(16)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster2_core0_watchdog: wdt@c100000 {
+ cluster2_core0_watchdog: watchdog@c100000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc100000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -930,7 +930,7 @@ QORIQ_CLK_PLL_DIV(16)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster2_core1_watchdog: wdt@c110000 {
+ cluster2_core1_watchdog: watchdog@c110000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc110000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -940,7 +940,7 @@ QORIQ_CLK_PLL_DIV(16)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster2_core2_watchdog: wdt@c120000 {
+ cluster2_core2_watchdog: watchdog@c120000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc120000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -950,7 +950,7 @@ QORIQ_CLK_PLL_DIV(16)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster2_core3_watchdog: wdt@c130000 {
+ cluster2_core3_watchdog: watchdog@c130000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc130000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index dac33a3eab841..fe4755c54af2e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -389,7 +389,7 @@ serial3: serial@21d0600 {
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
};
- cluster1_core0_watchdog: wdt@c000000 {
+ cluster1_core0_watchdog: watchdog@c000000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc000000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -399,7 +399,7 @@ QORIQ_CLK_PLL_DIV(4)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster1_core1_watchdog: wdt@c010000 {
+ cluster1_core1_watchdog: watchdog@c010000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc010000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -409,7 +409,7 @@ QORIQ_CLK_PLL_DIV(4)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster2_core0_watchdog: wdt@c100000 {
+ cluster2_core0_watchdog: watchdog@c100000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc100000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -419,7 +419,7 @@ QORIQ_CLK_PLL_DIV(4)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster2_core1_watchdog: wdt@c110000 {
+ cluster2_core1_watchdog: watchdog@c110000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc110000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -429,7 +429,7 @@ QORIQ_CLK_PLL_DIV(4)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster3_core0_watchdog: wdt@c200000 {
+ cluster3_core0_watchdog: watchdog@c200000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc200000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -439,7 +439,7 @@ QORIQ_CLK_PLL_DIV(4)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster3_core1_watchdog: wdt@c210000 {
+ cluster3_core1_watchdog: watchdog@c210000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc210000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -449,7 +449,7 @@ QORIQ_CLK_PLL_DIV(4)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster4_core0_watchdog: wdt@c300000 {
+ cluster4_core0_watchdog: watchdog@c300000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc300000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
@@ -459,7 +459,7 @@ QORIQ_CLK_PLL_DIV(4)>,
clock-names = "wdog_clk", "apb_pclk";
};
- cluster4_core1_watchdog: wdt@c310000 {
+ cluster4_core1_watchdog: watchdog@c310000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc310000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
--
2.34.1
next prev parent reply other threads:[~2024-06-26 20:26 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-26 20:25 [PATCH v2 00/13] arm64: dts: layerscaple: clean up some simple CHECK_WARNING Frank Li
2024-06-26 20:25 ` [PATCH v2 01/13] arm64: dts: layerscape: rename node 'timer' as 'rtc' Frank Li
2024-06-26 20:28 ` [PATCH v2 00/13] arm64: dts: layerscaple: clean up some simple CHECK_WARNING Frank Li
2024-06-27 10:37 ` Shawn Guo
2024-06-26 20:25 ` [PATCH v2 02/13] arm64: dts: layerscape: add platform special compatible string for gpio Frank Li
2024-07-01 16:43 ` Rob Herring
2024-07-01 18:51 ` Frank Li
2024-06-26 20:25 ` [PATCH v2 03/13] arm64: dts: fsl-lx2160a: fix #address-cells for pinctrl-single Frank Li
2024-06-26 20:25 ` [PATCH v2 04/13] arm64: dts: fsl-ls1012a: remove property 'snps,host-vbus-glitches' Frank Li
2024-06-26 20:25 ` [PATCH v2 05/13] arm64: dts: layerscape: replace node name 'nor' with 'flash' Frank Li
2024-06-26 20:25 ` [PATCH v2 06/13] arm64: dts: layerscape: remove compatible string 'fsl,fman-xmdio' for fman3 Frank Li
2024-06-26 20:25 ` [PATCH v2 07/13] arm64: dts: layerscaple: add #dma-cells for qdma Frank Li
2024-06-27 17:17 ` Rob Herring
2024-06-27 17:22 ` Rob Herring
2024-06-27 18:27 ` Frank Li
2024-06-28 2:34 ` Shawn Guo
2024-06-26 20:25 ` Frank Li [this message]
2024-06-26 20:25 ` [PATCH v2 09/13] arm64: dts: layerscape: change pcie interrupt order Frank Li
2024-06-26 20:25 ` [PATCH v2 10/13] arm64: dts: layerscape: rename aux_bus to aux-bus Frank Li
2024-06-26 20:25 ` [PATCH v2 11/13] arm64: dts: fsl-ls1043a: remove unused clk-name at watchdog node Frank Li
2024-06-26 20:25 ` [PATCH v2 12/13] arm64: dts: fsl-ls1046a: rename thermal node name Frank Li
2024-06-26 20:25 ` [PATCH v2 13/13] arm64: dts: layerscape: rename b(q)man-portals to b(q)man-portals-bus Frank Li
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