From: James Raphael Tiovalen <jamestiotio@gmail.com>
To: kvm-riscv@lists.infradead.org
Subject: [kvm-unit-tests PATCH v6 2/5] riscv: Update exception cause list
Date: Tue, 30 Jul 2024 14:18:17 +0800 [thread overview]
Message-ID: <20240730061821.43811-3-jamestiotio@gmail.com> (raw)
In-Reply-To: <20240730061821.43811-1-jamestiotio@gmail.com>
Update the list of exception and interrupt causes to follow the latest
RISC-V privileged ISA specification (version 20240411 section 18.6.1).
Reviewed-by: Andrew Jones <andrew.jones@linux.dev>
Signed-off-by: James Raphael Tiovalen <jamestiotio@gmail.com>
---
lib/riscv/asm/csr.h | 10 ++++++++++
lib/riscv/asm/processor.h | 2 +-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/lib/riscv/asm/csr.h b/lib/riscv/asm/csr.h
index d6909d93..ba810c9f 100644
--- a/lib/riscv/asm/csr.h
+++ b/lib/riscv/asm/csr.h
@@ -36,6 +36,16 @@
#define EXC_VIRTUAL_INST_FAULT 22
#define EXC_STORE_GUEST_PAGE_FAULT 23
+/* Interrupt causes */
+#define IRQ_S_SOFT 1
+#define IRQ_VS_SOFT 2
+#define IRQ_S_TIMER 5
+#define IRQ_VS_TIMER 6
+#define IRQ_S_EXT 9
+#define IRQ_VS_EXT 10
+#define IRQ_S_GEXT 12
+#define IRQ_PMU_OVF 13
+
#ifndef __ASSEMBLY__
#define csr_swap(csr, val) \
diff --git a/lib/riscv/asm/processor.h b/lib/riscv/asm/processor.h
index 6451adb5..4c9ad968 100644
--- a/lib/riscv/asm/processor.h
+++ b/lib/riscv/asm/processor.h
@@ -4,7 +4,7 @@
#include <asm/csr.h>
#include <asm/ptrace.h>
-#define EXCEPTION_CAUSE_MAX 16
+#define EXCEPTION_CAUSE_MAX 24
#define INTERRUPT_CAUSE_MAX 16
typedef void (*exception_fn)(struct pt_regs *);
--
2.43.0
WARNING: multiple messages have this Message-ID (diff)
From: James Raphael Tiovalen <jamestiotio@gmail.com>
To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org
Cc: andrew.jones@linux.dev, atishp@rivosinc.com,
cade.richard@berkeley.edu,
James Raphael Tiovalen <jamestiotio@gmail.com>
Subject: [kvm-unit-tests PATCH v6 2/5] riscv: Update exception cause list
Date: Tue, 30 Jul 2024 14:18:17 +0800 [thread overview]
Message-ID: <20240730061821.43811-3-jamestiotio@gmail.com> (raw)
In-Reply-To: <20240730061821.43811-1-jamestiotio@gmail.com>
Update the list of exception and interrupt causes to follow the latest
RISC-V privileged ISA specification (version 20240411 section 18.6.1).
Reviewed-by: Andrew Jones <andrew.jones@linux.dev>
Signed-off-by: James Raphael Tiovalen <jamestiotio@gmail.com>
---
lib/riscv/asm/csr.h | 10 ++++++++++
lib/riscv/asm/processor.h | 2 +-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/lib/riscv/asm/csr.h b/lib/riscv/asm/csr.h
index d6909d93..ba810c9f 100644
--- a/lib/riscv/asm/csr.h
+++ b/lib/riscv/asm/csr.h
@@ -36,6 +36,16 @@
#define EXC_VIRTUAL_INST_FAULT 22
#define EXC_STORE_GUEST_PAGE_FAULT 23
+/* Interrupt causes */
+#define IRQ_S_SOFT 1
+#define IRQ_VS_SOFT 2
+#define IRQ_S_TIMER 5
+#define IRQ_VS_TIMER 6
+#define IRQ_S_EXT 9
+#define IRQ_VS_EXT 10
+#define IRQ_S_GEXT 12
+#define IRQ_PMU_OVF 13
+
#ifndef __ASSEMBLY__
#define csr_swap(csr, val) \
diff --git a/lib/riscv/asm/processor.h b/lib/riscv/asm/processor.h
index 6451adb5..4c9ad968 100644
--- a/lib/riscv/asm/processor.h
+++ b/lib/riscv/asm/processor.h
@@ -4,7 +4,7 @@
#include <asm/csr.h>
#include <asm/ptrace.h>
-#define EXCEPTION_CAUSE_MAX 16
+#define EXCEPTION_CAUSE_MAX 24
#define INTERRUPT_CAUSE_MAX 16
typedef void (*exception_fn)(struct pt_regs *);
--
2.43.0
next prev parent reply other threads:[~2024-07-30 6:18 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-30 6:18 [kvm-unit-tests PATCH v6 0/5] riscv: sbi: Add support to test timer extension James Raphael Tiovalen
2024-07-30 6:18 ` James Raphael Tiovalen
2024-07-30 6:18 ` [kvm-unit-tests PATCH v6 1/5] riscv: Extend exception handling support for interrupts James Raphael Tiovalen
2024-07-30 6:18 ` James Raphael Tiovalen
2024-07-30 6:18 ` James Raphael Tiovalen [this message]
2024-07-30 6:18 ` [kvm-unit-tests PATCH v6 2/5] riscv: Update exception cause list James Raphael Tiovalen
2024-07-30 6:18 ` [kvm-unit-tests PATCH v6 3/5] riscv: Add method to probe for SBI extensions James Raphael Tiovalen
2024-07-30 6:18 ` James Raphael Tiovalen
2024-07-30 6:18 ` [kvm-unit-tests PATCH v6 4/5] riscv: Add some delay and timer routines James Raphael Tiovalen
2024-07-30 6:18 ` James Raphael Tiovalen
2024-07-30 6:18 ` [kvm-unit-tests PATCH v6 5/5] riscv: sbi: Add test for timer extension James Raphael Tiovalen
2024-07-30 6:18 ` James Raphael Tiovalen
2024-08-02 8:36 ` Andrew Jones
2024-08-02 8:36 ` Andrew Jones
2024-08-02 12:23 ` James R T
2024-08-02 12:23 ` James R T
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240730061821.43811-3-jamestiotio@gmail.com \
--to=jamestiotio@gmail.com \
--cc=kvm-riscv@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.