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From: Simon Horman <horms@kernel.org>
To: Grzegorz Nitka <grzegorz.nitka@intel.com>
Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org,
	anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com,
	Karol Kolacinski <karol.kolacinski@intel.com>
Subject: Re: [Intel-wired-lan] [PATCH iwl-next v1 3/3] ice: E825C PHY register cleanup
Date: Fri, 7 Feb 2025 10:07:18 +0000	[thread overview]
Message-ID: <20250207100718.GM554665@kernel.org> (raw)
In-Reply-To: <20250206083655.3005151-4-grzegorz.nitka@intel.com>

On Thu, Feb 06, 2025 at 09:36:55AM +0100, Grzegorz Nitka wrote:
> From: Karol Kolacinski <karol.kolacinski@intel.com>
> 
> Minor PTP register refactor, including logical grouping E825C 1-step
> timestamping registers. Remove unused register definitions
> (PHY_REG_GPCS_BITSLIP, PHY_REG_REVISION).
> Also, apply preferred GENMASK macro (instead of ICE_M) for register
> fields definition affected by this patch.
> 
> Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>

In reference to my comment on patch 1/3, this patch is also doing sevearl
things. But I think that is fine because: they are all cleanups; they are
somewhat related to each other; and overall the patch is still not so long.

Reviewed-by: Simon Horman <horms@kernel.org>

...

WARNING: multiple messages have this Message-ID (diff)
From: Simon Horman <horms@kernel.org>
To: Grzegorz Nitka <grzegorz.nitka@intel.com>
Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org,
	anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com,
	Karol Kolacinski <karol.kolacinski@intel.com>
Subject: Re: [PATCH iwl-next v1 3/3] ice: E825C PHY register cleanup
Date: Fri, 7 Feb 2025 10:07:18 +0000	[thread overview]
Message-ID: <20250207100718.GM554665@kernel.org> (raw)
In-Reply-To: <20250206083655.3005151-4-grzegorz.nitka@intel.com>

On Thu, Feb 06, 2025 at 09:36:55AM +0100, Grzegorz Nitka wrote:
> From: Karol Kolacinski <karol.kolacinski@intel.com>
> 
> Minor PTP register refactor, including logical grouping E825C 1-step
> timestamping registers. Remove unused register definitions
> (PHY_REG_GPCS_BITSLIP, PHY_REG_REVISION).
> Also, apply preferred GENMASK macro (instead of ICE_M) for register
> fields definition affected by this patch.
> 
> Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>

In reference to my comment on patch 1/3, this patch is also doing sevearl
things. But I think that is fine because: they are all cleanups; they are
somewhat related to each other; and overall the patch is still not so long.

Reviewed-by: Simon Horman <horms@kernel.org>

...

  reply	other threads:[~2025-02-07 10:07 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-06  8:36 [Intel-wired-lan] [PATCH iwl-next v1 0/3] E825C PTP cleanup Grzegorz Nitka
2025-02-06  8:36 ` Grzegorz Nitka
2025-02-06  8:36 ` [Intel-wired-lan] [PATCH iwl-next v1 1/3] ice: Add sync delay for E825C Grzegorz Nitka
2025-02-06  8:36   ` Grzegorz Nitka
2025-02-07 10:03   ` [Intel-wired-lan] " Simon Horman
2025-02-07 10:03     ` Simon Horman
2025-02-10 10:54     ` [Intel-wired-lan] " Nitka, Grzegorz
2025-02-10 10:54       ` Nitka, Grzegorz
2025-02-06  8:36 ` [Intel-wired-lan] [PATCH iwl-next v1 2/3] ice: Refactor E825C PHY registers info struct Grzegorz Nitka
2025-02-06  8:36   ` Grzegorz Nitka
2025-02-07 10:03   ` [Intel-wired-lan] " Simon Horman
2025-02-07 10:03     ` Simon Horman
2025-02-07 10:05     ` [Intel-wired-lan] " Simon Horman
2025-02-07 10:05       ` Simon Horman
2025-02-10 11:05       ` [Intel-wired-lan] " Nitka, Grzegorz
2025-02-10 11:05         ` Nitka, Grzegorz
2025-02-06  8:36 ` [Intel-wired-lan] [PATCH iwl-next v1 3/3] ice: E825C PHY register cleanup Grzegorz Nitka
2025-02-06  8:36   ` Grzegorz Nitka
2025-02-07 10:07   ` Simon Horman [this message]
2025-02-07 10:07     ` Simon Horman

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