Re: [PATCH] iommu/amd: Add Secure ATS support

[Jason Gunthorpe <jgg@ziepe.ca>]

On Wed, Feb 26, 2025 at 02:50:57AM +0000, Tian, Kevin wrote:
> > Maybe it is both 2 and 3 if the GCR3 PASID 0 is setup to not translate
> > but do identity?
> 
> yes but conceptually it's still more a #2 thing from host p.o.v. The host
> still sees a nested configuration no matter how the guest configures
> each GCR3 entry.

AMD doesn't even support nesting now, so if this patch works it means
it is scenario #2.

> Not exactly. They are functionally different but serving the same purpose
> to the user. From user p.o.v. it's sufficient to have a general flag for sats
> when allocating a domain. The underlying driver decides whether such
> flag is supported based on the domain type and the associated device,
> just like checks on other existing flags.

We already discussed that #4 works with CXL and #2/#3 don't. They also
tolerate different PCI topology settings. The core code needs to know
what it is getting into and in the case of ARM it needs to instruct
the driver which of the two options to use.

#2/#3 seems to be prefered when possible because it uses less memory,
has less invalidation overhead, and apparently about the same
performance according to the SMMU spec.

So I think two flags is the right starting point..

Jason