From: Vasant Hegde <vasant.hegde@amd.com>
To: "Tian, Kevin" <kevin.tian@intel.com>,
Jason Gunthorpe <jgg@ziepe.ca>,
Robin Murphy <robin.murphy@arm.com>
Cc: "Liu, Yi L" <yi.l.liu@intel.com>,
"iommu@lists.linux.dev" <iommu@lists.linux.dev>,
"joro@8bytes.org" <joro@8bytes.org>,
"will@kernel.org" <will@kernel.org>,
"suravee.suthikulpanit@amd.com" <suravee.suthikulpanit@amd.com>
Subject: Re: [PATCH] iommu/amd: Add Secure ATS support
Date: Thu, 27 Feb 2025 21:34:01 +0530 [thread overview]
Message-ID: <cc4cf4ae-2d29-4747-b655-df841661b82a@amd.com> (raw)
In-Reply-To: <BN9PR11MB5276B090C61D1F059538AF7B8CC22@BN9PR11MB5276.namprd11.prod.outlook.com>
Kevin, Jason,
On 2/26/2025 12:40 PM, Tian, Kevin wrote:
>> From: Vasant Hegde <vasant.hegde@amd.com>
>> Sent: Wednesday, February 26, 2025 12:47 PM
>>
>>>
>>> 3) TA is an IOVA and the IOMMU runs it through the full translation
>>> to validate it. ATS is just used to signal non-present
>>
>> Yes. AMD does this when Host page table is configured.
>
> Here 'signal non-present' implies to support PRI.
>
> But...
>
>>
>> We need to consider various scenarios. For AMD:
>> - Currently on baremetal, we cannot enable SVA and Secure ATS
>
> ... here it says SVA/SATS are incompatible. Any more background?
Sorry. I should have explained it better.
To support SVA (PASID/PRI), we have to configure domain with AMD Guest (v2) Page
table and host page table will not be set (DTE[Mode]=0).
GVA -> GPA contains translation and GPA = SPA.
On ATS request it will send GPA back to device (which is actually a SPA). We can
support secure ATS, but ATS response will contain the SPA.
-Vasant
next prev parent reply other threads:[~2025-02-27 16:04 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-25 10:58 [PATCH] iommu/amd: Add Secure ATS support Vasant Hegde
2025-02-25 12:30 ` Yi Liu
2025-02-25 13:18 ` Robin Murphy
2025-02-25 13:57 ` Yi Liu
2025-02-25 14:55 ` Jason Gunthorpe
2025-02-26 1:09 ` Yi Liu
2025-02-26 1:13 ` Jason Gunthorpe
2025-02-26 1:27 ` Yi Liu
2025-02-26 2:52 ` Tian, Kevin
2025-02-26 1:12 ` Tian, Kevin
2025-02-26 1:17 ` Jason Gunthorpe
2025-02-26 2:50 ` Tian, Kevin
2025-02-26 12:57 ` Jason Gunthorpe
2025-02-26 7:05 ` Tian, Kevin
2025-02-26 12:58 ` Jason Gunthorpe
2025-02-27 15:27 ` Vasant Hegde
2025-02-28 6:32 ` Tian, Kevin
2025-02-28 7:43 ` Yi Liu
2025-02-28 8:30 ` Vasant Hegde
2025-02-28 8:47 ` Yi Liu
2025-02-28 8:47 ` Vasant Hegde
2025-03-02 8:10 ` Yi Liu
2025-03-03 3:00 ` Tian, Kevin
2025-03-04 6:58 ` Yi Liu
2025-03-03 11:42 ` Vasant Hegde
2025-03-05 3:24 ` Tian, Kevin
2025-03-10 17:07 ` Vasant Hegde
2025-03-12 7:15 ` Tian, Kevin
2025-03-17 8:56 ` Vasant Hegde
2025-04-07 5:28 ` Tian, Kevin
2025-03-03 18:38 ` Jason Gunthorpe
2025-03-04 2:16 ` Baolu Lu
2025-03-04 14:18 ` Jason Gunthorpe
2025-03-05 2:45 ` Baolu Lu
2025-03-05 2:46 ` Tian, Kevin
2025-03-04 6:50 ` Yi Liu
2025-03-04 10:46 ` Vasant Hegde
2025-03-04 14:20 ` Jason Gunthorpe
2025-03-05 2:50 ` Tian, Kevin
2025-03-05 17:22 ` Jason Gunthorpe
2025-03-06 2:41 ` Tian, Kevin
2025-03-14 12:54 ` Yi Liu
2025-03-04 10:15 ` Vasant Hegde
2025-03-04 14:24 ` Jason Gunthorpe
2025-03-10 16:35 ` Vasant Hegde
2025-03-14 12:09 ` Yi Liu
2025-03-19 19:52 ` Jason Gunthorpe
2025-03-14 12:22 ` Yi Liu
2025-02-28 8:26 ` Vasant Hegde
2025-02-28 14:56 ` Jason Gunthorpe
2025-03-03 2:55 ` Tian, Kevin
2025-03-10 14:13 ` Vasant Hegde
2025-03-12 6:55 ` Tian, Kevin
2025-03-03 11:56 ` Vasant Hegde
2025-02-26 4:47 ` Vasant Hegde
2025-02-26 7:10 ` Tian, Kevin
2025-02-26 13:01 ` Jason Gunthorpe
2025-02-26 22:42 ` Jerry Snitselaar
2025-02-27 16:04 ` Vasant Hegde [this message]
2025-02-28 0:04 ` Jason Gunthorpe
2025-02-28 6:18 ` Tian, Kevin
2025-02-28 1:47 ` Baolu Lu
2025-02-28 6:15 ` Tian, Kevin
2025-02-28 8:53 ` Vasant Hegde
2025-02-28 14:53 ` Jason Gunthorpe
2025-03-03 2:43 ` Tian, Kevin
2025-02-28 8:38 ` Vasant Hegde
2025-02-26 4:33 ` Vasant Hegde
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