[PATCH 8/8] lib: sbi_hart: properly reset Ssstateen

["Radim Krčmář" <rkrcmar@ventanamicro.com>]

sstateen* and hstateen* CSRs must be zeroed by M-mode if the mstateen*
registers are missing, to avoid security issues.

Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com>
---
 lib/sbi/sbi_hart.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index bc0a73d1298d..0f61e9cd1c98 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -114,12 +114,22 @@ static void mstatus_init(struct sbi_scratch *scratch)
 		csr_write64(CSR_MSTATEEN1, SMSTATEEN_STATEN);
 		csr_write64(CSR_MSTATEEN2, SMSTATEEN_STATEN);
 		csr_write64(CSR_MSTATEEN3, SMSTATEEN_STATEN);
+	}
 
-		if (misa_extension('S'))
+	if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SMSTATEEN) ||
+	    sbi_hart_has_extension(scratch, SBI_HART_EXT_SSSTATEEN)) {
+		if (misa_extension('S')) {
 			csr_write(CSR_SSTATEEN0, 0);
-
-		if (misa_extension('H'))
+			csr_write(CSR_SSTATEEN1, 0);
+			csr_write(CSR_SSTATEEN2, 0);
+			csr_write(CSR_SSTATEEN3, 0);
+		}
+		if (misa_extension('H')) {
 			csr_write64(CSR_HSTATEEN0, (uint64_t)0);
+			csr_write64(CSR_HSTATEEN1, (uint64_t)0);
+			csr_write64(CSR_HSTATEEN2, (uint64_t)0);
+			csr_write64(CSR_HSTATEEN3, (uint64_t)0);
+		}
 	}
 
 	if (sbi_hart_priv_version(scratch) >= SBI_HART_PRIV_VER_1_12) {
-- 
2.48.1


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