Re: [PATCH 1/8] lib: sbi: add 64 bit csr macros

From: "Radim Krčmář" <rkrcmar@ventanamicro.com>
To: "Anup Patel" <anup@brainfault.org>
Cc: <opensbi@lists.infradead.org>
Subject: Re: [PATCH 1/8] lib: sbi: add 64 bit csr macros
Date: Mon, 28 Apr 2025 15:48:20 +0200	[thread overview]
Message-ID: <D9IBI128G7PQ.10FJADCTGTA4T@ventanamicro.com> (raw)
In-Reply-To: <CAAhSdy3L1_FFuy-UzViRdCWSQeZc6v_fBhwbHb9oT7Ei4FA0KQ@mail.gmail.com>

2025-04-28T17:58:31+05:30, Anup Patel <anup@brainfault.org>:
> On Tue, Apr 15, 2025 at 8:13 PM Radim Krčmář <rkrcmar@ventanamicro.com> wrote:
>>
>> Most CSRs are XLEN bits wide, but some are 64 bit, so rv32 needs two
>> accesses, plaguing the code with ifdefs.
>>
>> Add new helpers that split 64 bit operation into two operations on rv32.
>>
>> The helpers don't use "csr + 0x10", but append "H" at the end of the csr
>> name to get a compile-time error when accessing a non 64 bit register.
>> This has the downside that you have to use the name when accessing them.
>> e.g. csr_read64(0x1234) or csr_read64(CSR_SATP) won't compile and the
>> error messages you get for these bugs are not straightforward.
>>
>> Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com>
>> ---
>> diff --git a/include/sbi/riscv_asm.h b/include/sbi/riscv_asm.h
>> @@ -156,6 +156,27 @@
>>                                      : "memory");                  \
>>         })
>>
>> +
>
> Redundant newline.

Oops, it will be gone in v2, thanks.

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