From: Nicholas Piggin <npiggin@gmail.com>
To: Gerd Hoffmann <kraxel@redhat.com>
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
qemu-devel@nongnu.org, "Kevin Wolf" <kwolf@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Fabiano Rosas" <farosas@suse.de>,
"Laurent Vivier" <lvivier@redhat.com>,
"Phil Dennis-Jordan" <phil@philjordan.eu>,
"Bernhard Beschow" <shentey@gmail.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH v4 09/22] hw/usb/hcd-xhci-pci: Make PCI device more configurable
Date: Fri, 2 May 2025 13:30:33 +1000 [thread overview]
Message-ID: <20250502033047.102465-10-npiggin@gmail.com> (raw)
In-Reply-To: <20250502033047.102465-1-npiggin@gmail.com>
To prepare to support another USB PCI Host Controller, make some PCI
configuration dynamic.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/usb/hcd-xhci-pci.h | 9 ++++
hw/usb/hcd-xhci-pci.c | 118 +++++++++++++++++++++++++++++++++---------
2 files changed, 103 insertions(+), 24 deletions(-)
diff --git a/hw/usb/hcd-xhci-pci.h b/hw/usb/hcd-xhci-pci.h
index 5b61ae84555..09aabae6e01 100644
--- a/hw/usb/hcd-xhci-pci.h
+++ b/hw/usb/hcd-xhci-pci.h
@@ -41,6 +41,15 @@ typedef struct XHCIPciState {
OnOffAuto msi;
OnOffAuto msix;
bool conditional_intr_mapping;
+ uint8_t cache_line_size;
+ uint8_t pm_cap_off;
+ uint8_t pcie_cap_off;
+ uint8_t msi_cap_off;
+ uint8_t msix_cap_off;
+ int msix_bar_nr;
+ uint64_t msix_bar_size;
+ uint32_t msix_table_off;
+ uint32_t msix_pba_off;
} XHCIPciState;
#endif
diff --git a/hw/usb/hcd-xhci-pci.c b/hw/usb/hcd-xhci-pci.c
index b93c80b09d8..911daf7e51f 100644
--- a/hw/usb/hcd-xhci-pci.c
+++ b/hw/usb/hcd-xhci-pci.c
@@ -32,9 +32,6 @@
#include "trace.h"
#include "qapi/error.h"
-#define OFF_MSIX_TABLE 0x3000
-#define OFF_MSIX_PBA 0x3800
-
static void xhci_pci_intr_update(XHCIState *xhci, int n, bool enable)
{
XHCIPciState *s = container_of(xhci, XHCIPciState, xhci);
@@ -120,6 +117,31 @@ static int xhci_pci_vmstate_post_load(void *opaque, int version_id)
return 0;
}
+static int xhci_pci_add_pm_capability(PCIDevice *pci_dev, uint8_t offset,
+ Error **errp)
+{
+ int err;
+
+ err = pci_add_capability(pci_dev, PCI_CAP_ID_PM, offset,
+ PCI_PM_SIZEOF, errp);
+ if (err < 0) {
+ return err;
+ }
+
+ pci_set_word(pci_dev->config + offset + PCI_PM_PMC,
+ PCI_PM_CAP_VER_1_2 |
+ PCI_PM_CAP_D1 | PCI_PM_CAP_D2 |
+ PCI_PM_CAP_PME_D0 | PCI_PM_CAP_PME_D1 |
+ PCI_PM_CAP_PME_D2 | PCI_PM_CAP_PME_D3hot);
+ pci_set_word(pci_dev->wmask + offset + PCI_PM_PMC, 0);
+ pci_set_word(pci_dev->config + offset + PCI_PM_CTRL,
+ PCI_PM_CTRL_NO_SOFT_RESET);
+ pci_set_word(pci_dev->wmask + offset + PCI_PM_CTRL,
+ PCI_PM_CTRL_STATE_MASK);
+
+ return 0;
+}
+
static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp)
{
int ret;
@@ -128,7 +150,7 @@ static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp)
dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */
dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
- dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
+ dev->config[PCI_CACHE_LINE_SIZE] = s->cache_line_size;
dev->config[0x60] = 0x30; /* release number */
object_property_set_link(OBJECT(&s->xhci), "host", OBJECT(s), NULL);
@@ -144,40 +166,78 @@ static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp)
s->xhci.nec_quirks = true;
}
- if (s->msi != ON_OFF_AUTO_OFF) {
- ret = msi_init(dev, 0x70, s->xhci.numintrs, true, false, &err);
- /*
- * Any error other than -ENOTSUP(board's MSI support is broken)
- * is a programming error
- */
- assert(!ret || ret == -ENOTSUP);
- if (ret && s->msi == ON_OFF_AUTO_ON) {
- /* Can't satisfy user's explicit msi=on request, fail */
- error_append_hint(&err, "You have to use msi=auto (default) or "
- "msi=off with this machine type.\n");
+ if (s->pm_cap_off) {
+ if (xhci_pci_add_pm_capability(dev, s->pm_cap_off, &err)) {
error_propagate(errp, err);
return;
}
- assert(!err || s->msi == ON_OFF_AUTO_AUTO);
- /* With msi=auto, we fall back to MSI off silently */
- error_free(err);
}
+
+ if (s->msi != ON_OFF_AUTO_OFF) {
+ ret = msi_init(dev, s->msi_cap_off, s->xhci.numintrs,
+ true, false, &err);
+ if (ret) {
+ if (ret != -ENOTSUP) {
+ /* Programming error */
+ error_propagate(errp, err);
+ return;
+ }
+ if (s->msi == ON_OFF_AUTO_ON) {
+ /* Can't satisfy user's explicit msi=on request, fail */
+ error_append_hint(&err, "You have to use msi=auto (default) "
+ "or msi=off with this machine type.\n");
+ error_propagate(errp, err);
+ return;
+ }
+ error_free(err);
+ err = NULL; /* With msi=auto, we fall back to MSI off silently */
+ }
+ }
+
pci_register_bar(dev, 0,
PCI_BASE_ADDRESS_SPACE_MEMORY |
PCI_BASE_ADDRESS_MEM_TYPE_64,
&s->xhci.mem);
if (pci_bus_is_express(pci_get_bus(dev))) {
- ret = pcie_endpoint_cap_init(dev, 0xa0);
+ ret = pcie_endpoint_cap_init(dev, s->pcie_cap_off);
assert(ret > 0);
}
if (s->msix != ON_OFF_AUTO_OFF) {
- /* TODO check for errors, and should fail when msix=on */
- msix_init(dev, s->xhci.numintrs,
- &s->xhci.mem, 0, OFF_MSIX_TABLE,
- &s->xhci.mem, 0, OFF_MSIX_PBA,
- 0x90, NULL);
+ MemoryRegion *msix_bar = &s->xhci.mem;
+
+ if (s->msix_bar_nr != 0) {
+ memory_region_init(&dev->msix_exclusive_bar, OBJECT(dev),
+ "xhci-msix", s->msix_bar_size);
+ msix_bar = &dev->msix_exclusive_bar;
+ pci_register_bar(dev, s->msix_bar_nr,
+ PCI_BASE_ADDRESS_SPACE_MEMORY |
+ PCI_BASE_ADDRESS_MEM_TYPE_64,
+ msix_bar);
+ }
+
+ ret = msix_init(dev, s->xhci.numintrs,
+ msix_bar, s->msix_bar_nr, s->msix_table_off,
+ msix_bar, s->msix_bar_nr, s->msix_pba_off,
+ s->msix_cap_off, &err);
+ if (ret) {
+ if (ret != -ENOTSUP) {
+ /* Programming error */
+ error_propagate(errp, err);
+ return;
+ }
+ if (s->msix == ON_OFF_AUTO_ON) {
+ /* Can't satisfy user's explicit msix=on request, fail */
+ error_append_hint(&err, "You have to use msix=auto (default) "
+ "or msix=off with this machine type.\n");
+ error_propagate(errp, err);
+ return;
+ }
+ error_free(err);
+ err = NULL; /* With msix=auto, we fall back to MSI-X off silently */
+ /* Should we unregister BAR and memory region here? */
+ }
}
s->xhci.as = pci_get_address_space(dev);
}
@@ -214,6 +274,16 @@ static void xhci_instance_init(Object *obj)
PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS;
object_initialize_child(obj, "xhci-core", &s->xhci, TYPE_XHCI);
qdev_alias_all_properties(DEVICE(&s->xhci), obj);
+
+ s->cache_line_size = 0x10;
+ s->pm_cap_off = 0;
+ s->pcie_cap_off = 0xa0;
+ s->msi_cap_off = 0x70;
+ s->msix_cap_off = 0x90;
+ s->msix_bar_nr = 0;
+ s->msix_bar_size = 0;
+ s->msix_table_off = 0x3000;
+ s->msix_pba_off = 0x3800;
}
static const Property xhci_pci_properties[] = {
--
2.47.1
next prev parent reply other threads:[~2025-05-02 3:33 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-02 3:30 [PATCH v4 00/22] usb/xhci and usb/msd improvements and tests Nicholas Piggin
2025-05-02 3:30 ` [PATCH v4 01/22] hw/usb/xhci: Move HCD constants to a header and add register constants Nicholas Piggin
2025-05-12 12:25 ` Peter Maydell
2025-05-02 3:30 ` [PATCH v4 02/22] hw/usb/xhci: Rename and move HCD register region constants to header Nicholas Piggin
2025-05-12 12:29 ` Peter Maydell
2025-05-02 3:30 ` [PATCH v4 03/22] tests/qtest/xhci: test the qemu-xhci device Nicholas Piggin
2025-05-19 13:54 ` Fabiano Rosas
2025-05-02 3:30 ` [PATCH v4 04/22] tests/qtest/xhci: Add controller and device setup and ring tests Nicholas Piggin
2025-05-19 14:03 ` Fabiano Rosas
2025-05-02 3:30 ` [PATCH v4 05/22] tests/qtest/xhci: Add basic USB Mass Storage tests Nicholas Piggin
2025-05-19 14:44 ` Fabiano Rosas
2025-05-02 3:30 ` [PATCH v4 06/22] hw/usb/xhci: Support TR NOOP commands Nicholas Piggin
2025-05-12 13:06 ` Peter Maydell
2025-05-02 3:30 ` [PATCH v4 07/22] tests/qtest/xhci: add a test for " Nicholas Piggin
2025-05-19 14:54 ` Fabiano Rosas
2025-05-02 3:30 ` [PATCH v4 08/22] tests/qtest/usb-hcd-xhci: Deliver msix interrupts Nicholas Piggin
2025-05-02 8:24 ` Philippe Mathieu-Daudé
2025-05-05 1:05 ` Nicholas Piggin
2025-05-02 3:30 ` Nicholas Piggin [this message]
2025-05-12 13:12 ` [PATCH v4 09/22] hw/usb/hcd-xhci-pci: Make PCI device more configurable Peter Maydell
2025-05-02 3:30 ` [PATCH v4 10/22] hw/usb/hcd-xhci-pci: Add TI TUSB73X0 XHCI controller model Nicholas Piggin
2025-05-12 13:15 ` Peter Maydell
2025-05-02 3:30 ` [PATCH v4 11/22] usb/msd: Split in and out packet handling Nicholas Piggin
2025-05-05 9:22 ` Kevin Wolf
2025-05-02 3:30 ` [PATCH v4 12/22] usb/msd: Ensure packet structure layout is correct Nicholas Piggin
2025-05-05 9:30 ` Kevin Wolf
2025-05-02 3:30 ` [PATCH v4 13/22] usb/msd: Improved handling of mass storage reset Nicholas Piggin
2025-05-02 3:30 ` [PATCH v4 14/22] usb/msd: Improve packet validation error logging Nicholas Piggin
2025-05-05 10:26 ` Kevin Wolf
2025-05-02 3:30 ` [PATCH v4 15/22] usb/msd: Allow CBW packet size greater than 31 Nicholas Piggin
2025-05-05 10:50 ` Kevin Wolf
2025-05-02 3:30 ` [PATCH v4 16/22] usb/msd: Split async packet tracking into data and csw Nicholas Piggin
2025-05-05 13:05 ` Kevin Wolf
2025-05-05 14:04 ` Kevin Wolf
2025-05-02 3:30 ` [PATCH v4 17/22] usb/msd: Add some additional assertions Nicholas Piggin
2025-05-02 3:30 ` [PATCH v4 18/22] usb/msd: Rename mode to cbw_state, and tweak names Nicholas Piggin
2025-05-02 3:30 ` [PATCH v4 19/22] usb/msd: Add NODATA CBW state Nicholas Piggin
2025-05-02 3:30 ` [PATCH v4 20/22] usb/msd: Permit a DATA-IN or CSW packet before CBW packet Nicholas Piggin
2025-05-02 3:30 ` [PATCH v4 21/22] tests/qtest/xhci: Test USB Mass Storage relaxed CSW order Nicholas Piggin
2025-05-19 15:03 ` Fabiano Rosas
2025-05-02 3:30 ` [PATCH v4 22/22] usb/msd: Add more tracing Nicholas Piggin
2025-05-05 2:03 ` [PATCH v4 00/22] usb/xhci and usb/msd improvements and tests Nicholas Piggin
2025-05-05 9:02 ` Kevin Wolf
2025-05-12 13:20 ` Peter Maydell
2025-05-12 15:33 ` Fabiano Rosas
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