[PATCH 0/3] riscv: Add double trap testing

From: "Clément Léger" <cleger@rivosinc.com>
To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org
Cc: "Clément Léger" <cleger@rivosinc.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Ved Shanbhogue" <ved@rivosinc.com>
Subject: [PATCH 0/3] riscv: Add double trap testing
Date: Fri, 23 May 2025 09:53:07 +0200	[thread overview]
Message-ID: <20250523075341.1355755-1-cleger@rivosinc.com> (raw)

Add a test that triggers double trap and verify that it's behavior
conforms to the spec. Also use SSE to verify that an SSE event is
correctly sent upon double trap.

In order to run this test, one can use the following command using an
upstream version of OpenSBI:

$ qemu-system-riscv64 \
	-M virt \
	-cpu max \
	-nographic -serial mon:stdio \
	-bios <opensbi>/fw_dynamic.bin \
	-kernel riscv/isa-dbltrp.flat

Clément Léger (3):
  lib/riscv: export FWFT functions
  lib/riscv: clear SDT when entering exception handling
  riscv: Add ISA double trap extension testing

 riscv/Makefile      |   1 +
 lib/riscv/asm/csr.h |   1 +
 lib/riscv/asm/sbi.h |   5 ++
 lib/riscv/sbi.c     |  20 +++++
 riscv/cstart.S      |   9 ++-
 riscv/isa-dbltrp.c  | 189 ++++++++++++++++++++++++++++++++++++++++++++
 riscv/sbi-fwft.c    |  49 ++++--------
 riscv/unittests.cfg |   5 ++
 8 files changed, 240 insertions(+), 39 deletions(-)
 create mode 100644 riscv/isa-dbltrp.c

-- 
2.49.0

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