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From: "Clément Léger" <cleger@rivosinc.com>
To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org
Cc: "Clément Léger" <cleger@rivosinc.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Ved Shanbhogue" <ved@rivosinc.com>
Subject: [PATCH 2/3] lib/riscv: clear SDT when entering exception handling
Date: Fri, 23 May 2025 09:53:09 +0200	[thread overview]
Message-ID: <20250523075341.1355755-3-cleger@rivosinc.com> (raw)
In-Reply-To: <20250523075341.1355755-1-cleger@rivosinc.com>

In order to avoid taking double trap once we have entered a trap and
saved everything, clear SDT at the end of entry. This is not exactly
required when double trap is disabled (probably most of the time), but
that's not harmful.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 riscv/cstart.S | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/riscv/cstart.S b/riscv/cstart.S
index 575f929b..a86f97f0 100644
--- a/riscv/cstart.S
+++ b/riscv/cstart.S
@@ -212,14 +212,15 @@ secondary_entry:
 	REG_S	t6, PT_T6(a0)			// x31
 	csrr	a1, CSR_SEPC
 	REG_S	a1, PT_EPC(a0)
-	csrr	a1, CSR_SSTATUS
-	REG_S	a1, PT_STATUS(a0)
 	csrr	a1, CSR_STVAL
 	REG_S	a1, PT_BADADDR(a0)
 	csrr	a1, CSR_SCAUSE
 	REG_S	a1, PT_CAUSE(a0)
 	REG_L	a1, PT_ORIG_A0(a0)
 	REG_S	a1, PT_A0(a0)
+	li t0, 	SR_SDT
+	csrrc 	a1, CSR_SSTATUS, t0
+	REG_S	a1, PT_STATUS(a0)
 .endm
 
 /*
@@ -227,6 +228,8 @@ secondary_entry:
  * Also restores a0.
  */
 .macro restore_context
+	REG_L	a1, PT_STATUS(a0)
+	csrw	CSR_SSTATUS, a1
 	REG_L	ra, PT_RA(a0)			// x1
 	REG_L	sp, PT_SP(a0)			// x2
 	REG_L	gp, PT_GP(a0)			// x3
@@ -260,8 +263,6 @@ secondary_entry:
 	REG_L	t6, PT_T6(a0)			// x31
 	REG_L	a1, PT_EPC(a0)
 	csrw	CSR_SEPC, a1
-	REG_L	a1, PT_STATUS(a0)
-	csrw	CSR_SSTATUS, a1
 	REG_L	a1, PT_BADADDR(a0)
 	csrw	CSR_STVAL, a1
 	REG_L	a1, PT_CAUSE(a0)
-- 
2.49.0


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WARNING: multiple messages have this Message-ID (diff)
From: "Clément Léger" <cleger@rivosinc.com>
To: kvm@vger.kernel.org, kvm-riscv@lists.infradead.org
Cc: "Clément Léger" <cleger@rivosinc.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Ved Shanbhogue" <ved@rivosinc.com>
Subject: [PATCH 2/3] lib/riscv: clear SDT when entering exception handling
Date: Fri, 23 May 2025 09:53:09 +0200	[thread overview]
Message-ID: <20250523075341.1355755-3-cleger@rivosinc.com> (raw)
In-Reply-To: <20250523075341.1355755-1-cleger@rivosinc.com>

In order to avoid taking double trap once we have entered a trap and
saved everything, clear SDT at the end of entry. This is not exactly
required when double trap is disabled (probably most of the time), but
that's not harmful.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 riscv/cstart.S | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/riscv/cstart.S b/riscv/cstart.S
index 575f929b..a86f97f0 100644
--- a/riscv/cstart.S
+++ b/riscv/cstart.S
@@ -212,14 +212,15 @@ secondary_entry:
 	REG_S	t6, PT_T6(a0)			// x31
 	csrr	a1, CSR_SEPC
 	REG_S	a1, PT_EPC(a0)
-	csrr	a1, CSR_SSTATUS
-	REG_S	a1, PT_STATUS(a0)
 	csrr	a1, CSR_STVAL
 	REG_S	a1, PT_BADADDR(a0)
 	csrr	a1, CSR_SCAUSE
 	REG_S	a1, PT_CAUSE(a0)
 	REG_L	a1, PT_ORIG_A0(a0)
 	REG_S	a1, PT_A0(a0)
+	li t0, 	SR_SDT
+	csrrc 	a1, CSR_SSTATUS, t0
+	REG_S	a1, PT_STATUS(a0)
 .endm
 
 /*
@@ -227,6 +228,8 @@ secondary_entry:
  * Also restores a0.
  */
 .macro restore_context
+	REG_L	a1, PT_STATUS(a0)
+	csrw	CSR_SSTATUS, a1
 	REG_L	ra, PT_RA(a0)			// x1
 	REG_L	sp, PT_SP(a0)			// x2
 	REG_L	gp, PT_GP(a0)			// x3
@@ -260,8 +263,6 @@ secondary_entry:
 	REG_L	t6, PT_T6(a0)			// x31
 	REG_L	a1, PT_EPC(a0)
 	csrw	CSR_SEPC, a1
-	REG_L	a1, PT_STATUS(a0)
-	csrw	CSR_SSTATUS, a1
 	REG_L	a1, PT_BADADDR(a0)
 	csrw	CSR_STVAL, a1
 	REG_L	a1, PT_CAUSE(a0)
-- 
2.49.0


  parent reply	other threads:[~2025-05-23  8:06 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-23  7:53 [PATCH 0/3] riscv: Add double trap testing Clément Léger
2025-05-23  7:53 ` Clément Léger
2025-05-23  7:53 ` [PATCH 1/3] lib/riscv: export FWFT functions Clément Léger
2025-05-23  7:53   ` Clément Léger
2025-06-03  7:14   ` Andrew Jones
2025-06-03  7:14     ` Andrew Jones
2025-05-23  7:53 ` Clément Léger [this message]
2025-05-23  7:53   ` [PATCH 2/3] lib/riscv: clear SDT when entering exception handling Clément Léger
2025-06-03  8:16   ` Andrew Jones
2025-06-03  8:16     ` Andrew Jones
2025-06-03  8:22     ` Clément Léger
2025-06-03  8:22       ` Clément Léger
2025-05-23  7:53 ` [PATCH 3/3] riscv: Add ISA double trap extension testing Clément Léger
2025-05-23  7:53   ` Clément Léger
2025-06-03  9:09   ` Andrew Jones
2025-06-03  9:09     ` Andrew Jones
2025-06-03  9:39     ` Clément Léger
2025-06-03  9:39       ` Clément Léger
2025-06-03  7:10 ` [PATCH 0/3] riscv: Add double trap testing Andrew Jones
2025-06-03  7:10   ` Andrew Jones
2025-06-03  7:52   ` Clément Léger
2025-06-03  7:52     ` Clément Léger

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