Re: [PATCH 5.10 03/14] arm64: insn: add encoders for atomic operations

[Sasha Levin <sashal@kernel.org>]

[ Sasha's backport helper bot ]

Hi,

✅ All tests passed successfully. No issues detected.
No action required from the submitter.

The upstream commit SHA1 provided is correct: fa1114d9eba5087ba5e81aab4c56f546995e6cd3

WARNING: Author mismatch between patch and upstream commit:
Backport author: Pu Lehui<pulehui@huaweicloud.com>
Commit author: Hou Tao<houtao1@huawei.com>

Status in newer kernel trees:
6.15.y | Present (exact SHA1)
6.14.y | Present (exact SHA1)
6.12.y | Present (exact SHA1)
6.6.y | Present (exact SHA1)
6.1.y | Present (exact SHA1)
5.15.y | Not found

Note: The patch differs from the upstream commit:
---
1:  fa1114d9eba50 ! 1:  5d6b22f0bb8f5 arm64: insn: add encoders for atomic operations
    @@ Metadata
      ## Commit message ##
         arm64: insn: add encoders for atomic operations
     
    +    [ Upstream commit fa1114d9eba5087ba5e81aab4c56f546995e6cd3 ]
    +
         It is a preparation patch for eBPF atomic supports under arm64. eBPF
         needs support atomic[64]_fetch_add, atomic[64]_[fetch_]{and,or,xor} and
         atomic[64]_{xchg|cmpxchg}. The ordering semantics of eBPF atomics are
    @@ Commit message
         Signed-off-by: Hou Tao <houtao1@huawei.com>
         Link: https://lore.kernel.org/r/20220217072232.1186625-3-houtao1@huawei.com
         Signed-off-by: Will Deacon <will@kernel.org>
    +    Signed-off-by: Pu Lehui <pulehui@huawei.com>
     
      ## arch/arm64/include/asm/insn.h ##
     @@ arch/arm64/include/asm/insn.h: enum aarch64_insn_ldst_type {
    @@ arch/arm64/include/asm/insn.h: enum aarch64_insn_adr_type {
      #define	__AARCH64_INSN_FUNCS(abbr, mask, val)				\
      static __always_inline bool aarch64_insn_is_##abbr(u32 code)		\
      {									\
    -@@ arch/arm64/include/asm/insn.h: __AARCH64_INSN_FUNCS(store_post,	0x3FE00C00, 0x38000400)
    - __AARCH64_INSN_FUNCS(load_post,	0x3FE00C00, 0x38400400)
    +@@ arch/arm64/include/asm/insn.h: __AARCH64_INSN_FUNCS(prfm,	0x3FC00000, 0x39800000)
    + __AARCH64_INSN_FUNCS(prfm_lit,	0xFF000000, 0xD8000000)
      __AARCH64_INSN_FUNCS(str_reg,	0x3FE0EC00, 0x38206800)
      __AARCH64_INSN_FUNCS(ldadd,	0x3F20FC00, 0x38200000)
     +__AARCH64_INSN_FUNCS(ldclr,	0x3F20FC00, 0x38201000)
    @@ arch/arm64/include/asm/insn.h: u32 aarch64_insn_gen_prefetch(enum aarch64_insn_r
      u32 aarch64_set_branch_offset(u32 insn, s32 offset);
      
     
    - ## arch/arm64/lib/insn.c ##
    -@@ arch/arm64/lib/insn.c: u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
    + ## arch/arm64/kernel/insn.c ##
    +@@ arch/arm64/kernel/insn.c: u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
      
      	switch (type) {
      	case AARCH64_INSN_LDST_LOAD_EX:
    @@ arch/arm64/lib/insn.c: u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_regi
      		break;
      	default:
      		pr_err("%s: unknown load/store exclusive encoding %d\n", __func__, type);
    -@@ arch/arm64/lib/insn.c: u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
    +@@ arch/arm64/kernel/insn.c: u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
      					    state);
      }
      
    @@ arch/arm64/lib/insn.c: u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_regi
      
      	switch (size) {
      	case AARCH64_INSN_SIZE_32:
    -@@ arch/arm64/lib/insn.c: u32 aarch64_insn_gen_ldadd(enum aarch64_insn_register result,
    +@@ arch/arm64/kernel/insn.c: u32 aarch64_insn_gen_ldadd(enum aarch64_insn_register result,
      
      	insn = aarch64_insn_encode_ldst_size(size, insn);
      
    @@ arch/arm64/lib/insn.c: u32 aarch64_insn_gen_ldadd(enum aarch64_insn_register res
      	insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn,
      					    result);
      
    -@@ arch/arm64/lib/insn.c: u32 aarch64_insn_gen_ldadd(enum aarch64_insn_register result,
    +@@ arch/arm64/kernel/insn.c: u32 aarch64_insn_gen_ldadd(enum aarch64_insn_register result,
      					    value);
      }
      
    @@ arch/arm64/lib/insn.c: u32 aarch64_insn_gen_ldadd(enum aarch64_insn_register res
      
      static u32 aarch64_insn_encode_prfm_imm(enum aarch64_insn_prfm_type type,
      					enum aarch64_insn_prfm_target target,
    -@@ arch/arm64/lib/insn.c: u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
    +@@ arch/arm64/kernel/insn.c: u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
      	insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, Rn);
      	return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, Rm);
      }
---

Results of testing on various branches:

| Branch                    | Patch Apply | Build Test |
|---------------------------|-------------|------------|
| stable/linux-5.15.y       |  Success    |  Success   |